CN104965468B - A kind of common interface module suitable for the multi-functional acquisition control devices of CPCI - Google Patents
A kind of common interface module suitable for the multi-functional acquisition control devices of CPCI Download PDFInfo
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- CN104965468B CN104965468B CN201510399042.1A CN201510399042A CN104965468B CN 104965468 B CN104965468 B CN 104965468B CN 201510399042 A CN201510399042 A CN 201510399042A CN 104965468 B CN104965468 B CN 104965468B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25314—Modular structure, modules
Abstract
The invention discloses a kind of common interface module suitable for the multi-functional acquisition control devices of CPCI.The module is set up on the premise of the motherboard hardware and firmware of the multi-functional acquisition control device based on cpci bus standard keep stable, unified hardware connectivity standards and communication protocol are defined by a kind of common interface module suitable for the multi-functional acquisition control devices of CPCI, so that meeting unified hardware and firewire standard based on the function daughter board that different demands are designed, daughter board work simultaneously on mainboard of a variety of difference in functionalitys is realized.
Description
Technical field
It is applicable the present invention relates to the collection of industrial measurement and control FIELD Data and the cross-species transferability of control device, more particularly to one kind
In the common interface module of the multi-functional acquisition control devices of CPCI.
Background technology
At present in industrial measurement and control field, the data collecting card application based on cpci bus standard is more and more extensive, has benefited from
Its stable mechanical structure, compared to pci bus standard better performance the features such as.Scene especially is controlled in large scale industry,
There is higher requirement to the stability of the precision, speed and harvester of data acquisition in itself, this occasion CPCI's is excellent
Point is just more highlighted.
The more commonly used mode of operation of CPCI data collecting cards is at present：Connected by pci bridge chip with cpci bus
Connect, realize the communication of board and host computer, the connection with PCI bridge chips is then realized by FPGA main control chips；Meanwhile,
Integrated functional module is also connected with fpga chip on data collecting card, realizes the connection of data collecting card and external interface, from
And complete the function such as the collection of signal or the conversion of data.
But plate body space and the resource constraint of fpga chip of CPCI data collecting cards are constrained to, when Industry Control is existing
When field is needed simultaneously using a variety of different acquisition functions, traditional data collecting card is difficult to meet requirement, may be accomplished by out
Send out data collecting card a variety of, cost increase, not easy care are not only caused, while the load of the backboard slot of industrial computer can also increase
Plus, it is unfavorable for the operating of whole system.Therefore, a kind of common interface module suitable for the multi-functional acquisition control devices of CPCI can
With the separation of optimized integration communication module and functional module so that while integrated a variety of functions on one piece of CPCI data collecting card
Module, these functional modules pass through the slot of general-purpose interface and the acquisition control as main control board using in the form of functional cards
Card connection, and using the mode of operation of multiple FPGA chip-in series, realize the read-write of data.
The present invention sets up hardware and the firmware guarantor in the mainboard of the multi-functional acquisition control device based on cpci bus standard
Keep steady on the premise of determining, pass through hardware defined in a kind of common interface module suitable for the multi-functional acquisition control devices of CPCI
Connection standard and communication protocol so that unified hardware and firewire standard are met based on the function daughter board designed by different demands,
Realize that the daughter board of a variety of difference in functionalitys works simultaneously on mainboard.The advantage of the module is, can be based on versatility interface
Standard designs different functional cards, and need not be changed as the acquisition and control card of mainboard so that whole device it is expansible
Property is greatly promoted.
The content of the invention
It is of the invention in order to realize integrated a variety of functions on the same acquisition control device based on cpci bus standard
Purpose is to provide a kind of common interface module suitable for the multi-functional acquisition control devices of CPCI, and it is more to be applied to CPCI by one kind
The common interface module of function acquisition control device defines unified hardware connectivity standards and communication protocol so that based on difference
The function daughter board of Demand Design meets unified hardware and firewire standard, realizes the daughter boards of a variety of difference in functionalitys on mainboard simultaneously
Work.
The purpose of the present invention is achieved through the following technical solutions：One kind is applied to the multi-functional acquisition control devices of CPCI
Common interface module, it is characterised in that：Multi-functional acquisition control device based on cpci bus standard is by adopting as mainboard
Collect control card and constituted as the functional cards of daughter board, mainboard and daughter board pass through suitable for the multi-functional acquisition control devices of CPCI
Common interface module is connected and communicated, and two pieces of daughter boards can be at most connected simultaneously on one piece of mainboard.The common interface module is hard
Mainly include on part：The fpga chip of mainboard, the general-purpose interface one of mainboard, the general-purpose interface two of mainboard, the external interface of mainboard,
The power module of mainboard；The fpga chip of daughter board, the general-purpose interface of daughter board, the functional module of daughter board.
The general-purpose interface one of described mainboard is made up of two parallel interface slots of A, B, and this two slots are 20* respectively
The male slot of 2 pins, the A slots of the general-purpose interface one of mainboard and the external interface of mainboard are connected, the B of the general-purpose interface one of mainboard
Fpga chip and the power module connection of slot and mainboard；The general-purpose interface two of described mainboard is connect by A, B two are parallel
Mouthful slot composition, this two slots are the male slot of 20*2 pins respectively, the A slots of the general-purpose interface two of mainboard and mainboard it is outer
Portion's interface connection, the B slots of the general-purpose interface two of mainboard and the fpga chip and power module of mainboard are connected.
The general-purpose interface of described daughter board is made up of two parallel interface slots of A, B, and this two slots are 20*2 respectively
The female slot of pin, the A slots of the general-purpose interface of daughter board and the functional module of daughter board are connected, the B slots of the general-purpose interface of daughter board
It is connected with the fpga chip of daughter board.
Daughter board is plugged on the general-purpose interface one of mainboard or general-purpose interface two by the general-purpose interface of daughter board, daughter board it is logical
The general-purpose interface one of mainboard or the A slots of general-purpose interface two, the B slots of the general-purpose interface of daughter board are connected with the A slots of interface
Connect the B slots of the corresponding general-purpose interface of mainboard.Voltage signal needed for each module of daughter board be all by common interface module by
What the power module of mainboard was provided, the general-purpose interface two that the fpga chip of mainboard passes through the general-purpose interface one of mainboard or mainboard
B slots can be connected with the FPGA of two pieces of daughter boards simultaneously and realize communication, and define clock signal position CLK, read control bit RD, write
Control bit WR, address enable position ADS these four control signals, the mode bit of 3, the address bit of 5 and the data bit of 8,
The power module of mainboard is provided by the B slots of the general-purpose interface one of mainboard or the general-purpose interface two of mainboard to daughter board simultaneously
1.2V, 2.5V, 3.3V, 5V ,+12V and -12V voltage signal.The external interface of described mainboard is 90 degree of the pins of SCSI 68
Female interface, is interconnected, the B slots of the general-purpose interface one of mainboard and the B slots of general-purpose interface two have 24 tunnels respectively with ancillary equipment
The external interface connection of signalling channel and mainboard.
A kind of common interface module suitable for the multi-functional acquisition control devices of CPCI, when hardware unit is connected with industrial computer
After, communicated between mainboard and daughter board according to the communication protocol of the common interface module：
(1) first, the function daughter board being connected on mainboard feeds back to the working condition of itself the FPGA chips of mainboard,
So that mainboard recognizes the corresponding functional attributes of the daughter board, daughter board is carried out by 3 mode bits defined on common interface module
Daughter board feedback of status, 3 mode bits can at most be defined not to be had on 8 kinds of different states, the general-purpose interface of 000 expression mainboard
There is connection daughter board, 001 to 111 expression 7 kinds of different function daughter boards, i.e. mainboard can at most recognize 7 kinds of different function daughter boards；
(2) after step (1) is completed, mainboard FPGA is by the address of the general-purpose interface one of mainboard and the general-purpose interface two of mainboard
Enable bit ADS sets low level, and host computer sends instruction to mainboard, and mainboard obtains the address of 8, and the highest order of the address is 0
The daughter board that the general-purpose interface one of gating mainboard is connected is represented, the highest order of the address is 1 general-purpose interface for representing gating mainboard
Two daughter boards connected；Address combination of the 2nd and the 3rd since highest order represents the classification of gating daughter board, have 00,
01st, 10,11 4 kind；Combination from the 4th to the 8th passes through the 5 of the general-purpose interface one of mainboard or the general-purpose interface two of mainboard
Bit address bit port is transmitted to daughter board, for selecting register defined in the FPGA of daughter board, can at most determine in the FPGA of daughter board
The register of adopted 32 different addresses, these registers are used to deposit the signal that the functional module of daughter board is gathered from ancillary equipment,
Or storage mainboard is transmitted to the data of daughter board by 8 data channel of general-purpose interface one or general-purpose interface two；
(3) after step (2) is completed, the fpga chip of mainboard is judged according to the action of host computer, if without new
Instruction, then return to (1)；If host computer passes on new instruction, the i.e. functional module to the daughter board of gating to carry out specifically
Operation, now mainboard is waited for, and the daughter board being strobed then enters step (4)；
(4) FPGA of mainboard is judged according to the instruction of host computer, if read operation, then the FPGA of mainboard passes through
The corresponding reading control bit RD of the daughter board of gating is set low level by common interface module, what the daughter board being strobed gathered functional module
Signal is stored in 32 registers defined in (2) using 8 bits as a unit, and then the FPGA of daughter board is according to main in (2)
5 bit address that plate is transmitted to daughter board search out the register of corresponding address, the signal of 8 bits stored in the register are passed through logical
Signal parallel is transmitted to the FPGA of mainboard with 8 data bit ports of interface module, host computer is uploaded to after processing；If
Write operation, then the FPGA of mainboard the corresponding control bit WR that writes of the daughter board of gating is set low by level by common interface module, then
Need the data write will by 8 data bit ports of common interface module in the form of 8 bit binary numbers host computer
It is transmitted to the FPGA of daughter board, 5 bit address that the FPGA of daughter board is transmitted to daughter board according to mainboard in (2) are searched out accordingly data parallel
The register of location, is stored data in 32 registers defined in (2), and is transmitted to the functional module of daughter board as needed,
Handled and exported；
(5) after step (4) is completed, an operation cycle terminates, and (1) is returned again and carries out next operation cycle.
Further, in 40 road pins of the A slots of the general-purpose interface one of described mainboard, No. 1, No. 4, No. 7, No. 10,
No. 13, No. 16, No. 19, No. 20, No. 21, No. 24, No. 27, No. 30, No. 33, No. 36, No. 39 and No. 40 pins are GND, other
24 road pins are signal position, are connected with external interface；In 40 road pins of the A slots of the general-purpose interface two of described mainboard, 1
Number, No. 4, No. 7, No. 10, No. 13, No. 16, No. 19, No. 20, No. 21, No. 24, No. 27, No. 30, No. 33, No. 36, No. 39 and 40
Number pin is GND, and other 24 road pins are signal position, are connected with external interface；
Further, in 40 road pins of the B slots of the general-purpose interface one of described mainboard, No. 4, No. 8, No. 11,14
Number, No. 16, No. 18, No. 20, No. 24, No. 28, No. 31, No. 34, No. 36, No. 38, No. 40 pins be GND, No. 15 pins are 3.3V
Voltage, No. 17 pins are that 2.5V voltages, No. 19 pins are that 1.2V voltages, No. 35 pins are that+12V voltages, No. 37 pins are -12V
Voltage, No. 39 pins are 5V voltages, and No. 1 pin is that clock signal position CLK, No. 2 pins are to read control bit RD, No. 3 pins to write
Control bit WR, No. 5 pins are address enable position ADS, and No. 6, No. 7 and No. 9 pins are mode bit, No. 10, No. 12, No. 13,21
Number, No. 22 pins be 5 bit address position, No. 23, No. 25, No. 26, No. 27, No. 29, No. 30, No. 32, No. 33 pins be 8 data
Position；In 40 road pins of the B slots of the general-purpose interface two of described mainboard, No. 4, No. 8, No. 11, No. 14, No. 16, No. 18,20
Number, No. 24, No. 28, No. 31, No. 34, No. 36, No. 38, No. 40 pins be GND, No. 15 pins are that 3.3V voltages, No. 17 pins are
2.5V voltages, No. 19 pins are that 1.2V voltages, No. 35 pins are that+12V voltages, No. 37 pins are that -12V voltages, No. 39 pins are
5V voltages, No. 1 pin is that clock signal position CLK, No. 2 pins are to read control bit RD, No. 3 pins to write control bit WR, No. 5 pins
For address enable position ADS, No. 6, No. 7 and No. 9 pins are mode bit, No. 10, No. 12, No. 13, No. 21, No. 22 pins be 5 ground
Location position, No. 23, No. 25, No. 26, No. 27, No. 29, No. 30, No. 32, No. 33 pins be 8 data bit.
Further, in 40 road pins of the A slots of the general-purpose interface of described daughter board, No. 1, No. 4, No. 7, No. 10,13
Number, No. 16, No. 19, No. 20, No. 21, No. 24, No. 27, No. 30, No. 33, No. 36, No. 39 and No. 40 pins be GND, other 24
Road pin is signal position, is connected with external interface；
Further, in 40 road pins of the B slots of the general-purpose interface of described daughter board, No. 4, No. 8, No. 11, No. 14,
No. 16, No. 18, No. 20, No. 24, No. 28, No. 31, No. 34, No. 36, No. 38, No. 40 pins be GND, No. 15 pins are 3.3V electricity
Pressure, No. 17 pins are that 2.5V voltages, No. 19 pins are that 1.2V voltages, No. 35 pins be that+12V voltages, No. 37 pins are -12V electric
Pressure, No. 39 pins are 5V voltages, and No. 1 pin is that clock signal position CLK, No. 2 pins are to read control bit RD, No. 3 pins to write control
Position WR processed, No. 5 pins are address enable position ADS, and No. 6, No. 7 and No. 9 pins are mode bit, No. 10, No. 12, No. 13, No. 21,
No. 22 pins are 5 bit address position, No. 23, No. 25, No. 26, No. 27, No. 29, No. 30, No. 32, No. 33 pins be 8 data bit.
The present invention has an advantageous effect in that compared with background technology：The multi-functional collection controls of CPCI are applied to by one kind
Hardware connectivity standards and communication protocol defined in the common interface module of device processed so that based on the work(designed by different demands
Can daughter board meet unified hardware and firewire standard, realize daughter board work simultaneously on mainboard of a variety of difference in functionalitys.If needed
Will other functions, need only design corresponding function daughter board according to the standard of common interface module, and the acquisition and control card
The hardware and firmware of itself need not then be changed, and reduce the cost of whole acquisition control device, improve the expansible of device
Property, more adapt to the complicated demand in Industry Control scene.
Brief description of the drawings
Fig. 1 is the common interface module theory diagram of mainboard；
Fig. 2 is the interface module theory diagram of SSI data acquisition cards；
Fig. 3 is the interface module theory diagram of DAC data processing cards；
Fig. 4 is the A slot circuit diagrams of the general-purpose interface of mainboard；
Fig. 5 is the B slot circuit diagrams of the general-purpose interface of mainboard；
Fig. 6 is the A slot circuit diagrams of the general-purpose interface of SSI data acquisition cards；
Fig. 7 is the B slot circuit diagrams of the general-purpose interface of SSI data acquisition cards；
Fig. 8 is the A slot circuit diagrams of the general-purpose interface of DAC data processing cards；
Fig. 9 is the B slot circuit diagrams of the general-purpose interface of DAC data processing cards；
Figure 10 is the sequential logic figure of the communication protocol of the present invention.
Embodiment
The present invention is further illustrated below in conjunction with the accompanying drawings.
Embodiment for convenience of explanation, mainboard of the invention using the acquisition and control card based on cpci bus standard as
Example, daughter board one and daughter board two are specifically described by taking SSI data acquisition cards and DAC data processing cards as an example respectively, wherein SSI letters
Number capture card reads synchronous serial interface signal and the processing Jing Guo SSI modules is transmitted to mainboard, DAC data processing cards reading mainboard
Its data signal is transmitted to, ancillary equipment is output to by the conversion of DAC module.
A kind of common interface module suitable for the multi-functional acquisition control devices of CPCI of the present invention, it believes in mainboard, SSI
The hardware connection mode of number capture card and DAC data processing cards respectively as shown in Figure 1, Figure 2 and Figure 3.
On mainboard, general-purpose interface one is made up of two parallel interface slots of A, B, and this two slots are 20*2 pins respectively
Male slot, the external interface of the A slots of the general-purpose interface one of mainboard and mainboard connected, and the B of the general-purpose interface one of mainboard is inserted
Fpga chip and the power module connection of groove and mainboard；The general-purpose interface two of mainboard is by two parallel interface slot groups of A, B
Into this two slots are the male slot of 20*2 pins respectively, and the A slots of the general-purpose interface two of mainboard and the external interface of mainboard connect
Connect, the B slots of the general-purpose interface two of mainboard and the fpga chip and power module of mainboard are connected.
On SSI data acquisition cards, the general-purpose interface on SSI data acquisition cards is by two parallel interface slot groups of A, B
Into this two slots are the A slots and daughter board of the general-purpose interface on the female slot of 20*2 pins, SSI data acquisition cards respectively
Functional module is connected, and the B slots of the general-purpose interface on SSI data acquisition cards and the fpga chip of daughter board are connected.At DAC data
On reason card, the general-purpose interface on DAC data processing cards is made up of two parallel interface slots of A, B, and this two slots are respectively
The A slots of general-purpose interface on the female slot of 20*2 pins, DAC data processing cards and the functional module of daughter board are connected, DAC numbers
Connected according to the B slots of the general-purpose interface on processing card and the fpga chip of daughter board.
SSI data acquisition cards and DAC data processing cards pass through the general-purpose interface one and the general-purpose interface of mainboard of mainboard respectively
Two and mainboard connection, the general-purpose interface of SSI data acquisition cards A slots connection mainboard general-purpose interface one A slots, DAC numbers
According to the B slots of the general-purpose interface two of the B slots connection mainboard of the general-purpose interface of processing card.Voltage letter needed for each module of daughter board
Number all it is to be provided by common interface module by the power module of mainboard, the general-purpose interface that the fpga chip of mainboard passes through mainboard
One and mainboard general-purpose interface two B slots can simultaneously be connected with the FPGA of two pieces of daughter boards and realize communication, and define clock believe
Number position CLK, read control bit RD, write control bit WR, address enable position ADS these four control signals, the mode bit of 3, the ground of 5
Location position and the data bit of 8, while general-purpose interface one or the general-purpose interface of mainboard that the power module of mainboard passes through mainboard
Two B slots provide 1.2V, 2.5V, 3.3V, 5V ,+12V and -12V voltage signal to daughter board.The external interface of mainboard is
90 degree of female interfaces of the pins of SCSI 68, are interconnected with ancillary equipment, the B slots of the general-purpose interface one of mainboard and the B of general-purpose interface two
The external interface that slot has 24 tunnel signalling channels and mainboard respectively is connected.
As shown in Fig. 4, Fig. 6 and Fig. 8, be respectively the acquisition and control card based on cpci bus standard, SSI data acquisition cards,
The A slots of the general-purpose interface of DAC data processing cards.The A slots of the general-purpose interface of acquisition and control card based on cpci bus standard
40 road pins in, No. 1, No. 4, No. 7, No. 10, No. 13, No. 16, No. 19, No. 20, No. 21, No. 24, No. 27, No. 30, No. 33,
No. 36, No. 39 and No. 40 pins are GND, and other 24 road pins are signal position, are connected with external interface；SSI data acquisition cards
General-purpose interface A slots 40 road pins in, No. 1, No. 4, No. 7, No. 10, No. 13, No. 16, No. 19, No. 20, No. 21,24
Number, No. 27, No. 30, No. 33, No. 36, No. 39 and No. 40 pins be GND, other 24 road pins are signal position, with external interface
Connection；In 40 road pins of the A slots of the general-purpose interface of DAC data processing cards, No. 1, No. 4, No. 7, No. 10, No. 13, No. 16,19
Number, No. 20, No. 21, No. 24, No. 27, No. 30, No. 33, No. 36, No. 39 and No. 40 pins be GND, other 24 road pins are letter
Number position, is connected with external interface.
As shown in Fig. 5, Fig. 7 and Fig. 9, be respectively the acquisition and control card based on cpci bus standard, SSI data acquisition cards,
The B slots of the general-purpose interface of DAC data processing cards.The B slots of the general-purpose interface of acquisition and control card based on cpci bus standard
40 road pins in, No. 44, No. 48, No. 51, No. 54, No. 56, No. 58, No. 60, No. 64, No. 68, No. 71, No. 74, No. 76,78
Number, No. 80 pins be GND, No. 55 pins are that 3.3V voltages, No. 57 pins are that 2.5V voltages, No. 59 pins are 1.2V voltages, 75
Number pin is that+12V voltages, No. 77 pins are that -12V voltages, No. 79 pins are 5V voltages, No. 41 pins be clock signal position CLK,
No. 42 pins are that to read control bit RD, No. 43 pins to write control bit WR, No. 45 pins be address enable position ADS, No. 46, No. 47 and
No. 49 pins are mode bit, No. 50, No. 52, No. 53, No. 61, No. 62 pins be 5 bit address position, No. 63, No. 65, No. 66,67
Number, No. 69, No. 70, No. 72, No. 73 pins be 8 data bit.
In 40 road pins of the B slots of the general-purpose interface of SSI data acquisition cards, No. 44, No. 48, No. 51, No. 54, No. 56,
No. 58, No. 60, No. 64, No. 68, No. 71, No. 74, No. 76, No. 78, No. 80 pins be GND, No. 55 pins be 3.3V voltages, No. 57
Pin be 2.5V voltages, No. 59 pins be 1.2V voltages, No. 75 pins be+12V voltages, No. 77 pins be -12V voltages, No. 79
Pin is 5V voltages, and No. 41 pins are that clock signal position CLK, No. 42 pins are to read control bit RD, No. 43 pins to write control bit
WR, No. 45 pins are address enable position ADS, and No. 46, No. 47 and No. 49 pins are mode bit, No. 50, No. 52, No. 53, No. 61,
No. 62 pins are 5 bit address position, No. 63, No. 65, No. 66, No. 67, No. 69, No. 70, No. 72, No. 73 pins be 8 data bit.
In 40 road pins of the B slots of the general-purpose interface of DAC data processing cards, No. 44, No. 48, No. 51, No. 54, No. 56,
No. 58, No. 60, No. 64, No. 68, No. 71, No. 74, No. 76, No. 78, No. 80 pins be GND, No. 55 pins be 3.3V voltages, No. 57
Pin be 2.5V voltages, No. 59 pins be 1.2V voltages, No. 75 pins be+12V voltages, No. 77 pins be -12V voltages, No. 79
Pin is 5V voltages, and No. 41 pins are that clock signal position CLK, No. 42 pins are to read control bit RD, No. 43 pins to write control bit
WR, No. 45 pins are address enable position ADS, and No. 46, No. 47 and No. 49 pins are mode bit, No. 50, No. 52, No. 53, No. 61,
No. 62 pins are 5 bit address position, No. 63, No. 65, No. 66, No. 67, No. 69, No. 70, No. 72, No. 73 pins be 8 data bit.
As shown in Figure 10, it is the sequential logic figure of communication protocol of the invention.One kind is applied to the multi-functional collection controls of CPCI
The common interface module of device processed, after hardware unit is connected with industrial computer, according to the general-purpose interface between mainboard and daughter board
The communication protocol of module is communicated：
(1) first, the function daughter board being connected on mainboard feeds back to the working condition of itself the FPGA chips of mainboard,
So that mainboard recognizes the corresponding functional attributes of the daughter board, daughter board is carried out by 3 mode bits defined on common interface module
Daughter board feedback of status, 3 mode bits can at most be defined not to be had on 8 kinds of different states, the general-purpose interface of 000 expression mainboard
There is connection daughter board, 001 to 111 expression 7 kinds of different function daughter boards, i.e. mainboard can at most recognize 7 kinds of different function daughter boards；
(2) after step (1) is completed, mainboard FPGA is by the address of the general-purpose interface one of mainboard and the general-purpose interface two of mainboard
Enable bit ADS sets low level, and host computer sends instruction to mainboard, and mainboard obtains the address of 8, and the highest order of the address is 0
The daughter board that the general-purpose interface one of gating mainboard is connected is represented, the highest order of the address is 1 general-purpose interface for representing gating mainboard
Two daughter boards connected；Address combination of the 2nd and the 3rd since highest order represents the classification of gating daughter board, have 00,
01st, 10,11 4 kind；Combination from the 4th to the 8th passes through the 5 of the general-purpose interface one of mainboard or the general-purpose interface two of mainboard
Bit address bit port is transmitted to daughter board, for selecting register defined in the FPGA of daughter board, can at most determine in the FPGA of daughter board
The register of adopted 32 different addresses, these registers are used to deposit the signal that the functional module of daughter board is gathered from ancillary equipment,
Or storage mainboard is transmitted to the data of daughter board by 8 data channel of general-purpose interface one or general-purpose interface two；
(3) after step (2) is completed, the fpga chip of mainboard is judged according to the action of host computer, if without new
Instruction, then return to (1)；If host computer passes on new instruction, the i.e. functional module to the daughter board of gating to carry out specifically
Operation, now mainboard is waited for, and the daughter board being strobed then enters step (4)；
(4) FPGA of mainboard is judged according to the instruction of host computer, if read operation, then the FPGA of mainboard passes through
The corresponding reading control bit RD of the daughter board of gating is set low level by common interface module, what the daughter board being strobed gathered functional module
Signal is stored in 32 registers defined in (2) using 8 bits as a unit, and then the FPGA of daughter board is according to main in (2)
5 bit address that plate is transmitted to daughter board search out the register of corresponding address, the signal of 8 bits stored in the register are passed through logical
Signal parallel is transmitted to the FPGA of mainboard with 8 data bit ports of interface module, host computer is uploaded to after processing；If
Write operation, then the FPGA of mainboard the corresponding control bit WR that writes of the daughter board of gating is set low by level by common interface module, then
Need the data write will by 8 data bit ports of common interface module in the form of 8 bit binary numbers host computer
It is transmitted to the FPGA of daughter board, 5 bit address that the FPGA of daughter board is transmitted to daughter board according to mainboard in (2) are searched out accordingly data parallel
The register of location, is stored data in 32 registers defined in (2), and is transmitted to the functional module of daughter board as needed,
Handled and exported；
(5) after step (4) is completed, an operation cycle terminates, and (1) is returned again and carries out next operation cycle.
Claims (5)
1. a kind of common interface module suitable for the multi-functional acquisition control devices of CPCI, the multi-functional acquisition control dresses of CPCI
Put based on cpci bus standard, be made up of the acquisition and control card as mainboard and the functional cards as daughter board, mainboard and daughter board
Connect and communicate by the common interface module, can at most connect two pieces of daughter boards on one piece of mainboard simultaneously；It is characterized in that：
The common interface module includes：Outside the fpga chip of mainboard, the general-purpose interface one of mainboard, the general-purpose interface two of mainboard, mainboard
Portion's interface, the power module of mainboard；The fpga chip of daughter board, the general-purpose interface of daughter board, the functional module of daughter board；
The general-purpose interface one of described mainboard is made up of two parallel interface slots of A, B, and this two slots are 20*2 pins respectively
Male slot, the external interface of the A slots of the general-purpose interface one of mainboard and mainboard connected, and the B of the general-purpose interface one of mainboard is inserted
Fpga chip and the power module connection of groove and mainboard；The general-purpose interface two of described mainboard is by two parallel interfaces of A, B
Slot is constituted, and this two slots are the male slot of 20*2 pins, the A slots of the general-purpose interface two of mainboard and the outside of mainboard respectively
Interface is connected, and the B slots of the general-purpose interface two of mainboard and the fpga chip and power module of mainboard are connected；
The general-purpose interface of described daughter board is made up of two parallel interface slots of A, B, and this two slots are 20*2 pins respectively
Female slot, the A slots of the general-purpose interface of daughter board and the functional module of daughter board are connected, B slots and the son of the general-purpose interface of daughter board
The fpga chip connection of plate；
Daughter board is plugged on the general-purpose interface one of mainboard or general-purpose interface two by the general-purpose interface of daughter board, and the general of daughter board connects
The A slots of the corresponding general-purpose interface of A slots connection mainboard of mouth, the B slots connection mainboard of the general-purpose interface of daughter board is corresponding logical
With the B slots of interface；Voltage signal needed for each module of daughter board is all to be carried by common interface module by the power module of mainboard
Supply, the fpga chip of mainboard by the B slots of the general-purpose interface one of mainboard or the general-purpose interface two of mainboard simultaneously with two pieces
The fpga chip of daughter board connects and realizes communication, and the communication link between the wherein FPGA of the FPGA of mainboard and each piece of daughter board has
20 circuit-switched data transmission channels, and being defined in firmware layer in face of the signal of this 20 paths, be respectively clock signal position CLK,
Read control bit RD, write control bit WR, address enable position ADS these four control signals, 3 mode bits, 5 bit address position and 8
Data bit；Simultaneously the power module of mainboard by the B slots of the general-purpose interface one of mainboard or the general-purpose interface two of mainboard to son
Plate provides 1.2V, 2.5V, 3.3V, 5V ,+12V and -12V voltage signal；The external interface of described mainboard is the pins of SCSI 68
90 degree of female interfaces, interconnected with ancillary equipment, the A slots difference of the A slots of the general-purpose interface one of mainboard and general-purpose interface two
The external interface for having 24 tunnel signalling channels and mainboard is connected；
Communicated between mainboard and daughter board according to the communication protocol of the common interface module：
(1) first, the function daughter board being connected on mainboard feeds back to the working condition of itself fpga chip of mainboard, so that
Mainboard recognizes the corresponding functional attributes of the daughter board, and daughter board carries out daughter board shape by 3 mode bits defined on common interface module
State is fed back, and 3 mode bits, which can be at most defined on 8 kinds of different states, the general-purpose interface of 000 expression mainboard, does not have connexon
Plate, 001 to 111 expression 7 kinds of different function daughter boards, i.e. mainboard can at most recognize 7 kinds of different function daughter boards；
(2) after step (1) is completed, mainboard FPGA is by the general-purpose interface one of mainboard and the address enable of the general-purpose interface two of mainboard
Position ADS sets low level, and host computer sends instruction to mainboard, and mainboard obtains the address of 8, and the highest order of the address represents for 0
The daughter board that the general-purpose interface one of gating mainboard is connected, the highest order of the address is 1 institute of general-purpose interface two for representing gating mainboard
The daughter board of connection；Address combination of the 2nd and the 3rd since highest order represents the classification of gating daughter board, have 00,01,
10th, 11 4 kinds；5 ground combined by the general-purpose interface one of mainboard or the general-purpose interface two of mainboard from the 4th to the 8th
Location bit port is transmitted to daughter board, for selecting register defined in the FPGA of daughter board, at most can define 32 in the FPGA of daughter board
The register of individual different address, these registers are used to deposit the signal that the functional module of daughter board is gathered from ancillary equipment, or
Storage mainboard is transmitted to the data of daughter board by 8 data channel of general-purpose interface one or general-purpose interface two；
(3) after step (2) is completed, the fpga chip of mainboard is judged according to the action of host computer, if without new finger
Order, then return to (1)；If host computer passes on new instruction, i.e. the functional module to the daughter board of gating is specifically operated,
Now mainboard is waited for, and the daughter board being strobed then enters step (4)；
(4) FPGA of mainboard is judged according to the instruction of host computer, if read operation, then the FPGA of mainboard is connect by general
The corresponding reading control bit RD of the daughter board of gating is set low level by mouth mold block, the signal that the daughter board being strobed gathers functional module with
8 bits are a unit, are stored in 32 registers defined in (2), then the FPGA of daughter board is transmitted to according to mainboard in (2)
5 bit address of daughter board search out the register of corresponding address, and the signal of 8 bits stored in the register is passed through into general-purpose interface
Signal parallel is transmitted to the FPGA of mainboard by 8 data bit ports of module, and host computer is uploaded to after processing；If writing behaviour
Make, then the corresponding control bit WR that writes of the daughter board of gating is set low level by the FPGA of mainboard by common interface module, then will be upper
Position machine need the data write in the form of 8 bit binary numbers by 8 data bit ports of common interface module by data
The FPGA of daughter board is concurrently transmitted to, 5 bit address that the FPGA of daughter board is transmitted to daughter board according to mainboard in (2) search out corresponding address
Register, is stored data in 32 registers defined in (2), and is transmitted to the functional module of daughter board as needed, is carried out
Processing and output；
(5) after step (4) is completed, an operation cycle terminates, and (1) is returned again and carries out next operation cycle.
2. a kind of common interface module suitable for the multi-functional acquisition control devices of CPCI according to claim 1, it is special
Levy and be：In 40 road pins of the A slots of the general-purpose interface one of described mainboard, No. 1, No. 4, No. 7, No. 10, No. 13, No. 16,
No. 19, No. 20, No. 21, No. 24, No. 27, No. 30, No. 33, No. 36, No. 39 and No. 40 pins are GND, and other 24 road pins are letter
Number position, is connected with external interface；In 40 road pins of the A slots of the general-purpose interface two of described mainboard, No. 1, No. 4, No. 7,10
Number, No. 13, No. 16, No. 19, No. 20, No. 21, No. 24, No. 27, No. 30, No. 33, No. 36, No. 39 and No. 40 pins be GND, its
His 24 road pins are signal position, are connected with external interface.
3. a kind of common interface module suitable for the multi-functional acquisition control devices of CPCI according to claim 1, it is special
Levy and be：In 40 road pins of the B slots of the general-purpose interface one of described mainboard, No. 4, No. 8, No. 11, No. 14, No. 16, No. 18,
No. 20, No. 24, No. 28, No. 31, No. 34, No. 36, No. 38, No. 40 pins be GND, No. 15 pins are 3.3V voltages, No. 17 pins
It is that 1.2V voltages, No. 35 pins are that+12V voltages, No. 37 pins are -12V voltages, No. 39 pins for 2.5V voltages, No. 19 pins
For 5V voltages, No. 1 pin is that clock signal position CLK, No. 2 pins are to read control bit RD, No. 3 pins to write control bit WR, No. 5 pipes
Pin is address enable position ADS, and No. 6, No. 7 and No. 9 pins are mode bit, No. 10, No. 12, No. 13, No. 21, No. 22 pins be 5
Address bit, No. 23, No. 25, No. 26, No. 27, No. 29, No. 30, No. 32, No. 33 pins be 8 data bit；Described mainboard it is logical
In the 40 road pins with the B slots of interface two, No. 4, No. 8, No. 11, No. 14, No. 16, No. 18, No. 20, No. 24, No. 28, No. 31,
No. 34, No. 36, No. 38, No. 40 pins be GND, No. 15 pins are that 3.3V voltages, No. 17 pins are that 2.5V voltages, No. 19 pins are
1.2V voltages, No. 35 pins are that+12V voltages, No. 37 pins are that -12V voltages, No. 39 pins are 5V voltages, and No. 1 pin is clock
Signal position CLK, No. 2 pins are that to read control bit RD, No. 3 pins to write control bit WR, No. 5 pins be address enable position ADS, No. 6,
No. 7 and No. 9 pins are mode bit, No. 10, No. 12, No. 13, No. 21, No. 22 pins be 5 bit address position, No. 23, No. 25, No. 26,
No. 27, No. 29, No. 30, No. 32, No. 33 pins be 8 data bit.
4. a kind of common interface module suitable for the multi-functional acquisition control devices of CPCI according to claim 1, it is special
Levy and be：In 40 road pins of the A slots of the general-purpose interface of described daughter board, No. 1, No. 4, No. 7, No. 10, No. 13, No. 16,19
Number, No. 20, No. 21, No. 24, No. 27, No. 30, No. 33, No. 36, No. 39 and No. 40 pins be GND, other 24 road pins are signal
Position, is connected with external interface.
5. a kind of common interface module suitable for the multi-functional acquisition control devices of CPCI according to claim 1, it is special
Levy and be：In 40 road pins of the B slots of the general-purpose interface of described daughter board, No. 4, No. 8, No. 11, No. 14, No. 16, No. 18,20
Number, No. 24, No. 28, No. 31, No. 34, No. 36, No. 38, No. 40 pins be GND, No. 15 pins are that 3.3V voltages, No. 17 pins are
2.5V voltages, No. 19 pins are that 1.2V voltages, No. 35 pins are that+12V voltages, No. 37 pins are that -12V voltages, No. 39 pins are
5V voltages, No. 1 pin is that clock signal position CLK, No. 2 pins are to read control bit RD, No. 3 pins to write control bit WR, No. 5 pins
For address enable position ADS, No. 6, No. 7 and No. 9 pins are mode bit, No. 10, No. 12, No. 13, No. 21, No. 22 pins be 5 ground
Location position, No. 23, No. 25, No. 26, No. 27, No. 29, No. 30, No. 32, No. 33 pins be 8 data bit.
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| CN111694788A (en) * | 2020-04-21 | 2020-09-22 | 恒信大友（北京）科技有限公司 | Motherboard circuit |
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