CN103123516A - Method and device of united communication between mainboard and a plurality of adapter cards - Google Patents
Method and device of united communication between mainboard and a plurality of adapter cards Download PDFInfo
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- CN103123516A CN103123516A CN2011103695051A CN201110369505A CN103123516A CN 103123516 A CN103123516 A CN 103123516A CN 2011103695051 A CN2011103695051 A CN 2011103695051A CN 201110369505 A CN201110369505 A CN 201110369505A CN 103123516 A CN103123516 A CN 103123516A
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Abstract
The invention discloses a method and a device of united communication between a mainboard and a plurality of adapter cards, and relates to the field of high-speed digital communication and the united communication of the plurality of adapter cards, signal acquisition and processing. The device of the united communication between the mainboard and the plurality of adapter cards comprises the mainboard and the plurality of adapter cards which are connected with the mainboard through a plurality of board-to-board connectors, wherein the board-to-board connectors are of the same type. The mainboard is used for receiving interface data sent by the adapter cards, processing the interface data after converting the interface data into a data format which can be recognized by the mainboard, and sending the interface data to corresponding adapter cards after converting data which is sent to the adapter cards into the interface data. The adapter cards are used for receiving interface data sent by the mainboard, processing the interface data after converting the interface data into a data format which can be recognized by the adapter cards, and sending the interface data to the mainboard after converting data which is sent to the mainboard into the interface data. The method and the device of the united communication between the mainboard and the plurality of adapter cards achieve normal communication between the mainboard and the plurality of adapter cards.
Description
Technical field
The present invention relates to high-speed digital communication and a plurality of adapter joint communication, signals collecting and process field relate generally to method and the device of a kind of mainboard and a plurality of adapter joint communications.
Background technology
Current, high-speed digital signal is processed development rapidly, and communication interface, communication level are varied simultaneously, in such cases, in a system, need different adapters to come communication interface, communication level is processed, and communicates by bus and control signal simultaneously and between mainboard.Therefore interface definition and respective outer side edges to data communicate by letter, the function of adapter realizes and adapter multiplexing most important.
Summary of the invention
Technical matters to be solved by this invention is how to realize the joint communication between mainboard and a plurality of different adapter, therefore method and the device of a kind of mainboard and a plurality of adapter joint communications are provided.
In order to address the above problem, the invention discloses the device of a kind of mainboard and a plurality of adapter joint communications, comprise a mainboard, a plurality of adapters that the plate connector for substrate by a plurality of same types is connected with described mainboard, wherein:
Described mainboard receives the interface data that each adapter sends, and process after this interface data being converted to the data layout of this mainboard identification, and the data that will be transferred to each adapter sends to corresponding adapter after being converted to described interface data;
Described adapter receives the interface data that described mainboard sends, and process after this interface data being converted to the data layout of this adapter identification, and the data that will be transferred to described mainboard sends to described mainboard after being converted to described interface data.
Preferably, in said apparatus, described mainboard comprises processing unit and interface unit, wherein:
Described processing unit is processed the data that described interface unit sends, and the data that will be transferred to each adapter send to described interface unit;
Described interface unit, receive the interface data that each adapter sends, the data layout that this interface data is converted to the identification of this mainboard sends to described processing unit, and receives the data that described processing unit sends, and sends to corresponding adapter after these data are converted to described interface data.
Preferably, in said apparatus, described adapter comprises processing unit and interface unit, wherein:
Described processing unit is processed the data that described interface unit sends, and the data that will be transferred to mainboard send to described interface unit;
Described interface unit, receive the interface data that mainboard sends, the data layout that this interface data is converted to the identification of this adapter sends to described processing unit, and receives the data that described processing unit sends, and sends to described mainboard after these data are converted to described interface data.
Preferably, in said apparatus, described mainboard sends to the interface data of described adapter, and described adapter to send to the interface data of described mainboard be the data of identical or different communication format.
The invention also discloses a kind of method of mainboard and a plurality of adapter joint communications, comprising:
The plate connector for substrate of mainboard by a plurality of same types receives the interface data that a plurality of adapters send, and processes after the interface data that receives being converted to the data layout of this mainboard identification;
When described mainboard during to each adapter the transmission of data, the data that transmit are converted to the plate connector for substrate by correspondence sends to corresponding adapter after described interface data.
Preferably, in said method, when described adapter received the interface data of described mainboard transmission, the data layout that first this interface data is converted to the identification of this adapter was processed again;
When described adapter during to described mainboard the transmission of data, after being converted to described interface data, the data that transmit send to described mainboard.
Preferably, in said method, described mainboard sends to the interface data of described adapter, and described adapter to send to the interface data of described mainboard be the data of identical or different communication format.
Preferably, said method also comprises, pin corresponding to power supply, bus interface and control interface on described plate connector for substrate and bus signals and the control signal on the plate connector for substrate are set in advance.
Preferably, in said method, described bus signals comprise at least the input of clock signal (mCLK), data output signal (DI DO) and input output control signal (CSI CSO), wherein, described input output control signal (CSI CSO) be periodic signal.
Preferably, in said method, described input the width of output control signal (CSI CSO) be directly proportional to the size of data traffic.
Technical solution of the present invention has realized the proper communication between mainboard and a plurality of different adapter.
Description of drawings
Fig. 1 is the connection diagram of mainboard and a plurality of adapters in the present embodiment;
Fig. 2 is the bus data sequential chart that defines on the plate connector for substrate in the present embodiment;
Fig. 3 is the sequential chart of reading of the control signal that defines on the plate connector for substrate in the present embodiment;
Fig. 4 is the sequential chart of writing of the control signal that defines on the plate connector for substrate in the present embodiment.
Embodiment
In order to make the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, technical solution of the present invention is described in further detail.Need to prove, in the situation that do not conflict, the application's embodiment and the feature in embodiment can make up arbitrarily mutually.
The present embodiment provides the device of a kind of mainboard and a plurality of adapter joint communications, and its structure comprises a mainboard as shown in Figure 1, a plurality of adapters that the plate connector for substrate by a plurality of same types is connected with this mainboard.Wherein, the quantity of plate connector for substrate identical with the quantity of adapter (the present embodiment comprises N plate connector for substrate and N adapter as shown in Figure 1).The below introduces the function of each several part.
Mainboard be used for to receive the interface data that each adapter sends, and process after this interface data being converted to the data layout of this mainboard identification, and the data that will be transferred to each adapter sends to corresponding adapter after being converted to described interface data;
Particularly, mainboard comprises again processing unit and interface unit.The data that processing unit, main docking port unit send are processed, and the data that will be transferred to each adapter send to interface unit.Interface unit, be used for receiving the interface data that each adapter sends, the data layout that this interface data is converted to the identification of this mainboard sends to processing unit, and the data of reception ﹠ disposal unit transmission, and sends to corresponding adapter after these data are converted to described interface data.Wherein, the interface unit in mainboard can adopt Special Interface Chip or FPGA (programmable gate array) chip to realize.And processing unit and interface unit can be separate chips, also these two unit can be integrated in a chip and realize.
Adapter receives the interface data that mainboard sends, and process after this interface data being converted to the data layout of this adapter identification, and the data that will be transferred to mainboard sends to described mainboard after being converted to interface data.
Particularly, adapter comprises processing unit and interface unit at least.Processing unit, the data that the docking port unit sends are processed, and the data that will be transferred to mainboard send to interface unit.Interface unit receives the interface data that mainboard sends, and the data layout that this interface data is converted to the identification of this adapter sends to processing unit, and the data of reception ﹠ disposal unit transmission, and sends to mainboard after these data are converted to described interface data.Wherein, the interface unit in adapter can adopt Special Interface Chip or FPGA (programmable gate array) chip to realize, adopts fpga chip in the present embodiment, and Slave serial mode is adopted in its configuration.And processing unit and interface unit can be separate chips, also these two unit can be integrated in a chip and realize.
In said apparatus, the signal definition on the plate connector for substrate needs consistent, and is multiplexing to guarantee adapter.Wherein, interface unit in mainboard, and can adopt Special Interface Chip or FPGA (programmable gate array) chip to realize with interface unit in each adapter, take the data that guarantee to transmit between mainboard and adapter as same interface data, thereby realize multiplexing on same plate connector for substrate of a plurality of adapters.
Mainboard sends to the interface data of adapter, and adapter to send to the interface data of mainboard be the data of identical or different communication format.That is to say, in order to satisfy system requirements, the signal definition that requires mainboard to issue a plurality of different adapters by the plate connector for substrate is consistent.Same, it is also consistent that a plurality of different adapters are issued the signal definition of mainboard by the plate connector for substrate separately.And mainboard is issued the signal of each adapter and the signal that each adapter is issued mainboard, its definition can be identical also can be different.
Preferably, the plate connector for substrate that is used for connection mainboard and a plurality of adapters that adopts in said apparatus is the plate connector for substrate of same type, need choose reasonable, just can not increase the size of whole device when guaranteeing the multiplexing same plate connector for substrate of a plurality of adapters.Particularly, during the option board connector for substrate, need at least to consider two aspects.
First aspect need to according to the size of mainboard and adapter height and width, be selected suitable connector.Namely first according to adapter quantity, the cabinet size is considered the function except adapter simultaneously, determines the mainboard size.Determine size according to the adapter function again.Finally, determine connector according to the width dimensions of the height of mainboard and a plurality of adapters, that is, selected plate connector for substrate is the plate connector for substrate that satisfies simultaneously mainboard and a plurality of adapter height and width requirement.Wherein, requirement for height refers to, after mainboard connected by the plate connector for substrate with each adapter, the difference in height on both sides was in the scope of appointment.Width requirement refers to, the difference of the width after the width of N plate connector for substrate after side by side is arranged side by side with N adapter is in specified scope, and wherein, the width of each plate connector for substrate is relevant with its lead pin pitch.
Second aspect is selected connector according to the signal wire quantity between mainboard and a plurality of adapter.It is the signal wire total quantity that the signal wire quantity of selected plate connector for substrate reaches a plurality of adapters at least.But in preferred version, consider the reasonable size of system, the signal wire quantity on selected plate connector for substrate than the signal wire total quantity of a plurality of adapters Duo several get final product.
In addition, due to mainboard and a plurality of different adapter use same plate connector for substrate.Therefore the plate connector for substrate of mainboard and adapter is respectively male or female seat, can not mix.Particularly, the power pin, bus interface pin and the control interface pin that are connected to an end (plate connector for substrate male as shown in Figure 1) of each plate connector for substrate of the interface unit in mainboard is connected.Interface unit in each adapter is connected respectively to power pin, bus interface pin and the control interface pin of the other end (plate connector for substrate female as shown in Figure 1) of each plate connector for substrate.
Simultaneously, mainboard also can pass through control signal, reads the setting on each adapter, to distinguish different adapters.After carefully analyzing mainboard and adapter function, the definition of each pin of interface unit also will be set, general to guarantee each adapter.But the application does not limit detailed signaling interface kind and detailed pin definitions, as long as the pin of definition comprises: power supply,, the pins such as bus interface, control interface get final product.
And the mounting means of adapter on the plate connector for substrate can freely be selected, namely can parallel or vertical placement, decide according to system.
The below illustrates the course of work of said apparatus to have particular application as example.
Suppose the demand according to mainboard and each adapter, selected two pairs of PMC connectors of same type, model is 5120521-1 and the 5120527-1 of AMP Inc..Wherein, 5120521-1 is welded on mainboard, is referred to as P4 and P3,5120527-1 is welded on adapter, be referred to as P2 and P1.P4 and P2 are a pair of, and P3 and P1 are a pair of.The more convenient adapter of this kind syndeton multiplexing.
Because P2 is corresponding with P4 and P3 with P1, thus next the specific definition of P2 and the upper signal of P1 is described by table 1 and table 2, and the signal definition on P4 and P3 repeats no more.
Table 1 is the signal definition detailed annotation table on P1:
Table 2 is the signal definition detailed annotation table on P2:
In the signal on above-mentioned table 1 and the defined plate connector for substrate of table 2, the sequential of bus signals as shown in Figure 2.In figure, the mCLK clock is 50MHz, but data traffic is controlled and data are processed because arranging of mCLK clock directly has influence on, therefore the frequency of mCLK clock can be set as required according to concrete application scenarios.In addition, separate work between the signal CSI shown in Fig. 2 and CSO, DI and DO exist with ... respectively CSI and CSO.Therefore, also can finely tune the sequential of CSI and CSO, as delaying time or in advance, processing to facilitate data.The applicant also considers in order to facilitate data traffic to control and the data processing, requires the data-bus width of signal DI and DO controlled, recommends the data-bus width of DI and DO to be set to the 1-32 position in the present embodiment.Similarly, control and the data processing in order to facilitate data traffic, require the width of CSI and CSO controlled, and preferably CSI and CSO are set to periodic signal.CSI shown in Fig. 2 and CSO are the periodic signal that width is 4 clocks.But the width of CSI and CSO is not limited to 4 clocks, and its preferred width range is 1 to 25 clock.
In the signal on above-mentioned table 1 and the defined plate connector for substrate of table 2, the read operation process of control signal as shown in Figure 3, the write operation process is as shown in Figure 4.SDI, SDO, SCLK, SCS1 can form first group of control signal, be used for mainboard the information in the PROM on adapter is read, to determine the type of adapter.SDI, SDO, SCLK, SCS2 can form second group of control signal, are used for mainboard to the operation of the FPGA internal register on adapter (being interface unit and the processing unit on adapter).In addition, as can be seen from Table 1 and Table 2, these two groups of control signals are multiplexing three pins, thus hardware cost saved.These two groups of control signals have also adopted identical sequential, can simplify software and process.
Embodiment 2
The present embodiment is introduced a kind of method of mainboard and a plurality of adapter joint communications, and the device that the method can be provided by above-described embodiment realizes, particularly, the method comprises following operation:
The plate connector for substrate of mainboard by a plurality of same types receives the interface data that a plurality of adapters send, and processes after the interface data that receives being converted to the data layout of this mainboard identification;
When mainboard during to each adapter the transmission of data, the data that transmit are converted to the plate connector for substrate by correspondence sends to corresponding adapter after interface data.
When adapter received the interface data of above-mentioned mainboard transmission, the data layout that first this interface data is converted to the identification of this adapter was processed again; When adapter during to the mainboard the transmission of data, send to mainboard after the data that will transmit being converted to interface data.
Wherein, realize the multiplexing of plate connector for substrate in order to satisfy system requirements with the utmost point, requiring the data that mainboard is issued a plurality of different adapters by the plate connector for substrate is the data of same communication format, and the data that a plurality of different adapters are issued mainboard by the plate connector for substrate separately are the data of same communication format.And mainboard is issued the data of each adapter and the data that each adapter is issued mainboard, and its communication format can be identical, also can be different.
In addition, said method also comprises, the definition of bus signals and control signal on pin corresponding to power supply, bus interface and control interface on described plate connector for substrate and definite plate connector for substrate is set in advance.Particularly, each pin and bus signals and the control signal of plate connector for substrate can be set according to above-mentioned table 1 and table 2.Wherein, bus signals comprise at least the input of clock signal (mCLK), data output signal (DI DO) and input output control signal (CSI CSO).The setting of mCLK clock can directly have influence on data traffic control and data are processed, therefore the frequency of mCLK clock can be set as required according to concrete application scenarios.Separate work between signal CSI and CSO, DI and DO exist with ... respectively CSI and CSO.Can finely tune the sequential of CSI and CSO, as delaying time or in advance, processing to facilitate data.In addition, control and the data processing in order to facilitate data traffic, require the data-bus width of signal DI and DO controlled.For example, the data-bus width of DI and DO can be set to the 1-32 position.And signal CSI the width of CSO be directly proportional to the size of data traffic, be signal CSI the width of CSO wider, the data traffic in data transmission procedure is larger, therefore, the width of signal CSI and CSO can arrange as required, and preferably CSI and CSO are set to periodic signal.Also need to prove, in the process of signalization width, it is consistent that the data-bus width of signal CSI and CSO is wanted.Recommend the width of CSI/CSO at 1-25 clock width range in the application., when width was set to 1 minimum clock, the data traffic that can transmit was minimum, and when width was set to 25 maximum clocks, the data traffic that can transmit was maximum.Particularly: it is 32bit that each clock data width is set, and when the width of CSI/CSO was 4 clocks, the data traffic of transmission was 4x32=128bit.When the width of CSI/CSO is 8 clocks, the data traffic that can transmit is 8x32=256bit.
Control signal can be divided into two groups according to function, first group of control signal SDI, and SDO, SCLK and SCS1 can be used for mainboard the information in the PROM on adapter are read, to determine the type (can distinguish different adapters) of adapter.Second group of control signal SDI, SDO, SCLK and SCS2 can be used for mainboard to the operation of the FPGA internal register on adapter (being interface unit and the processing unit on adapter).And these two groups of control signals are multiplexing three pins have reached the effect of saving hardware cost.These two groups of control signals have also adopted identical sequential, have simplified the software processing.
In the present embodiment, other details can be referring to the description in above-described embodiment 1.
The above is only preferred embodiments of the present invention, is not for limiting protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. the device of a mainboard and a plurality of adapter joint communications, is characterized in that, this device comprises a mainboard, a plurality of adapters that the plate connector for substrate by a plurality of same types is connected with described mainboard, wherein:
Described mainboard receives the interface data that each adapter sends, and process after this interface data being converted to the data layout of this mainboard identification, and the data that will be transferred to each adapter sends to corresponding adapter after being converted to described interface data;
Described adapter receives the interface data that described mainboard sends, and process after this interface data being converted to the data layout of this adapter identification, and the data that will be transferred to described mainboard sends to described mainboard after being converted to described interface data.
2. device as claimed in claim 1, is characterized in that, described mainboard comprises processing unit and interface unit, wherein:
Described processing unit is processed the data that described interface unit sends, and the data that will be transferred to each adapter send to described interface unit;
Described interface unit, receive the interface data that each adapter sends, the data layout that this interface data is converted to the identification of this mainboard sends to described processing unit, and receives the data that described processing unit sends, and sends to corresponding adapter after these data are converted to described interface data.
3. device as claimed in claim 2, is characterized in that, described adapter comprises processing unit and interface unit, wherein:
Described processing unit is processed the data that described interface unit sends, and the data that will be transferred to mainboard send to described interface unit;
Described interface unit, receive the interface data that mainboard sends, the data layout that this interface data is converted to the identification of this adapter sends to described processing unit, and receives the data that described processing unit sends, and sends to described mainboard after these data are converted to described interface data.
4. device as claimed in claim 3, is characterized in that,
Described mainboard sends to the interface data of described adapter, and described adapter to send to the interface data of described mainboard be the data of identical or different communication format.
5. the method for a mainboard and a plurality of adapter joint communications, is characterized in that, the method comprises:
The plate connector for substrate of mainboard by a plurality of same types receives the interface data that a plurality of adapters send, and processes after the interface data that receives being converted to the data layout of this mainboard identification;
When described mainboard during to each adapter the transmission of data, the data that transmit are converted to the plate connector for substrate by correspondence sends to corresponding adapter after described interface data.
6. method as claimed in claim 5, is characterized in that,
When described adapter received the interface data of described mainboard transmission, the data layout that first this interface data is converted to the identification of this adapter was processed again;
When described adapter during to described mainboard the transmission of data, after being converted to described interface data, the data that transmit send to described mainboard.
7. method as claimed in claim 6, is characterized in that,
Described mainboard sends to the interface data of described adapter, and described adapter to send to the interface data of described mainboard be the data of identical or different communication format.
8. as claim 5,6 or 7 described methods, it is characterized in that, the method also comprises:
Pin corresponding to power supply, bus interface and control interface on described plate connector for substrate and bus signals and the control signal on the plate connector for substrate are set in advance.
9. method as claimed in claim 8, is characterized in that,
Described bus signals comprise at least the input of clock signal (mCLK), data output signal (DI DO) and input output control signal (CSI CSO), wherein, described input output control signal (CSI CSO) be periodic signal.
10. method as claimed in claim 9, is characterized in that,
Described input the width of output control signal (CSI CSO) be directly proportional to the size of data traffic.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104965468A (en) * | 2015-07-06 | 2015-10-07 | 浙江大学 | Universal interface module for CPCI multi-functional acquisition control device |
| CN106463098A (en) * | 2016-07-26 | 2017-02-22 | 北京小米移动软件有限公司 | Display device and motherboards applied to the display device |
| WO2020041102A1 (en) * | 2018-08-21 | 2020-02-27 | General Electric Company | Networking systems using multiple peripheral component cards |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1841355A (en) * | 2005-06-03 | 2006-10-04 | 微星科技股份有限公司 | Dual-bus adapter card |
| CN101089836A (en) * | 2006-06-15 | 2007-12-19 | 辉达公司 | Motherboard for cost-effective high performance graphics system with two or more graphics processing units |
| CN101101583A (en) * | 2006-07-05 | 2008-01-09 | 友劲科技股份有限公司 | PCI-Express multi-mode extended card and communication device possessing the extended card |
| CN101221458A (en) * | 2004-04-09 | 2008-07-16 | 辉达公司 | Edge connector for field changeable graphics system |
| CN102081437A (en) * | 2009-11-26 | 2011-06-01 | 鸿富锦精密工业（深圳）有限公司 | Computer |
-
2011
- 2011-11-18 CN CN201110369505.1A patent/CN103123516B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101221458A (en) * | 2004-04-09 | 2008-07-16 | 辉达公司 | Edge connector for field changeable graphics system |
| CN1841355A (en) * | 2005-06-03 | 2006-10-04 | 微星科技股份有限公司 | Dual-bus adapter card |
| CN101089836A (en) * | 2006-06-15 | 2007-12-19 | 辉达公司 | Motherboard for cost-effective high performance graphics system with two or more graphics processing units |
| CN101101583A (en) * | 2006-07-05 | 2008-01-09 | 友劲科技股份有限公司 | PCI-Express multi-mode extended card and communication device possessing the extended card |
| CN102081437A (en) * | 2009-11-26 | 2011-06-01 | 鸿富锦精密工业（深圳）有限公司 | Computer |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104965468A (en) * | 2015-07-06 | 2015-10-07 | 浙江大学 | Universal interface module for CPCI multi-functional acquisition control device |
| CN104965468B (en) * | 2015-07-06 | 2017-10-31 | 浙江大学 | A kind of common interface module suitable for the multi-functional acquisition control devices of CPCI |
| CN106463098A (en) * | 2016-07-26 | 2017-02-22 | 北京小米移动软件有限公司 | Display device and motherboards applied to the display device |
| WO2018018410A1 (en) * | 2016-07-26 | 2018-02-01 | 北京小米移动软件有限公司 | Display device and motherboard applied thereto |
| US10084985B2 (en) | 2016-07-26 | 2018-09-25 | Beijing Xiaomi Mobile Software Co., Ltd. | Display device and mainboard applied in the display device |
| CN106463098B (en) * | 2016-07-26 | 2018-11-23 | 北京小米移动软件有限公司 | Show equipment and applied to the mainboard in display equipment |
| WO2020041102A1 (en) * | 2018-08-21 | 2020-02-27 | General Electric Company | Networking systems using multiple peripheral component cards |
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| CN103123516B (en) | 2016-12-21 |
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