CN116381470A - Trigger signal synchronization method and system in ATE equipment - Google Patents
Trigger signal synchronization method and system in ATE equipment Download PDFInfo
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- CN116381470A CN116381470A CN202310271337.5A CN202310271337A CN116381470A CN 116381470 A CN116381470 A CN 116381470A CN 202310271337 A CN202310271337 A CN 202310271337A CN 116381470 A CN116381470 A CN 116381470A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318516—Test of programmable logic devices [PLDs]
- G01R31/318519—Test of field programmable gate arrays [FPGA]
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
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Abstract
The scheme relates to a trigger signal synchronization method and system in ATE equipment. The method comprises the following steps: generating trigger signals through FPGA chips on a synchronous board card in the ATE equipment, and transmitting the trigger signals to each resource board card through a backboard wiring in the ATE equipment; capturing each delay parameter of an effective trigger signal through a trigger and a carry chain in the FPGA on each resource board card and feeding back the delay parameter to the synchronous board card; the synchronous board card selects one of the delay parameters as a reference parameter, and adjusts and outputs the phase of the trigger signal by utilizing ODLEAY resources in the FPGA according to the delay parameters to complete the synchronization of the trigger signal. The system link delay detection is completed through the trigger signals of all channels, the phase relation of the trigger signals is adjusted through the delay parameters fed back by all channels, and finally, the real-time synchronization from the synchronous board card to the trigger signals of all resource boards can be realized, the synchronous board card is completed in the FPGA, the occupied resources are less, the portability is strong, the wiring problem of the printed board is effectively solved, and the cost is saved.
Description
Technical Field
The present invention relates to the field of semiconductor testing technologies, and in particular, to a method and a system for synchronizing trigger signals in ATE equipment.
Background
With the continuous development of semiconductor technology, semiconductor test machines, that is, ATE equipment, play a very important role in the field of semiconductor testing. ATE equipment is high-end semiconductor equipment integrating various high-precision and high-performance test measurement functions, is the most important equipment in the semiconductor test process, and determines the cost and efficiency of semiconductor test. The ability of ATE devices to accurately synchronize the multi-channel parallel testing of semiconductor chips under test directly determines the testing performance of the ATE devices.
However, when testing conventional ATE equipment, if the service board is to be triggered synchronously, clock chip hardware is often added to perform synchronization, which has the problems of more occupied resources and higher cost.
Disclosure of Invention
Based on the above, in order to solve the above technical problems, a method and a system for synchronizing trigger signals in ATE equipment are provided, which can reduce the occupation of resources and save the cost.
A method of trigger signal synchronization in ATE equipment, the method comprising:
generating trigger signals through FPGA chips on a synchronous board card in ATE equipment, wherein the trigger signals are transmitted to each resource board card through backboard wiring in the ATE equipment;
capturing each delay parameter of the effective trigger signal through a trigger and a carry chain in the FPGA on each resource board card and feeding back the delay parameter to the synchronous board card;
and the synchronous board card adjusts and outputs the phase of the trigger signal by utilizing ODLEAY resources in the FPGA according to each delay parameter so as to finish the synchronization of the trigger signal.
In one embodiment, the generating, by the FPGA chip on the synchronization board inside the ATE device, a trigger signal includes:
a synchronous board card in the ATE equipment receives a trigger signal generation instruction sent by an upper computer;
and generating an instruction by the FPGA chip on the synchronous board card in the ATE equipment according to the trigger signal, and generating the trigger signal.
In one embodiment, the adjusting, by the synchronization board card, the phase of the output trigger signal according to each delay parameter by using an ODLEAY resource in the FPGA includes:
the synchronous board card selects one of the delay parameters as a reference parameter;
and the synchronous board card performs successive approximation adjustment on the delay units of the resource board cards by utilizing ODLEAY resources in the FPGA according to the reference parameters and the delay parameters until the trigger signal calibration of the resource board cards is completed.
In one embodiment, capturing, by using a trigger and a carry chain in the FPGA on each resource board, each delay parameter of the trigger signal and feeding back the delay parameter to the synchronous board, where the capturing includes:
counting by means of end-to-end connection of carry chains through the carry chains in the FPGA on each resource board card, and obtaining counted time;
and each resource board card takes the counted time as statistical time, determines each delay parameter according to the statistical time and feeds back the delay parameter to the synchronous board card.
In one embodiment, the synchronization board card establishes an independent communication physical link and a trigger signal physical link with each resource board card respectively.
In one embodiment, the communication physical link is used for respectively performing data exchange between the synchronous board card and each resource board card; the trigger signal physical link is used to generate a synchronous trigger signal.
The utility model provides a trigger signal synchronization system in ATE equipment, the system includes inside synchronous integrated circuit board, each resource integrated circuit board of ATE equipment, synchronous integrated circuit board, each the equal communication connection of resource integrated circuit board, wherein:
the synchronous board card is used for generating trigger signals through the FPGA chip, and the trigger signals are transmitted to each resource board card through backboard wiring inside the ATE equipment;
each resource board card is used for capturing each delay parameter of the effective trigger signal through a trigger and a carry chain in the FPGA and feeding back the delay parameter to the synchronous board card;
the synchronous board card is also used for adjusting and outputting the phase of the trigger signal by utilizing ODLEAY resources in the FPGA according to each delay parameter so as to complete the synchronization of the trigger signal.
According to the trigger signal synchronization method and system in the ATE equipment, the trigger signals are generated through the FPGA chip on the synchronization board card in the ATE equipment, and the trigger signals are transmitted to each data board card through the backboard wiring in the ATE equipment; capturing each delay parameter of the effective trigger signal through a trigger and a carry chain in the FPGA on each resource board card and feeding back the delay parameter to the synchronous board card; and the synchronous board card adjusts and outputs the phase of the trigger signal by utilizing ODLEAY resources in the FPGA according to each delay parameter so as to finish the synchronization of the trigger signal. The system link delay detection is completed through the trigger signals of all channels, the phase relation of the trigger signals is adjusted through the delay parameters fed back by all channels, and finally, the real-time synchronization from the synchronous board card to the trigger signals of all resource boards can be realized, the synchronous board card is completed in the FPGA, the occupied resources are less, the portability is strong, the wiring problem of the printed board is effectively solved, and the cost is saved.
Drawings
FIG. 1 is a diagram of an application environment for a trigger signal synchronization method in an ATE device in one embodiment;
FIG. 2 is a block diagram of trigger signal synchronization hardware and system connections in an ATE device in accordance with one embodiment;
FIG. 3 is a flow chart of a method of trigger signal synchronization in an ATE device according to one embodiment;
FIG. 4 is a functional block diagram of closed loop adjustment of the phase of a synchronous board trigger signal in one embodiment;
FIG. 5 is a functional block diagram of closed loop adjustment of the phase of a synchronous board trigger signal in one embodiment;
FIG. 6 is a functional block diagram of a TDC measurement module in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
The trigger signal synchronization method in the ATE equipment provided by the embodiment of the application can be applied to an application environment shown in fig. 1. As shown in FIG. 1, the application environment includes an ATE device 100. As shown in fig. 2, the ATE device may be provided with a synchronization board 210 and a plurality of resource boards 220, and the synchronization board 210 may be communicatively connected to the plurality of resource boards 220. Generating trigger signals through FPGA chips on the synchronous board card 210 in the ATE equipment, and transmitting the trigger signals to each resource board card 220 through backboard wiring in the ATE equipment; capturing each delay parameter of the effective trigger signal through the trigger and carry chain in the FPGA on each resource board 220 and feeding back to the synchronous board 210; the synchronization board 210 adjusts the phase of the output trigger signal according to each delay parameter by using the ODLEAY resource in the FPGA, and completes the synchronization of the trigger signal.
In one embodiment, as shown in fig. 3, a method for synchronizing trigger signals in an ATE device is provided, including the following steps:
As shown in fig. 2, 1 synchronization board 210 and at most 15 expandable resource boards 220 may be disposed in the ATE device, and the synchronization board 210 and each resource board 220 may be connected by a backplane wire, so that data communication may be performed between the synchronization board 210 and each resource board 220. The method is characterized in that each board card adopts XC7K325TFFG676 product model of Xilinx company 7 series Kintex series as a core to realize the ATE equipment trigger signal synchronization function.
The FPGA chip on the synchronization board 210 may generate the trigger signal and transmit it to the respective resource board 220 via a communication link.
Step 304, capturing each delay parameter of the effective trigger signal through the trigger and the carry chain in the FPGA on each resource board and feeding back to the synchronous board.
In the embodiment, trigger signals are generated through an FPGA chip on a synchronous board card in the ATE equipment, and the trigger signals are transmitted to each resource board card through a backboard wiring in the ATE equipment; capturing each delay parameter of an effective trigger signal through a trigger and a carry chain in the FPGA on each resource board card and feeding back the delay parameter to the synchronous board card; and the synchronous board card adjusts and outputs the phase of the trigger signal by utilizing ODLEAY resources in the FPGA according to each delay parameter, and the synchronization of the trigger signal is completed. The system link delay detection is completed through the trigger signals of all channels, the phase relation of the trigger signals is adjusted through the delay parameters fed back by all channels, and finally, the real-time synchronization from the synchronous board card to the trigger signals of all resource boards can be realized, the synchronous board card is completed in the FPGA, the occupied resources are less, the portability is strong, the wiring problem of the printed board is effectively solved, and the cost is saved.
In one embodiment, the method for synchronizing trigger signals in ATE equipment may further include a process for generating trigger signals, where the specific process includes: a synchronous board card in ATE equipment receives a trigger signal generation instruction sent by an upper computer; and generating an instruction by an FPGA chip on a synchronous board card in the ATE equipment according to the trigger signal, and generating the trigger signal.
In one embodiment, the method for synchronizing trigger signals in ATE equipment may further include a process for adjusting the phase of the output trigger signal, where the specific process includes: the synchronous board card selects one of the delay parameters as a reference parameter; and the synchronous board card performs successive approximation adjustment on the delay units of each resource board card by utilizing ODLEAY resources in the FPGA according to the reference parameters and each delay parameter until the calibration of the trigger signals of each resource board card is completed.
Specifically, the synchronous board card can select 1 path of the synchronous board card as a reference according to each delay parameter fed back by the resource board card in the trigger signal synchronous calibration stage, and the synchronous board card respectively adjusts delay units of other resource board cards according to the reference parameters, specifically successive approximation adjustment, until the calibration of the trigger signals of the resource board cards is completed.
In one embodiment, the method for synchronizing trigger signals in ATE equipment may further include a process of feeding back delay parameters, where the specific process includes: counting by means of carry chains in the FPGA on each resource board in an end-to-end mode, and obtaining counting time; and each resource board takes the counted time as the statistical time, and determines each delay parameter according to the statistical time and feeds back the delay parameter to the synchronous board card.
The capturing of the trigger signal is to adopt carry chain resources in the FPGA, realize counting by means of end-to-end connection of carry chains, and finally count time is counting time. Each resource board can determine each delay parameter according to the statistical time and feed back to the synchronous board.
In one embodiment, the synchronization board card establishes an independent communication physical link and a trigger signal physical link with each of the resource boards. The synchronous board card respectively establishes independent communication physical links and trigger signal physical links with the resource boards. Specifically, the FPGA on the synchronous board card can respectively generate 15 paths of communication links and 15 paths of trigger signal links, so as to perform data interaction communication with 15 resource boards.
In one embodiment, the communication physical link is used for exchanging data with each resource board by the synchronous board card respectively; the trigger signal physical link is used to generate a synchronous trigger signal.
It should be understood that, although the steps in the above-described flowcharts are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described above may include a plurality of sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, and the order of execution of the sub-steps or stages is not necessarily sequential, but may be performed alternately or alternately with at least a part of the sub-steps or stages of other steps or other steps.
In one embodiment, as shown in fig. 2, a trigger signal synchronization system in an ATE device is provided, where the system includes a synchronization board 210 and each resource board 220 inside the ATE device, and the synchronization board 210 and each resource board 220 are communicatively connected, where:
the synchronous board card 210 is configured to generate a trigger signal through the FPGA chip, where the trigger signal is transmitted to each of the resource boards 220 through a backplane wiring inside the ATE equipment;
each resource board 220 is configured to capture each delay parameter of the effective trigger signal through a trigger and a carry chain in the FPGA, and feed back the delay parameter to the synchronization board 210;
the synchronization board 210 is further configured to adjust a phase of the output trigger signal according to each delay parameter by using an ODLEAY resource in the FPGA, so as to complete synchronization of the trigger signal.
In one embodiment, the synchronization board 210 is further configured to receive a trigger signal generation instruction sent by the host computer; and the FPGA chip generates an instruction according to the trigger signal to generate the trigger signal.
In one embodiment, the synchronization board 210 is further configured to select one from the delay parameters as a reference parameter; and according to the reference parameters and each delay parameter, performing successive approximation adjustment on the delay units of each resource board 220 by utilizing ODLEAY resources in the FPGA until the calibration of the trigger signals of each resource board 220 is completed.
A functional block diagram of the synchronous board 210 trigger signal phase closed loop adjustment is shown in fig. 4. The phase closed-loop adjustment function of the trigger signal of the synchronization board 210 mainly comprises a trigger signal generating module 410, a closed-loop adjustment module 420 and a delay unit 430. The trigger signal generating module 410 is mainly responsible for receiving the function instruction of the upper computer to generate a trigger signal; the closed-loop adjusting module 420 is responsible for selecting 1 path of the delay parameters fed back by the resource board card as a reference in the synchronous calibration stage of the trigger signals of the ATE equipment, and the synchronous board card respectively adjusts the delay units of other resource board cards according to the reference delay parameters, so as to perform successive approximation adjustment until the calibration of the trigger signals of the resource board cards is completed; the delay unit 430 is used as a self-contained hardware resource in the FPGA, and can effectively adjust output delay for output signals, and the delay precision is 78ps.
In one embodiment, each resource board 220 is further configured to count by using a carry chain in the FPGA and end to end, and obtain the counted time; the counted time is taken as the statistical time, and each delay parameter is determined according to the statistical time and fed back to the synchronous board 210.
The capturing function of the trigger signal can be implemented in the data board 220, wherein the functional block diagram of the trigger signal capturing system is shown in fig. 5, and mainly includes a TDC measurement module 510 and a delay parameter generation module 520, and the process of the TDC measurement module 510 when acquiring the trigger signal is shown in fig. 6. The TDC measurement module 510 mainly adopts carry chain resources in the FPGA, and uses carry chains to implement counting end to end, and finally the counting time is the counting time; the delay parameter generating module 520 is mainly responsible for transmitting the delay parameter generated by the TDC measuring module to the synchronous board card through the communication link to realize the trigger signal delay statistics feedback.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. A method of trigger signal synchronization in ATE equipment, the method comprising:
generating trigger signals through FPGA chips on a synchronous board card in ATE equipment, wherein the trigger signals are transmitted to each resource board card through backboard wiring in the ATE equipment;
capturing each delay parameter of the effective trigger signal through a trigger and a carry chain in the FPGA on each resource board card and feeding back the delay parameter to the synchronous board card;
and the synchronous board card adjusts and outputs the phase of the trigger signal by utilizing ODLEAY resources in the FPGA according to each delay parameter so as to finish the synchronization of the trigger signal.
2. The method for synchronizing trigger signals in ATE equipment according to claim 1, wherein the generating trigger signals by FPGA chips on a synchronization board inside the ATE equipment comprises:
a synchronous board card in the ATE equipment receives a trigger signal generation instruction sent by an upper computer;
and generating an instruction by the FPGA chip on the synchronous board card in the ATE equipment according to the trigger signal, and generating the trigger signal.
3. The method for synchronizing trigger signals in ATE equipment according to claim 1, wherein the synchronizing board adjusts the phase of the output trigger signals by using ODLEAY resources inside the FPGA according to each delay parameter, comprising:
the synchronous board card selects one of the delay parameters as a reference parameter;
and the synchronous board card performs successive approximation adjustment on the delay units of the resource board cards by utilizing ODLEAY resources in the FPGA according to the reference parameters and the delay parameters until the trigger signal calibration of the resource board cards is completed.
4. The method for synchronizing trigger signals in ATE equipment according to claim 1, wherein capturing each delay parameter of the trigger signal and feeding back the delay parameter to the synchronization board through a trigger and a carry chain in the FPGA on each resource board comprises:
counting by means of end-to-end connection of carry chains through the carry chains in the FPGA on each resource board card, and obtaining counted time;
and each resource board card takes the counted time as statistical time, determines each delay parameter according to the statistical time and feeds back the delay parameter to the synchronous board card.
5. The method for synchronizing trigger signals in ATE equipment according to claim 1, wherein the synchronization board card establishes independent communication physical links and trigger signal physical links with the resource boards, respectively.
6. The method for synchronizing trigger signals in ATE equipment according to claim 5, wherein the communication physical link is used for exchanging data with each resource board by the synchronization board; the trigger signal physical link is used to generate a synchronous trigger signal.
7. The utility model provides a trigger signal synchronization system in ATE equipment, its characterized in that, the system includes inside synchronous integrated circuit board, each resource integrated circuit board of ATE equipment, synchronous integrated circuit board, each the equal communication connection of resource integrated circuit board, wherein:
the synchronous board card is used for generating trigger signals through the FPGA chip, and the trigger signals are transmitted to each resource board card through backboard wiring inside the ATE equipment;
each resource board card is used for capturing each delay parameter of the effective trigger signal through a trigger and a carry chain in the FPGA and feeding back the delay parameter to the synchronous board card;
the synchronous board card is also used for adjusting and outputting the phase of the trigger signal by utilizing ODLEAY resources in the FPGA according to each delay parameter so as to complete the synchronization of the trigger signal.
8. The system for synchronizing trigger signals in ATE equipment of claim 7, wherein the synchronization board card is further configured to receive a trigger signal generation instruction sent by an upper computer; and the FPGA chip generates an instruction according to the trigger signal to generate the trigger signal.
9. The ATE device trigger signal synchronization system of claim 7, wherein the synchronization board card is further configured to select one of the delay parameters as a reference parameter; and according to the reference parameters and the delay parameters, performing successive approximation adjustment on the delay units of the resource boards by utilizing ODLEAY resources in the FPGA until the calibration of the trigger signals of the resource boards is completed.
10. The trigger signal synchronization system in ATE equipment of claim 7, wherein each resource board card is further configured to count by means of a carry chain inside the FPGA, end-to-end by means of the carry chain, and obtain a counted time; and taking the counted time as a statistical time, determining each delay parameter according to the statistical time and feeding back to the synchronous board card.
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| CN202310271337.5A CN116381470A (en) | 2023-03-20 | 2023-03-20 | Trigger signal synchronization method and system in ATE equipment |
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| CN202310271337.5A CN116381470A (en) | 2023-03-20 | 2023-03-20 | Trigger signal synchronization method and system in ATE equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117970219A (en) * | 2024-03-12 | 2024-05-03 | 悦芯科技股份有限公司 | Synchronous calibration system between ATE test machine platen |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117970219A (en) * | 2024-03-12 | 2024-05-03 | 悦芯科技股份有限公司 | Synchronous calibration system between ATE test machine platen |
| CN117970219B (en) * | 2024-03-12 | 2024-07-05 | 悦芯科技股份有限公司 | Synchronous calibration system between ATE test machine platen |
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