CN210721099U - STM 32-based gating control system - Google Patents
STM 32-based gating control system Download PDFInfo
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- CN210721099U CN210721099U CN201921963234.0U CN201921963234U CN210721099U CN 210721099 U CN210721099 U CN 210721099U CN 201921963234 U CN201921963234 U CN 201921963234U CN 210721099 U CN210721099 U CN 210721099U
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Abstract
The utility model discloses a gating control system based on STM32, which comprises a processor; the processor is connected with the DC-DC conversion module through an interface circuit; the processor is connected with the input stage array of the relay; the relay input stage array is connected with the input stage instrument interface and the relay; the relay is connected with the relay output stage array; the input stage instrument interface is connected with the input stage array of the relay, and the output stage instrument interface is connected with the output stage relay array. The utility model discloses avoided the work of frequent change test instrument or test wiring, be convenient for establish automatic test system.
Description
Technical Field
The utility model relates to an automatic test technical field specifically is a gating control system based on STM 32.
Background
With the continuous development of the automation of the test technology, the test instruments provide automatic control interfaces, and in daily tests, the requirement that multiple instruments are needed for multiple parameter tests or a single instrument is used for completing multi-channel tests is often met.
Disclosure of Invention
The utility model aims to solve the technical problem that, it is not enough to prior art, provide a gating control system based on STM32, avoid frequently changing the work of test instrument or test wiring.
In order to solve the technical problem, the utility model discloses the technical scheme who adopts is: an STM 32-based gating control system, comprising a processor; the processor is connected with the DC-DC conversion module through an interface circuit; the processor is connected with the input stage array of the relay; the relay input stage array is connected with the input stage instrument interface and the relay; the relay is connected with the relay output stage array; the input stage instrument interface is connected with the input stage array of the relay, and the output stage instrument interface is connected with the output stage relay array.
The interface circuit is connected with the connector; the connector is connected with the upper computer.
The types of the relay input stage array, the relay output stage array and the relay are BMZ08R 1-E.
The input stage instrument interface and the output stage instrument interface both adopt Y11P-1832 circular connectors.
The input stage instrument interface is connected with a test instrument; the output stage instrument interface is connected with the object to be tested. Compared with the prior art, the utility model discloses the beneficial effect who has does: the utility model discloses utilize PC host computer (ADVANTECH 610L) to send control command through the RS232 serial ports, the gating control end is received the control command back of host computer through the serial ports by STM32, according to the control command of host computer, and the channel switching is accomplished to the control relay array, is connected input stage interface instrument and output stage interface measurand is connected, has avoided the work of frequent change test instrument or test wiring, is convenient for establish automatic test system.
Drawings
Fig. 1 is a diagram of a gating control system structure of STM32 according to an embodiment of the present invention;
fig. 2 is a schematic block diagram of a gating control system circuit of STM32 according to an embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a STM32 minimal system according to an embodiment of the present invention;
fig. 4 is a schematic block diagram of an embodiment of the relay array interconnection circuit of the present invention.
Detailed Description
As shown in fig. 1, an STM 32-based gating control system;
the system mainly comprises a PC upper computer (ADVANTECH 610L) control end, a gating control terminal and an instrument terminal interface;
an operation interface of a control end of a PC upper computer (ADVANTECH L) controls the gating logic of the relay (note: the control logic refers to research on intelligent relays based on STM32 and RS485 bus technologies, and an author: Liu Tong, an author unit: Hunan railway professional technology institute, journal, electronic world, No. 20 in 2014, and page 118), for example, the input-stage relays 1 and 2 and the output stages 3 and 4 are required to be gated, the relay required to be gated is selected on the operation interface, the PC upper computer (ADVANTECH L) sends a control instruction to a gating control terminal through an RS232 serial port, and the gating control terminal completes communication action according to the control instruction.
The whole control circuit of the gating control terminal mainly takes an STM32 single-chip microcomputer as a control core and comprises an RS232 interface circuit, an STM32 minimum system, a DC power supply conversion module, an input stage relay array, a relay and an output stage relay array.
Preferably, the STM32 microprocessor employs an STM32F103ZET6, configured with an external clock and reset circuit.
Preferably, the DC power conversion module adopts an LM2576S power management chip, and is equipped with a filter circuit, so that the power supply ripple is smaller.
Preferably, the input stage array of the relay, the output stage array of the relay and the relay all adopt BMZ08R1-E and are provided with an optical coupling isolation circuit, so that signal interference is avoided.
The utility model discloses a schematic diagram is connected to the relay array is seen in figure 4, and PB and the pin that the PC corresponds in connecing the PB and in figure 3 such as the type of PB1 in the IO of relay are used for driving 3 feet of each relay and switch between 2, 4 feet. For example, PB0 is connected with Io1, when PB0=0, K1-3 is communicated with K1-2, when PB0=1, K1-3 is communicated with K1-4, and the relays such as K1 are single-pole double-set relays, and the actions of the relays are controlled by the IO level of an STM32 microprocessor. Three sets of relays A1, A2 and A3, each set comprises 8 relays K1, and the total number of the relays is 24 (the utility model discloses there are 2 unused relays). In FIG. 4, K1-2 represents the 2 nd pin of the first relay, and so on; a2 is marked with X12-representing input stage, X21-representing output stage, and leads representing pins associated with A1 or A3.
PB 0-PB 15 and PC 0-PC 5 of the relay are connected with corresponding ports of an STM32 microprocessor, X12-1-X12-10 is connected with an input stage instrument interface, and X21-1-X21-10 is connected with an output stage instrument interface.
Claims (5)
1. An STM 32-based gating control system, comprising a processor; the processor is connected with the DC-DC conversion module through an interface circuit; the processor is connected with the input stage array of the relay; the relay input stage array is connected with the input stage instrument interface and the relay; the relay is connected with the relay output stage array; the input stage instrument interface is connected with the input stage array of the relay, and the output stage instrument interface is connected with the output stage relay array.
2. The STM 32-based strobe control system of claim 1, wherein the interface circuit is connected to a connector; the connector is connected with the upper computer.
3. The STM 32-based gating control system of claim 1, wherein the input relay stage array, the output relay stage array and the relay relays are all BMZ08R1-E in model.
4. The STM 32-based gating control system of claim 1, wherein the input stage instrument interface and the output stage instrument interface both use Y11P-1832 circular connectors.
5. The STM 32-based gating control system of claim 1, wherein the input stage instrumentation interface is to a test instrument; the output stage instrument interface is connected with the object to be tested.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921963234.0U CN210721099U (en) | 2019-11-13 | 2019-11-13 | STM 32-based gating control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921963234.0U CN210721099U (en) | 2019-11-13 | 2019-11-13 | STM 32-based gating control system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210721099U true CN210721099U (en) | 2020-06-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921963234.0U Active CN210721099U (en) | 2019-11-13 | 2019-11-13 | STM 32-based gating control system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210721099U (en) |
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2019
- 2019-11-13 CN CN201921963234.0U patent/CN210721099U/en active Active
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