CN204087575U - FPGA test and verification platform - Google Patents
FPGA test and verification platform Download PDFInfo
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- CN204087575U CN204087575U CN201420581377.6U CN201420581377U CN204087575U CN 204087575 U CN204087575 U CN 204087575U CN 201420581377 U CN201420581377 U CN 201420581377U CN 204087575 U CN204087575 U CN 204087575U
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Abstract
The utility model relates to a kind of FPGA test and verification platform, it comprises programmable logic chip and experiment module, described programmable logic chip is provided with jtag interface, programmable logic chip is connected with feed circuit and clock signal occurs and selection circuit, the model of described programmable logic chip is EPM7128SLC84-15N, and the IO port of chip EPM7128SLC84-15N is connected by arranging pin selectivity with between experiment module.This programme solves existing brassboard experiment module and fixes, chip plug trouble, flimsy problem.
Description
Technical field
The utility model relates to electronic technology, specifically a kind of FPGA test and verification platform.
Background technology
Programmable logic design (i.e. Programmable Logic Device) is as a kind of universal integrated circuit, and its logic function is determined device programming according to user.In recent years, along with developing rapidly of programmable logic technology, programmable logic technology has become an important developing instrument in electronic technology, automatic technology, detection technique, computer technology and the communication technology.Meanwhile, market is more and more urgent to the demand of programmable logic device (PLD) developer, has higher requirement to the teaching of programmable logic device (PLD) and practice.In order to better meet the use of colleges and universities and R&D institution, programmable logic device (PLD) experimental teaching circuit board arises at the historic moment.
But this kind of circuit board is each circuit module and element are fixed on circuit boards substantially, and experiment circuit module is fixed, a corresponding a kind of education experiment of brassboard; The file destination that program compilation generates directly is burnt in programmable logic device (PLD) and goes, and then programmable logic device (PLD) is installed on brassboard, test complete plug again on another brassboard of testing.Although this mode cost is lower, the plug repeatedly of the devices such as chip comparatively bothers, and easily damages pin.
Utility model content
The purpose of this utility model is to provide a kind of FPGA test and verification platform, and it can solve existing brassboard experiment module and fix, chip plug trouble, flimsy problem.
The technical solution of the utility model is as follows: a kind of FPGA test and verification platform, comprise programmable logic chip and experiment module, described programmable logic chip is provided with jtag interface, programmable logic chip is connected with feed circuit and clock signal occurs and selection circuit, the model of described programmable logic chip is EPM7128SLC84-15N, and the IO port of chip EPM7128SLC84-15N is connected by arranging pin selectivity with between experiment module.
Further, described experiment module comprises Independent keys circuit, one digit number code pipe display circuit, light emitting diode display circuit, 8 × 8 lattice display circuit and charactron group display circuit; Described one digit number code pipe display circuit and be also provided with first interface between light emitting diode display circuit and chip EPM7128SLC84-15N and arrange pin group, described 8 × 8 lattice display circuit and be also provided with the second interface between charactron group display circuit and chip EPM7128SLC84-15N and arrange pin group; Described feed circuit and one digit number code pipe display circuit, light emitting diode display circuit, between 8 × 8 lattice display circuit and charactron group display circuit, be provided with power control circuit.
Further, described one digit number code pipe display circuit, light emitting diode display circuit, 8 × 8 lattice display circuit and charactron group display circuit include the latch that model is 74373, described power control circuit comprises one No. four locking switches, four input ends of described No. four locking switches are connected with the output terminal of feed circuit, and four output terminals are connected respectively by the latch enable end of resistance with the latch of one digit number code pipe display circuit, light emitting diode display circuit, 8 × 8 lattice display circuit and charactron group display circuit.
Further, described feed circuit comprise source of stable pressure feed circuit, adapter feed circuit and USB feed circuit.
Between the main control chip of this programme and each experiment module, the row's of employing pin plugs flexibly, does not need welding circuit and fast changeable when damage.This platform selectivity can be implemented five people and decides by vote the elementary teaching experiments such as the variable add subtract counter experiment of experiment, the experiment of excess-three code translation circuit, the experiment of four full adders, binary-coded decimal-Seven pieces digital displaying code translator experiment, data selector integrated application experiment (blood group matching test circuit), counting clock Comprehensive Experiment, step-length and simple and easy traffic light controller by display interface circuit.Simultaneously by power control circuit operation circuit, be only communicated with the display section needing the experiment module run, prevent all the other experiment modules from causing interference, reduce the power consumption of whole brassboard simultaneously.And according to different demand, select three kinds of power supply modes to be system power supply.By carrying out verifying and lecture experiment in this platform, operator being grasped as early as possible and controls and realize principle.
Accompanying drawing explanation
Fig. 1 is system construction drawing of the present utility model;
Fig. 2 is the circuit connection diagram of programmable logic chip of the present utility model;
Fig. 3 is the structural drawing of Independent keys circuit of the present utility model;
Fig. 4 is the structural drawing of power control circuit of the present utility model;
Fig. 5 is the concrete implementing circuit of one of feed circuit of the present utility model.
Embodiment
Below in conjunction with drawings and Examples, the utility model will be further described.
A kind of FPGA test and verification platform, comprise programmable logic chip 1 and experiment module, described programmable logic chip 1 is provided with the jtag interface 5 for program downloads, feed circuit 2 are powered for programmable logic chip 1 and experiment module, and clock signal occurs and selection circuit 3 provides clock signal for programmable logic chip 1.Programmable MAX7000S family chip in described programmable logic chip 1 selective system, concrete model is EPM7128SLC84-15N, and the I/O port of chip EPM7128SLC84-15N is communicated with corresponding experimental circuit in experiment module between experiment module by arranging pin selectivity.As shown in Figure 2, chip EPM7128SLC84-15N arranges pin by YJ1, YJ2, YJ3, YJ4 tetra-and is drawn by terminal, be the extraction row pin of chip EPM7128SLC84-15N, the specification of 20P selected by these four row's pins, the IO port numbering of the corresponding chip of its each terminal.
As conventional tutoring system, the experiment module of this programme comprises Independent keys circuit 4, one digit number code pipe display circuit 9, light emitting diode display circuit 10,8 × 8 lattice display circuit 11 and charactron group display circuit 12, decides by vote the elementary teachings such as the variable add subtract counter experiment of experiment, the experiment of excess-three code translation circuit, the experiment of four full adders, binary-coded decimal-Seven pieces digital displaying code translator experiment, data selector integrated application experiment (blood group matching test circuit), counting clock Comprehensive Experiment, step-length and simple and easy traffic light controller test to meet five people.Wherein, Independent keys circuit 4 is connected with IO75 ~ 84 port of chip EPM7128SLC84-15N by YJ4, as shown in Figure 3, button SW0 ~ SW7 is connected by button non-locking switch S B1 and YJ4 correspondence Independent keys circuit 4, so that YJ4 is multiplexing in other experiment after SB1 tripping; Except this, stake resistance group RP1 and R14 forms loop, converts push button signalling S0 ~ S7 to low and high level signal, and SB2 is ping-pong type toggle switch, plays locking action.
One digit number code pipe display circuit 9 and light emitting diode display circuit 10 and the extraction of chip EPM7128SLC84-15N are arranged and are arranged pin group 6 selectivity by first interface between pin and be connected.Conventional one digit number code pipe display circuit 9 comprises a charactron and a model is the latch of 74373; And light emitting diode display circuit 10 also multiselect 8 light emitting diodes, model are latch and a stake resistance group composition of 74373.Both can share row's pin of a 20P to be communicated with the extraction row pin of the IO port of chip EPM7128SLC84-15N, are namely that first interface row pin group 6 needs row's pin of a 20P to form.
In like manner, described 8 × 8 lattice display circuit 11 and charactron group display circuit 12 and the extraction of chip EPM7128SLC84-15N are arranged and are arranged pin group 8 selectivity by the second interface between pin and be connected.8 × 8 conventional lattice display circuit 11 and charactron group display circuit 12 generally need adopt two models to be the latch of 74373, and therefore the second interface row pin group 8 needs row's pin of two 20P.
Described power control circuit 7 as shown in Figure 4, comprise one No. four locking switch SB3, four input ends of described No. four locking switch SB3 are connected with the output terminal VCC of feed circuit 2, and respectively by resistance, its four output terminals are drawn, the latch enable end of the latch of its output terminal LE373-ld1 corresponding one digit number code pipe display circuit 9, the latch enable end of the latch of output terminal LE373-ld8 corresponding charactron group display circuit 12, the latch enable end of the latch of output terminal LE373-lp respective leds display circuit 10, the latch enable end of the latch of output terminal LE373-dz correspondence 8 × 8 lattice display circuit 11.
Described feed circuit 2 comprise source of stable pressure feed circuit 2, adapter feed circuit 2 and USB feed circuit 2, and as shown in Figure 5, wherein source of stable pressure feed circuit 2 are drawn by source of stable pressure interface, provide the output terminal connecting valve button JMP4 of system power supply; Adapter feed circuit 2, by adapter extraction voltage, are modulated to suitable voltage through voltage stabilizer LM317 further, provide the output terminal connecting valve button JMP5 of system power supply; USB feed circuit 2 are powered by USB interface, provide the output terminal connecting valve button JMP6 of system power supply.JMP4, JMP5 and JMP6 are all connected to switch key JMP7, determine whether be energized by JMP7.
" EDA technology and VHDL contrived experiment instruct " teaching material that the working procedure that this platform adopts is published with reference to publishing house of Xian Electronics Science and Technology University in August, 2012, repeats no more here.
Claims (4)
1. a FPGA test and verification platform, comprise programmable logic chip and experiment module, described programmable logic chip is provided with jtag interface, programmable logic chip is connected with feed circuit and clock signal occurs and selection circuit, it is characterized in that: the model of described programmable logic chip is EPM7128SLC84-15N, the IO port of chip EPM7128SLC84-15N is connected by arranging pin selectivity with between experiment module.
2. FPGA test and verification platform according to claim 1, is characterized in that: described experiment module comprises Independent keys circuit, one digit number code pipe display circuit, light emitting diode display circuit, 8 × 8 lattice display circuit and charactron group display circuit; Described one digit number code pipe display circuit and be also provided with first interface between light emitting diode display circuit and chip EPM7128SLC84-15N and arrange pin group, described 8 × 8 lattice display circuit and be also provided with the second interface between charactron group display circuit and chip EPM7128SLC84-15N and arrange pin group; Described feed circuit and one digit number code pipe display circuit, light emitting diode display circuit, between 8 × 8 lattice display circuit and charactron group display circuit, be provided with power control circuit.
3. FPGA test and verification platform according to claim 2, it is characterized in that: described one digit number code pipe display circuit, light emitting diode display circuit, 8 × 8 lattice display circuit and charactron group display circuit include the latch that model is 74373, described power control circuit comprises one No. four locking switches, four input ends of described No. four locking switches are connected with the output terminal of feed circuit, and four output terminals are respectively by resistance and one digit number code pipe display circuit, light emitting diode display circuit, 8 × 8 lattice display circuit are connected with the latch enable end of the latch of charactron group display circuit.
4. FPGA test and verification platform according to any one of claim 1 to 3, is characterized in that: described feed circuit comprise source of stable pressure feed circuit, adapter feed circuit and USB feed circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420581377.6U CN204087575U (en) | 2014-10-09 | 2014-10-09 | FPGA test and verification platform |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420581377.6U CN204087575U (en) | 2014-10-09 | 2014-10-09 | FPGA test and verification platform |
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| Publication Number | Publication Date |
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| CN204087575U true CN204087575U (en) | 2015-01-07 |
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| CN201420581377.6U Active CN204087575U (en) | 2014-10-09 | 2014-10-09 | FPGA test and verification platform |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105259831A (en) * | 2015-10-26 | 2016-01-20 | 中国人民解放军军械工程学院 | Universal FPGA debugging device |
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2014
- 2014-10-09 CN CN201420581377.6U patent/CN204087575U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105259831A (en) * | 2015-10-26 | 2016-01-20 | 中国人民解放军军械工程学院 | Universal FPGA debugging device |
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