CN105259831A - Universal FPGA debugging device - Google Patents
Universal FPGA debugging device Download PDFInfo
- Publication number
- CN105259831A CN105259831A CN201510699665.0A CN201510699665A CN105259831A CN 105259831 A CN105259831 A CN 105259831A CN 201510699665 A CN201510699665 A CN 201510699665A CN 105259831 A CN105259831 A CN 105259831A
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- input
- signal
- fpga
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/23—Pc programming
- G05B2219/23283—Debugging, breakpoint
Abstract
The invention discloses a universal FPGA debugging device, and relates to the technical field of data processing device debugging devices. The device comprises an FPGA input signal shaping circuit, a signal input socket, a signal output socket, an FPGA output signal display circuit, and a power circuit. The FPGA input signal shaping circuit is connected with the input end of the signal input socket; the output end of the signal input socket is connected with the input end of the I/O interface of an FPGA to be debugged; the output end of the I/O interface of the FPGA to be debugged is connected with the input end of the signal output socket; the output end of the signal output socket is connected with the input end of the FPGA output signal display circuit; and the power circuit is connected with the power input ends of the modules needing power supply in the device. The device has the characteristics of simple structure, low manufacture cost, and high universality.
Description
Technical field
The present invention relates to the debugging apparatus technical field of data processing equipment, particularly relate to a kind of general FPGA debugging apparatus.
Background technology
Along with improving constantly of integrated circuit technology, on-site programmable gate array FPGA (Field-ProgrammableGateArray) is as special IC (ASIC, Application-Speci cIntegratedCircuit) a kind of semi-custom circuit in field and occurring, the logical block of FPGA can change according to the needs of user with being connected, FPGA by editable connection, the logical block of FPGA inside coupled together, so can complete required logic function.Before program is formally solidified fpga chip, need to power up debugging to FPGA program, during debugging, usually need multichannel input signal and multipath output signals.The FPGA development board of general purchase, is all develop for the fpga chip of a certain specific model specially, can not be used for the debugging of other model fpga chip.If buy the FPGA development board of Multiple Type, can greatly increase exploitation debugging cost undoubtedly, and existing FPGA development board structure is comparatively complicated, further increases cost.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of general FPGA debugging apparatus, and described device has that structure is simple, the feature of low cost of manufacture, highly versatile.
For solving the problems of the technologies described above, the technical solution used in the present invention is: a kind of general FPGA debugging apparatus, it is characterized in that: comprise FPGA input signal and form circuit, signal input socket, signal accessory power outlet, FPGA output signal display circuit and power circuit, the input end that described FPGA input signal forms circuit and signal input socket connects, and described FPGA input signal forms circuit for generation of low and high level signal; The output terminal of described signal input socket is connected with the input end of the I/O interface of FPGA to be debugged, for FPGA input signal being formed the low and high level signal converting extremely FPGA to be debugged that circuit produces; The output terminal of the I/O interface of FPGA to be debugged is connected with the input end of signal accessory power outlet, outputs signal display circuit for the output signal of FPGA to be debugged being forwarded to FPGA; The input end that output terminal and the FPGA of signal accessory power outlet output signal display circuit is connected, for showing the I/O interface output signal state of FPGA to be debugged; Described power circuit is connected with needing the power input of the module of powering in described device, for providing working power for it.
Further technical scheme is: described FPGA input signal forms circuit and comprises more than one input signal forming unit, each input signal forming unit comprises a switch S and two resistance R, one end of switch S is the input end of input signal forming unit, the other end of switch S is connected with one end of two resistance R respectively, the other end ground connection of one of them resistance R, the other end of another resistance R is the output terminal of input signal forming unit, the output terminal of input signal forming unit is connected with the signal input part of signal input socket, the input end of described input signal forming unit is the input end that described FPGA input signal forms circuit.
Further technical scheme is: described FPGA outputs signal the output signal display unit that display circuit comprises one or more, each output signal display unit comprises a current-limiting resistance and a LED, one end of described current-limiting resistance is the input end of described output signal display unit, the other end of current-limiting resistance is connected with the anode of LED, the plus earth of LED, the output terminal of described signal accessory power outlet is connected with the input end of output signal display unit.
Further technical scheme is: described power module comprises power switch SW and power conversion chip VR1, power module comprises two input ends, first input end of power module is directly connected with an input end of power switch SW, the input termination 3.3V power supply of this power module; Second input end of power module is connected with the input end of power conversion chip VR1, the input termination 5V power supply of this power module, the output terminal of power conversion chip VR1 is connected with another input end of power switch SW, the output terminal of power conversion chip VR1 is 3.3V, the output terminal of power switch SW is the power output end of described power module, and the input end that described power output end and FPGA input signal form circuit is connected.
Further technical scheme is: described power conversion chip VR1 uses LM1085 type power conversion chip.
The beneficial effect adopting technique scheme to produce is: described device forms circuit by FPGA input signal and produces long or short low and high level as required, input FPGA to be debugged, then output signal by FPGA the output signal that FPGA Debugging observed by display circuit, complete debug process.In described device, the formation of FPGA input signal circuit, signal input socket, signal accessory power outlet and FPGA output signal display circuit can adjust according to actual needs, highly versatile, and described device only includes the basic electronic component such as switch, resistance and LED, structure is simple, low cost of manufacture.
Accompanying drawing explanation
Fig. 1 is the theory diagram of device of the present invention;
Fig. 2 is the schematic diagram of power module of the present invention;
Fig. 3 is the schematic diagram that in the present invention, FPGA input signal forms circuit;
Fig. 4 is the schematic diagram of signal input socket in the present invention;
Fig. 5 is the schematic diagram of signal accessory power outlet in the present invention;
Fig. 6 is the partial schematic diagram that FPGA of the present invention outputs signal display circuit.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only a part of embodiment of the present invention, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
As shown in Figure 1, the invention discloses a kind of general FPGA debugging apparatus, comprise FPGA input signal and form circuit, signal input socket, signal accessory power outlet, FPGA output signal display circuit and power circuit.The input end that described FPGA input signal forms circuit and signal input socket connects, and described FPGA input signal forms circuit for generation of low and high level signal; The output terminal of described signal input socket is connected with the input end of the I/O interface of FPGA to be debugged, and for FPGA input signal being formed the low and high level signal converting extremely FPGA to be debugged that circuit produces, signal input socket as shown in Figure 4.The output terminal of the I/O interface of FPGA to be debugged is connected with the input end of signal accessory power outlet, and output signal display circuit for the output signal of FPGA to be debugged being forwarded to FPGA, signal accessory power outlet as shown in Figure 5; The input end that output terminal and the FPGA of signal accessory power outlet output signal display circuit is connected, for showing the I/O interface output signal state of FPGA to be debugged; Described power circuit is connected with needing the power input of the module of powering in described device, for providing working power for it.
As shown in Figure 3, described FPGA input signal forms circuit and comprises more than one input signal forming unit, each input signal forming unit comprises a switch S and two resistance R, one end of switch S is the input end of input signal forming unit, the other end of switch S is connected with one end of two resistance R respectively, the other end ground connection of one of them resistance R, the other end of another resistance R is the output terminal of input signal forming unit, the output terminal of input signal forming unit is connected with the signal input part of signal input socket, the input end of described input signal forming unit is the input end that described FPGA input signal forms circuit.It is pointed out that the number of described input signal forming unit can be arranged according to the I/O input interface number of FPGA to be debugged.
When pressing switch S, 3.3V voltage signal, by the I/O input pin of the resistance R on input signal forming unit output terminal, signal input socket access FPGA, simulates high level " 1 ".When release-push, 3.3V voltage signal disconnects, the resistance R ground connection that the I/O pin of corresponding FPGA is cascaded by two, simulation low level " 0 ".By controlling to press the time with release-push S, instantaneous or long-time " 1 ", " 0 " signal can be simulated.
As shown in Figure 4, described FPGA outputs signal the output signal display unit that display circuit comprises one or more, each output signal display unit comprises a current-limiting resistance and a LED, one end of described current-limiting resistance is the input end of described output signal display unit, the other end of current-limiting resistance is connected with the anode of LED, the plus earth of LED, the output terminal of described signal accessory power outlet is connected with the input end of output signal display unit.It is pointed out that the number of described input signal forming unit can be arranged according to the I/O output interface number of FPGA to be debugged.The voltage signal exported when fpga chip I/O pin is added on LED by current-limiting resistance, and when exporting as " 1 ", LED lights, and when exporting as " 0 ", light emitting diode extinguishes, for judging the output of fpga chip I/O pin according to the on and off of LED.
As shown in Figure 2, described power module comprises power switch SW and power conversion chip VR1, power module comprises two input ends, and first input end of power module is directly connected with an input end of power switch SW, the input termination 3.3V power supply of this power module; Second input end of power module is connected with the input end of power conversion chip VR1, the input termination 5V power supply of this power module, the output terminal of power conversion chip VR1 is connected with another input end of power switch SW, the output terminal of power conversion chip VR1 is 3.3V, the output terminal of power switch SW is the power output end of described power module, and the input end that described power output end and FPGA input signal form circuit is connected.
Preferably, described power conversion chip VR1 uses LM1085 type power conversion chip.An input end of power module uses 5V power voltage supply, and by LM1085,5V input power is converted to the 3.3V voltage identical with fpga chip I/O pin, another input end of power module can select 3.3V power supply directly to power for fpga chip I/O pin.
Described device forms circuit by FPGA input signal and produces long or short low and high level as required, inputs FPGA to be debugged, then outputs signal by FPGA the output signal that FPGA Debugging observed by display circuit, completes debug process.In described device, the formation of FPGA input signal circuit, signal input socket, signal accessory power outlet and FPGA output signal display circuit can adjust according to actual needs, highly versatile, and described device only includes the basic electronic component such as switch, resistance and LED, structure is simple, low cost of manufacture.
Claims (5)
1. a general FPGA debugging apparatus, it is characterized in that: comprise FPGA input signal and form circuit, signal input socket, signal accessory power outlet, FPGA output signal display circuit and power circuit, the input end that described FPGA input signal forms circuit and signal input socket connects, and described FPGA input signal forms circuit for generation of low and high level signal; The output terminal of described signal input socket is connected with the input end of the I/O interface of FPGA to be debugged, for FPGA input signal being formed the low and high level signal converting extremely FPGA to be debugged that circuit produces; The output terminal of the I/O interface of FPGA to be debugged is connected with the input end of signal accessory power outlet, outputs signal display circuit for the output signal of FPGA to be debugged being forwarded to FPGA; The input end that output terminal and the FPGA of signal accessory power outlet output signal display circuit is connected, for showing the I/O interface output signal state of FPGA to be debugged; Described power circuit is connected with needing the power input of the module of powering in described device, for providing working power for it.
2. general FPGA debugging apparatus as claimed in claim 1, it is characterized in that: described FPGA input signal forms circuit and comprises more than one input signal forming unit, each input signal forming unit comprises a switch S and two resistance R, one end of switch S is the input end of input signal forming unit, the other end of switch S is connected with one end of two resistance R respectively, the other end ground connection of one of them resistance R, the other end of another resistance R is the output terminal of input signal forming unit, the output terminal of input signal forming unit is connected with the signal input part of signal input socket, the input end of described input signal forming unit is the input end that described FPGA input signal forms circuit.
3. general FPGA debugging apparatus as claimed in claim 1, it is characterized in that: described FPGA outputs signal the output signal display unit that display circuit comprises one or more, each output signal display unit comprises a current-limiting resistance and a LED, one end of described current-limiting resistance is the input end of described output signal display unit, the other end of current-limiting resistance is connected with the anode of LED, the plus earth of LED, the output terminal of described signal accessory power outlet is connected with the input end of output signal display unit.
4. general FPGA debugging apparatus as claimed in claim 1, it is characterized in that: described power module comprises power switch SW and power conversion chip VR1, power module comprises two input ends, first input end of power module is directly connected with an input end of power switch SW, the input termination 3.3V power supply of this power module; Second input end of power module is connected with the input end of power conversion chip VR1, the input termination 5V power supply of this power module, the output terminal of power conversion chip VR1 is connected with another input end of power switch SW, the output terminal of power conversion chip VR1 is 3.3V, the output terminal of power switch SW is the power output end of described power module, and the input end that described power output end and FPGA input signal form circuit is connected.
5. general FPGA debugging apparatus as claimed in claim 4, is characterized in that: described power conversion chip VR1 uses LM1085 type power conversion chip.
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|---|---|---|---|
| CN201510699665.0A CN105259831A (en) | 2015-10-26 | 2015-10-26 | Universal FPGA debugging device |
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| CN201510699665.0A CN105259831A (en) | 2015-10-26 | 2015-10-26 | Universal FPGA debugging device |
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| CN201510699665.0A Pending CN105259831A (en) | 2015-10-26 | 2015-10-26 | Universal FPGA debugging device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107526585A (en) * | 2016-12-26 | 2017-12-29 | 上海交通大学 | FPGA development platforms and its debugging, method of testing based on Scala |
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| CN107526585B (en) * | 2016-12-26 | 2020-06-09 | 上海交通大学 | Scala-based FPGA development platform and debugging and testing method thereof |
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Application publication date: 20160120 |