CN211698703U - GW1N-4 multifunctional development board - Google Patents
GW1N-4 multifunctional development board Download PDFInfo
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- CN211698703U CN211698703U CN202020034097.9U CN202020034097U CN211698703U CN 211698703 U CN211698703 U CN 211698703U CN 202020034097 U CN202020034097 U CN 202020034097U CN 211698703 U CN211698703 U CN 211698703U
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Abstract
The utility model discloses a GW1N-4 multi-functional development board, including FPGA chip, GPIO circuit, LVDS, power supply circuit, download circuit, clock circuit, LED, slide switch, key switch and reset circuit. The utility model discloses in, the utility model relates to a GW1N-4 multi-functional development board provides fine study and performance verification platform for the user of chip, and the beginner learns the use of familiar software through the development board, newly-built, leading-in file, pin restraint, clock restraint, synthesize, the laying out wiring, download bitstream file, online logic analyzer if the project, the developer downloads the development program to the development board, online logic analyzer of accessible or LED test signal to combine to generate clock analysis document, know the performance of chip.
Description
Technical Field
The utility model relates to a development board technical field especially relates to a multi-functional development board of GW 1N-4.
Background
At present, most of FPGA development boards are development boards of imported chips Altera, Xilinx and Lattice, the development boards of domestic FPGA are few and incomplete, the foreign chip development boards are based on foreign chips, such as chips of Altera, Xilinx and Lattice, the development boards are only suitable for learning the chips, the domestic FPGA chips come out in recent years, but the development momentum is strong, people are exclamated, however, the domestic chips just start to be produced, and the FPGA is rarely produced in 2017. The set of multifunctional development boards was developed for better application of GW 1N-4.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a: the GW1N-4 multifunctional development board is provided for solving the problem of low adaptation degree of foreign development boards and domestic development boards.
In order to achieve the above purpose, the utility model adopts the following technical scheme:
a GW1N-4 multifunctional development board comprises an FPGA chip, a GPIO circuit, LVDS, a power circuit, a download circuit, a clock circuit, an LED, a slide switch, a key switch and a reset circuit:
the model of the FPGA chip is as follows: GW1N-UV4PG256MC 6/I5;
the download circuit of the development board is provided with two types, one type is realized by directly adopting a JATG interface, and the other type is realized by using a USB-to-JATG interface and using a chip FT2232 HL;
an external FLASH is arranged in the development board;
the power circuit uses a DC5V input;
a 50MHz crystal oscillator is arranged in the development board and is connected with a PLL input pin;
an SMA socket is arranged on the outer side of the development plate;
a reset circuit is arranged in the development board and connected with a reset key.
As a further description of the above technical solution:
the power supply circuit adopts an LDO power supply chip.
As a further description of the above technical solution:
the LED lamp developing device is characterized in that a plurality of groups of LED lamps are arranged in the developing board, the LED lamps are respectively connected with the power circuit and the FPGA chip, and the LED lamp connecting circuit is provided with a sliding switch.
As a further description of the above technical solution:
and a key switch is arranged on the outer side of the development board and is connected with the FPGA pin.
As a further description of the above technical solution:
the outer side of the development board is provided with 2 DC3-40P sockets with the distance of 2.54 mm.
As a further description of the above technical solution:
the outer side of the development board is provided with 2 DC3-20P sockets with the distance of 2 mm.
To sum up, owing to adopted above-mentioned technical scheme, the beneficial effects of the utility model are that: the utility model relates to a GW1N-4 multi-functional development board provides fine study and performance verification platform for the user of chip, the beginner learns the use familiar with software through the development board, newly-built, the leading-in file of project, pin restraint, clock restraint, synthesize, the overall arrangement wiring, download the bit stream file, online logic analysis appearance, the developer downloads the development board with development program, online logic analysis appearance of accessible or LED test signal to combine to generate clock analysis document, know the performance of chip.
Drawings
Fig. 1 shows a schematic diagram of a workflow block diagram provided according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.
Referring to fig. 1, the present invention provides a technical solution: a GW1N-4 multifunctional development board comprises an FPGA chip, a GPIO circuit, LVDS, a power circuit, a download circuit, a clock circuit, an LED, a slide switch, a key switch and a reset circuit:
the model of the FPGA chip is as follows: GW1N-UV4PG256MC6/I5 has the characteristics of low power consumption, instant start, low cost, nonvolatility, high safety, rich packaging types, convenience and flexibility in use and the like;
the download circuit of the development board is provided with two types, one type is realized by directly adopting a JATG interface, and the other type is realized by using a USB-to-JATG interface and using a chip FT2232 HL;
an external FLASH is arranged in the development board and used for storing a user program;
the power circuit adopts DC5V input, and the interface has overcurrent protection and reverse protection functions, and overcurrent protection current is 2A;
a 50MHz crystal oscillator is arranged in the development board, and the crystal oscillator is connected with a PLL input pin and used as clock input of the PLL in the FPGA, and the clock required by a user can be output through frequency division and multiplication of the PLL;
an SMA socket is arranged on the outer side of the development board, and meanwhile, for the convenience of user testing, the SMA socket is arranged on the outer side of the development board and serves as a clock input interface, and the clock signal is connected to an FPGA global clock pin;
the development board is internally provided with a reset circuit which is connected with a reset key, the reset circuit is additionally provided for better running the FPGA program, after the power is on, the reset chip automatically generates a reset signal to reset the FPGA, in addition, the FPGA program can be manually reset through the reset key, and the program test is convenient.
Specifically, as shown in fig. 1, the power circuit adopts an LDO power chip, and the LDO power chip is adopted to realize the conversion from 5V to 3.3V, from 3.3V to 2.5V, and from 3.3V to 1.2V, so that the supply current can reach 2A, the input voltage range is 1.425V to 6.5V, and the power requirement of the development board can be met.
Specifically, as shown in fig. 1, a plurality of groups of LED lamps are arranged in the development board, and the plurality of groups of LED lamps are respectively connected with the power circuit and the FPGA chip, and the LED lamp connection circuit is provided with a slide switch, so that the LED lamps can be tested in the following manner: when the output signal of the corresponding pin of the FPGA is at a logic low level, the LED is lightened; when the output signal is at high level, the LED is turned off, and the LED is used for controlling input during user testing through the sliding switch.
Specifically, as shown in fig. 1, a key switch is installed on the outer side of the development board, and the key switch is connected to the FPGA pin, so that a user can input a low level to the corresponding FPGA pin through manual control, and the low level can be used as a test control input.
Specifically, as shown in fig. 1, 2 DC3-40P sockets with a distance of 2.54mm are arranged on the outer side of the development board for facilitating the function expansion and test of users.
Specifically, as shown in fig. 1, 2 DC3-20P sockets with a distance of 2mm are disposed outside the development board for facilitating LVDS test and data communication for users.
The above, only be the concrete implementation of the preferred embodiment of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art is in the technical scope of the present invention, according to the technical solution of the present invention and the utility model, the concept of which is equivalent to replace or change, should be covered within the protection scope of the present invention.
Claims (6)
1. The utility model provides a GW1N-4 multi-functional development board, includes FPGA chip, GPIO circuit, LVDS, power supply circuit, download circuit, clock circuit, LED, slide switch, key switch and reset circuit, its characterized in that:
the model of the FPGA chip is as follows: GW1N-UV4PG256MC 6/I5;
the download circuit of the development board is provided with two types, one type is realized by directly adopting a JATG interface, and the other type is realized by using a USB-to-JATG interface and using a chip FT2232 HL;
an external FLASH is arranged in the development board;
the power circuit uses a DC5V input;
a 50MHz crystal oscillator is arranged in the development board and is connected with a PLL input pin;
an SMA socket is arranged on the outer side of the development plate;
a reset circuit is arranged in the development board and connected with a reset key.
2. The GW1N-4 multi-function development board of claim 1, wherein said power circuit is an LDO power chip.
3. The multifunctional development board for GW1N-4 as claimed in claim 1, wherein multiple sets of LED lamps are installed in the development board, and the multiple sets of LED lamps are respectively connected to the power circuit and the FPGA chip, and the LED lamp connection circuit is installed with a sliding switch.
4. The GW1N-4 multifunctional development board as claimed in claim 1, wherein a key switch is installed on the outer side of the development board, and the key switch is connected with FPGA pins.
5. A GW1N-4 multifunctional development board as claimed in claim 1, wherein said development board is provided with 2 DC3-40P sockets spaced 2.54mm apart on its outer side.
6. The GW1N-4 multifunctional development board of claim 1, wherein 2 DC3-20P sockets with a spacing of 2mm are provided outside the development board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020034097.9U CN211698703U (en) | 2020-01-08 | 2020-01-08 | GW1N-4 multifunctional development board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020034097.9U CN211698703U (en) | 2020-01-08 | 2020-01-08 | GW1N-4 multifunctional development board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211698703U true CN211698703U (en) | 2020-10-16 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CN202020034097.9U Active CN211698703U (en) | 2020-01-08 | 2020-01-08 | GW1N-4 multifunctional development board |
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| CN (1) | CN211698703U (en) |
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2020
- 2020-01-08 CN CN202020034097.9U patent/CN211698703U/en active Active
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