CN208819045U - A kind of FPGA development board - Google Patents
A kind of FPGA development board Download PDFInfo
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- CN208819045U CN208819045U CN201821363767.0U CN201821363767U CN208819045U CN 208819045 U CN208819045 U CN 208819045U CN 201821363767 U CN201821363767 U CN 201821363767U CN 208819045 U CN208819045 U CN 208819045U
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Abstract
The utility model belongs to Embedded Hardware Design technical field, provides a kind of FPGA development board.In the present invention, by using power module, FPGA module, DDR3 module, first memory module, download module, external clock interface module, debugging control module, the FPGA development board that network module and clock module are constituted, so that FPGA module accordingly controls the modules in FPGA development board, the read-write of DDR3 module completion data, the bit stream file and user data of first memory module storage FPGA module, download module is programmed the storage unit in FPGA module, and the bit stream file stored in the first memory module is downloaded, the debugging process of debugging control module control FPGA module, network module provides network interface for FPGA development board, so that the FPGA development board meet different user to this chip Evaluation requirement, and integral layout is reasonable, reliable performance.
Description
Technical field
The utility model belongs to Embedded Hardware Design technical field more particularly to a kind of FPGA development board.
Background technique
With the development of electronic technology, field programmable gate array (Field-Programmable Gate Array,
FPGA) as one in the field specific integrated circuit (Application Specific Integrated Circuit, ASIC)
Kind semi-custom circuit, had not only solved the deficiency of custom circuit, but also overcome the limited disadvantage of original programming device gate circuit number.
Production as FPGA designs manufacturer, the multiple fpga chips of high cloud semiconductor production, and conduct
Family's first generation product, high cloud GW2A-LV18PG256C8/I7 internal resource is abundant, Digital Signal Processing with high performance
(Digital Signal Processing, DSP) resource, high velocity, low pressure differential signal (Low-Voltage Differential
Signaling, LVDS) interface and memory resource abundant, FPGA architecture that these embedded resources collocation are simplified and
55nm technique makes GW2A Series FPGA product be suitable for the inexpensive application of high speed.
Although however, fpga chip GW2A-LV18PG256C8/I7 be suitable for high speed low cost application,
The evaluation board of the characteristics of currently on the market there are no based on the chip and possible application scenarios.
Therefore, it is necessary to a kind of technical solution is provided, to solve the above technical problems.
Utility model content
The purpose of this utility model is to provide a kind of FPGA development boards, and integral layout is reasonable, reliable performance, can meet
The evaluation requirement to this chip of different user.
The utility model is realized in this way a kind of FPGA development board, the FPGA development board include:
Power module, for providing power supply for the modules in the FPGA development board；
FPGA module is connect with the power module, corresponding for carrying out to the modules in the FPGA development board
Control；
DDR3 module is connect with the FPGA module, for completing the read-write of data；
First memory module is connect with the FPGA module, for storing the bit stream file of the FPGA module and using
User data；
Download module is connect with the FPGA module, for being programmed to the storage unit in the FPGA module, with
And the bit stream file stored in first memory module is downloaded；
External clock interface module is connect with the FPGA module, for providing clock interface for the FPGA module；
Debugging control module is connect with the FPGA module, for controlling the debugging process of the FPGA module；
Network module is connect with the FPGA module, for providing network interface for the FPGA development board；
Clock module, with the power module, the FPGA module, the DDR3 module, first memory module, institute
State download module and the network module connection, for the power module, the FPGA module, the DDR3 module,
First memory module, the download module and the network module provide corresponding work clock.
In the present invention, by using power module, FPGA module, DDR3 module, the first memory module, downloading mould
The FPGA development board that block, external clock interface module, debugging control module, network module and clock module are constituted, so that
FPGA module accordingly controls the modules in FPGA development board, and DDR3 module completes the read-write of data, the first storage
Module stores the bit stream file and user data of FPGA module, and download module compiles the storage unit in FPGA module
Journey, and the bit stream file stored in the first memory module is downloaded, debugging control module controls the tune of FPGA module
Examination process, network module provide network interface for FPGA development board, so that the FPGA development board meets pair of different user
The evaluation requirement of this chip, and integral layout is reasonable, reliable performance.
Detailed description of the invention
Fig. 1 is the modular structure schematic diagram of FPGA development board provided by an embodiment of the present invention；
Fig. 2 is the electrical block diagram of FPGA development board provided by another embodiment of the utility model.
Specific embodiment
In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with attached drawing and implementation
Example, the present invention will be further described in detail.It should be appreciated that specific embodiment described herein is only used to explain
The utility model is not used to limit the utility model.
The realization of the utility model is described in detail below in conjunction with specific attached drawing:
Fig. 1 shows the modular structure of FPGA development board provided by an embodiment of the present invention, for ease of description,
Only the parts related to this embodiment are shown, and details are as follows:
As shown in Figure 1, FPGA development board 10 provided by the utility model embodiment includes: power module 100, FPGA mould
Block 101, DDR3 module 102, the first memory module 103, download module 104, external clock interface module 105, debugging control mould
Block 106, network module 107 and clock module 108.
Specifically, power module 100, for providing power supply for the modules in FPGA development board.
Wherein, in the utility model embodiment, power module 100 is mainly using power supply chip, filter capacitor, configuration electricity
The power circuit of resistance composition is realized, includes 7 power supply chips in the power circuit, respectively 3 ONSEMI companies
The TPS51200 power supply of NCP3170ADR2G power supply chip, the TPS7A7001 power supply chip of 3 TI companies and 1 TI company
Chip.When it is implemented, the NCP3170ADR2G power supply chip of 3 ONSEMI companies, export electric current 3A, and generate 3.3V,
The supply voltage of 1.5V and 1.0V, the TPS7A7001 power supply chip of 3 TI companies, export electric current 2A, and generate 2.5V,
1.2V and all the way backup power source, the TPS51200 power supply chip of 1 TI company, 0.75V power supply needed for generating DDR3 chip.
It should be noted that in the utility model embodiment, the particular circuit configurations of power module 100 with no restrictions,
It can refer to the existing power supply circuit of the composition of NCP3170ADR2G power supply chip, TPS7A7001 power supply chip and TPS51200.
Further, FPGA module 101 are connect with power module 100, for the modules in FPGA development board into
The corresponding control of row.
Wherein, in the utility model embodiment, FPGA module 101 is by fpga chip, 50MHz crystal oscillator and peripheral resistor-capacitor unit
Composition, is the core of entire FPGA development board 10, and the FPGA module 101 can open entire FPGA by internal processes
The peripheral module of hair plate 10 carries out control operation.
When it is implemented, the fpga chip in FPGA module 101 uses high cloud semiconductor GW2A-LV18PG256C8/I7 core
Piece realizes that the fpga chip can control in its FPGA development board 10 when user tests it by FPGA development board 10
Modules carry out reading and writing data, high-speed communication etc..
Further, DDR3 module 102 is connect with FPGA module 101, for completing the read-write of data.
Wherein, in the utility model embodiment, DDR3 module 102 is made of DDR3 chip and peripheral resistor-capacitor unit, and
It is connected by its internal data/address bus, address bus and control bus with FPGA module 101, to complete the read-write of data.
When it is implemented, DDR3 chip is realized using the MT41J128M16JT-125:K chip of MICRON company, the chip
Including 6 bit data bus, memory space 2Gbit, packaged type is FBGA 96-ball (8mm*14mm), and data rate is
1600MT/s。
In the present embodiment, by the way that DDR3 module 102 is arranged in FPGA development board 10, so that user is developed using FPGA
Plate 10 carries out when exploitation is tested, it can be achieved that high-speed communication fpga chip GW2A-LV18PG256C8/I7.
Further, the first memory module 103 is connect with FPGA module 101, for storing the bit of FPGA module 101
Stream file and user data.
Wherein, in the utility model embodiment, the first memory module 103 is formed using FLASH chip and peripheral circuit,
Its data volume that can store 64Mbit, can be used for the bit stream file or user data of storage configuration FPGA module 101, and pass through
Serial Peripheral Interface (SPI) (Serial Peripheral Interface, SPI) is communicated with FPGA module 101；It should be noted that
When it is implemented, the W25Q64FVSSIG chip that WINBOND company can be used in FLASH chip is realized.
Further, download module 104 are connect with FPGA module 101, for the storage unit in FPGA module 101
It is programmed, and the bit stream file stored in the first memory module 103 is downloaded.
Wherein, in the utility model embodiment, download module 104 by chip FT2232HL, MINI-USB interface,
The circuit elements such as 12MHz crystal, protection diode and resistor-capacitor unit composition.Specifically, being arrived using FT2232HL chip by USB
The protocol conversion function of JTAG is realized and is programmed to the SRAM of fpga chip, and carries out bit stream file download to external Flash.
Further, external clock interface module 105 is connect with FPGA module 101, for providing for FPGA module 101
Clock interface.
Wherein, in the utility model embodiment, external clock interface module 105 can be mentioned by outside source for FPGA
For the clock of different frequency, to meet practical application request.When it is implemented, external clock interface module 105 is using Yangzhou essence
The JC3.660.046-1SMA interface of sincere electronics corporation's production realizes that the interface is the outer spiral shell inner hole base of 5 foot straight cuttings.
Further, debugging control module 106 is connect with FPGA module 101, for controlling the debugging of FPGA module 101
Process.
Wherein, in the utility model embodiment, debugging control module 106 is mainly used for user to fpga chip
When GW2A-LV18PG256C8/I7, test scene is switched over depending on the user's operation and test process is controlled, so as to
Exploitation test is carried out to fpga chip in user.
When it is implemented, debugging control module 106 is connect key switch and is constituted by multiple touch, it is multiple touch connect key switch with
FPGA module 101 connects, it is preferred that multiple touch connects key switch the switch element of model TL1105F160Q can be used
It realizes.
In addition, in other embodiments, when it is implemented, debugging control module 106 is made of multiple slide switches, it is multiple
Slide switch is connect with FPGA module 101, it is preferred that the switch element that signal is EG1218 can be used in multiple slide switch
It realizes.
In the utility model embodiment, using slide switch or reality of the key switch as debugging control module 106 is connect
Existing structure, so that user can manually control the programming jump that fpga chip is developed in test process by key and switch,
Simple and convenient for operation and mode is various.
Further, network module 107 are connect with FPGA module 101, for providing network interface for FPGA development board.
Wherein, in the utility model embodiment, network module 107 is by 2 RJ45 connectors, 2 PHY chips, 2
25MHz crystal oscillator, status display LED and resistor-capacitor unit composition realize the two-way Ethernet interface setting of FPGA development board 10.
When it is implemented, PHY chip is real using the B50610C1KML Ethernet chip of Broadcom company production
Existing, Ethernet chip B50610C1KML can support 10M, 100M, 1000M ethernet communication.It should be noted that
In the utility model embodiment, shown by 2 RJ45 connectors, 2 PHY chip B50610C1KML, 2 25MHz crystal oscillators, states
Show that the specific structure of the network module 107 of LED and resistor-capacitor unit composition can refer to the prior art, details are not described herein again.
In the present embodiment, network module 107 is set on FPGA development board 10, realizes the network of FPGA development board 10
Interface setting, and user is made to download bit stream file when fpga chip exploitation is tested by network.
Further, clock module 108 store mould with power module 100, FPGA module 101, DDR3 module 102, first
Block 103, download module 104 and network module 107 connect, and are used for power module 100, FPGA module 101, DDR3 module
102, the first memory module 103, download module 104 and network module 107 provide corresponding work clock.
Wherein, in the utility model embodiment, clock module 108 includes three kinds of clock sources, respectively all the way 50MHz
Clock, two-way 25MHz clock and all the way 12MHz clock, the three roads clock source be respectively fpga chip, 2 PHY chips and
FT2232HL provides clock signal.
When it is implemented, the 7C- of TXC company is respectively adopted in 50MHz clock source, 25MHz clock source and 12MHz clock source
The crystal of the crystal oscillator of 50.000MCA-T model, the crystal oscillator of 7C-25.000MBB-T model and 7B-12.000MAAJ-T model is real
It is existing.
Further, as one preferred embodiment of the utility model, as shown in Fig. 2, FPGA development board 10 further includes
Two memory modules 109.
Specifically, second memory module 109 is connect with FPGA module 101, for storing user data.
Wherein, in the utility model embodiment, the second memory module 109 is realized using SD card module, the SD card module
It is made of, can be communicated with fpga chip by clock line, order wire and data line SD card seat and peripheral resistor-capacitor unit, realize SD card
Read-write, while there is plug-in card detection function.When it is implemented, SD card seat uses the SD-503182 model of MOLEX company production
Deck realizes that the model pushes away -8 contact miniature SD card seat of pushing-type.
Further, as one preferred embodiment of the utility model, as shown in Fig. 2, the utility model embodiment provides
FPGA development board further include universal input/output interface module 110.
Specifically, universal input/output interface (General Purpose Input Output, the GPIO) module 110 with
FPGA module 101 connects, for providing input/output interface for FPGA development board.
When it is implemented, GPIO interface is made of the double contact pin of two the first default spacing, one of them is double for 20 feet
Socket needle, another is the double contact pin of 30 feet, and the spacing between two contact pins of each double contact pin is preferably 2.54 millimeters；
In addition, guiding to above-mentioned contact pin after series resistance.Series connection group queues the effect for improving signal quality and protecting port I/O.
Further, as one preferred embodiment of the utility model, as shown in Fig. 2, the utility model embodiment provides
FPGA development board 10 further include Low Voltage Differential Signal transceiver interface module 111.
Specifically, the Low Voltage Differential Signal transceiver interface module 111 is connect with FPGA module 101, for developing for FPGA
Plate provides differential signal input/output interface.
When it is implemented, double pin groups of the Low Voltage Differential Signal transceiver interface module 111 by two the second default spacing
At, and the spacing between each double contact pin is preferably 2 millimeters.Wherein, a double contact pin is Low Voltage Differential Signal transmission
Interface, another double contact pin is Low Voltage Differential Signal receiving interface, and transmission interface directly believes the difference of fpga chip
Number draw, receiving interface by 100 Ohmic resistances to differential pair matching after draws, with this make user can using this interface complete
Assessment to high-speed differential signal communication.
Further, as one preferred embodiment of the utility model, as shown in Fig. 2, the utility model embodiment provides
FPGA development board 10 further include debugging indicating module 112.
Wherein, debug indicating module 112, connect with FPGA module 101, for the debugging process to FPGA module 101 into
Row instruction.
When it is implemented, LED light realization can be used in debugging indicating module 112, make FPGA development board 10 that can show tune
Test result, it is user-friendly.
In the present embodiment, the utility model is directed to the GW2A-LV18PG256C8/I7FPGA chip of high cloud semiconductor, if
A FPGA development board 10 is counted, which has external interface abundant, such as LVDS interface, Ethernet interface, SD card
Seat and GPIO interface facilitate user to carry out a variety of application debugging；In addition, the FPGA development board has storage resource abundant, outside
DDR3SDRAM chip and FLASH chip are hung, facilitates user's storage using data and FPGA code program.
In the present invention, by using power module, FPGA module, DDR3 module, the first memory module, downloading mould
The FPGA development board that block, external clock interface module, debugging control module, network module and clock module are constituted, so that
FPGA module accordingly controls the modules in FPGA development board, and DDR3 module completes the read-write of data, the first storage
Module stores the bit stream file and user data of FPGA module, and download module compiles the storage unit in FPGA module
Journey, and the bit stream file stored in the first memory module is downloaded, debugging control module controls the tune of FPGA module
Examination process, network module provide network interface for FPGA development board, so that the FPGA development board meets pair of different user
The evaluation requirement of this chip, and integral layout is reasonable, reliable performance.
The above is only the preferred embodiment of the utility model only, is not intended to limit the utility model, all at this
Made any modifications, equivalent replacements, and improvements etc., should be included in the utility model within the spirit and principle of utility model
Protection scope within.
Claims (9)
1. a kind of FPGA development board, which is characterized in that the FPGA development board includes:
Power module, for providing power supply for the modules in the FPGA development board；
FPGA module is connect with the power module, for accordingly being controlled the modules in the FPGA development board；
DDR3 module is connect with the FPGA module, for completing the read-write of data；
First memory module is connect with the FPGA module, for storing the bit stream file and number of users of the FPGA module
According to；
Download module is connect with the FPGA module, for being programmed to the storage unit in the FPGA module and right
The bit stream file stored in first memory module is downloaded；
External clock interface module is connect with the FPGA module, for providing clock interface for the FPGA module；
Debugging control module is connect with the FPGA module, for controlling the debugging process of the FPGA module；
Network module is connect with the FPGA module, for providing network interface for the FPGA development board；
Clock module, with the power module, the FPGA module, the DDR3 module, first memory module, it is described under
Module and network module connection are carried, for the power module, FPGA module, the DDR3 module, described
First memory module, the download module and the network module provide corresponding work clock.
2. FPGA development board according to claim 1, which is characterized in that the FPGA development board further include:
Second memory module is connect, for storing user data with the FPGA module.
3. FPGA development board according to claim 1, which is characterized in that the FPGA development board includes:
Universal input/output interface module is connect with the FPGA module, for providing input and output for the FPGA development board
Interface.
4. FPGA development board according to claim 3, which is characterized in that the universal input/output interface module is by two
The double contact pin of first default spacing is constituted.
5. FPGA development board according to claim 1, which is characterized in that the FPGA development board includes:
Low Voltage Differential Signal transceiver interface module, connect with the FPGA module, for providing difference for the FPGA development board
Signal input output interface.
6. FPGA development board according to claim 5, which is characterized in that the Low Voltage Differential Signal transceiver interface module by
The double contact pin composition of two the second default spacing, one of them double contact pin are Low Voltage Differential Signal transmission interface, another
Double contact pin is Low Voltage Differential Signal receiving interface.
7. FPGA development board according to claim 1, which is characterized in that the debugging control module connects key by multiple touch
Switch is constituted, and the multiple touch connects key switch and connect with the FPGA module.
8. FPGA development board according to claim 1, which is characterized in that the debugging control module is by multiple slide switches
Composition, the multiple slide switch are connect with the FPGA module.
9. FPGA development board according to claim 1, which is characterized in that the FPGA development board further include:
Indicating module is debugged, connect with the FPGA module, is indicated for the debugging process to the FPGA module.
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| CN201821363767.0U CN208819045U (en) | 2018-08-22 | 2018-08-22 | A kind of FPGA development board |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111555949A (en) * | 2019-10-30 | 2020-08-18 | 江苏云涌电子科技股份有限公司 | VPN application development platform and monitoring method thereof |
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- 2018-08-22 CN CN201821363767.0U patent/CN208819045U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111555949A (en) * | 2019-10-30 | 2020-08-18 | 江苏云涌电子科技股份有限公司 | VPN application development platform and monitoring method thereof |
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