CN208861280U - A kind of FPGA development board for DDR3 memory bar - Google Patents
A kind of FPGA development board for DDR3 memory bar Download PDFInfo
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- CN208861280U CN208861280U CN201821397900.4U CN201821397900U CN208861280U CN 208861280 U CN208861280 U CN 208861280U CN 201821397900 U CN201821397900 U CN 201821397900U CN 208861280 U CN208861280 U CN 208861280U
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Abstract
The utility model belongs to Embedded Hardware Design technical field, provides a kind of FPGA development board for DDR3 memory bar.In the present invention, by using including DDR3 slot, fpga chip, memory configures chip, power module, download module, the FPGA development board for DDR3 memory bar of network module and clock module, so that DDR3 slot grafting DDR3 memory bar, fpga chip controls DDR3 memory bar and carries out high-speed data read-write, memory configures the application program for powering on bootstrap loading of chip storage fpga chip, power module provides power supply for corresponding device in FPGA development board, download module is programmed the storage unit in fpga chip, and the application program stored in memory configuration chip is downloaded, network module provides network interface for FPGA development board, clock module provides the driving clock of programming in logic to fpga chip, so that The FPGA development board of the onboard DDR3 slot the needs of can not only having met high-speed data acquisition and handle in real time, but also reduces the difficulty of pcb board Networking Design.
Description
Technical field
The utility model belongs to Embedded Hardware Design technical field more particularly to a kind of FPGA for DDR3 memory bar
Development board.
Background technique
With the high speed development of modern science and technology, in industrial production and scientific research, such as satellite communication, high speed image
The fields such as processing, high sDeed real-time digital signal processing, it is generally existing that high-speed high capacity, strong real-time and high bandwidth are carried out to data
Processing requirement.Currently, due to field programmable gate array (Field- Programmable Gate Array, FPGA) core
Piece has the special purpose interface for supporting external high speed memory devices, therefore fpga chip is more as the core element of system
Applied to fields such as communication, storage and performance applications.
Currently, one or more pieces plug-in DDR3 storage chips of fpga chip become in high-speed real-time design of memory systems
Preferred option.However, since DDR3 storage chip has the sample frequency and more balancings of high speed, greatly
Increase the difficulty of user's printed circuit (Printed Circuit Board, PCB) Networking Design.
Therefore, it is necessary to a kind of technical solution is provided, to solve the above technical problems.
Utility model content
The purpose of this utility model is to provide a kind of FPGA development boards for DDR3 memory bar, can both meet high speed
The demand that data are acquired and handled in real time, while the difficulty of pcb board Networking Design is reduced again.
The utility model is realized in this way a kind of FPGA development board for DDR3 memory bar, described in DDR3
The FPGA development board for depositing item includes:
DDR3 slot is used for grafting DDR3 memory bar；
Fpga chip is connect with the DDR3 slot, carries out high-speed data read-write for controlling the DDR3 memory bar；
Memory configures chip, connect with the fpga chip, for storing the bootstrap loading that powers on of the fpga chip
Application program；
Power module is connect, for being described with the fpga chip, memory configuration chip and the DDR3 slot
Fpga chip, memory configuration chip and the DDR3 memory bar provide power supply；
Download module is connect with the fpga chip, for being programmed to the storage unit in the fpga chip, with
And the application program stored in memory configuration chip is downloaded；
Network module is connect with the fpga chip, for providing for the FPGA development board for DDR3 memory bar
Network interface；
Clock module is connect with the fpga chip, for providing the driving clock of programming in logic to the fpga chip.
In the present invention, by using include DDR3 slot, fpga chip, memory configuration chip, power module,
The FPGA development board for DDR3 memory bar of download module, network module and clock module, so that DDR3 slot grafting
DDR3 memory bar, fpga chip control DDR3 memory bar and carry out high-speed data read-write, and memory configures chip and stores fpga chip
The application program for powering on bootstrap loading, power module is fpga chip, memory configuration chip and DDR3 memory bar provide electricity
Source, download module are programmed the storage unit in fpga chip, and to the application journey stored in memory configuration chip
Sequence is downloaded, and network module provides network interface, clock module, to FPGA core for the FPGA development board for DDR3 memory bar
Piece provides the driving clock of programming in logic, so that the FPGA development board for DDR3 memory bar of the onboard DDR3 slot,
Not only the needs of can having met high-speed data acquisition and having handled in real time, but also the difficulty of pcb board Networking Design is reduced, and also facilitate
Verifying and secondary development are carried out to design, reduce research and development and the time cost of user.
Detailed description of the invention
Fig. 1 is that the modular structure of the FPGA development board provided by an embodiment of the present invention for DDR3 memory bar is shown
It is intended to；
Fig. 2 is the modular structure schematic diagram of the power module in the FPGA development board shown in FIG. 1 for DDR3 memory bar；
Fig. 3 is provided by another embodiment of the utility model for the modular structure of the FPGA development board of DDR3 memory bar
Schematic diagram.
Specific embodiment
In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with attached drawing and implementation
Example, the present invention will be further described in detail.It should be appreciated that specific embodiment described herein is only used to explain
The utility model is not used to limit the utility model.
The realization of the utility model is described in detail below in conjunction with specific attached drawing:
Fig. 1 is shown provided by an embodiment of the present invention for the module knot of the FPGA development board of DDR3 memory bar
Structure, for ease of description, only the parts related to this embodiment are shown, and details are as follows:
As shown in Figure 1, the FPGA development board 10 provided by the utility model embodiment for DDR3 memory bar includes:
DDR3 slot 101, fpga chip 102, memory configure chip 103, power module 104, download module 105, network module
106 and clock module 107.
Wherein, DDR3 slot 101 is used for grafting DDR3 memory bar.
Fpga chip 102 is connect with DDR3 slot 101, carries out high-speed data read-write for controlling DDR3 memory bar.
Memory configures chip 103, connect with fpga chip 102, powers on bootstrap loading for store fpga chip 102
Application program.
Power module 104 connect with fpga chip 102, memory configuration chip 103 and DDR3 slot 101, is used for
Chip 103 is configured for fpga chip 102, memory and DDR3 memory bar provides power supply.
Download module 105 is connect with fpga chip 102, for being programmed to the storage unit in fpga chip 102,
And the application program stored in memory configuration chip 103 is downloaded.
Network module 106 is connect with fpga chip 102, for providing net for the FPGA development board for DDR3 memory bar
Network interface.
Clock module 107 is connect with fpga chip 102, when for providing the driving of programming in logic to fpga chip 102
Clock.
Wherein, DDR3 slot 101 is 240 pin standard dimm sockets.When it is implemented, at this for DDR3 memory bar
Setting is signal testing point, second slot grafting there are two DDR3 dimm socket, first slot on FPGA development board 10
DDR3 memory bar, DDR3 memory bar can be completed read-write under the control of FPGA chip 102, the cache of data realized with this.
Wherein, fpga chip 102 is high cloud semiconductor GW2A series of products, and concrete model GW2A-55K can control
DDR3 memory bar carries out high-speed data read-write.Specifically, the GW2A-55K chip is 55nm SRAM technique, core voltage
1.0V supports the static random of clock dynamic opening/closing, a variety of input and output (I/O) level standard and various modes to deposit
Reservoir, and there is high performance digital signal processing (Digital Signal Processing, DSP) module, abundant basic
Logic unit and flexible phaselocked loop (Phase Locked Loop, PLL)+dynamic link library (Dynamic Link
Library, DLL) resource.
Wherein, memory configuration 103 concrete model of chip is W25Q64DW.Due to no built-in in GW2A family chip
FLASH, it is therefore desirable to which external FLASH powers on bootstrap loading application program to store, and the main application as external FLASH, deposits
Reservoir configuration chips W 25Q64DW can realize the application program of storage fpga chip 102 well.
Wherein, as shown in Fig. 2, power module 104 includes power interface 104a, the first power supply chip 104b, second source
Chip 104c, third power supply chip 104d, the 4th power supply chip 104e and power management chip 104f.
Wherein, power interface 104a, for being connect with external power supply source, to provide supply voltage to power module 104.
First power supply chip 104b, even with power interface 104a and DDR3 slot (being not shown in the figure, please refer to Fig. 1)
It connects, for providing the first operating voltage according to DDR3 power management chip of the supply voltage into DDR3 memory bar.
Second source chip 104c, with fpga chip 102 (being not shown in the figure, please refer to Fig. 1), power interface 104a and
Memory configures chip 103 (being not shown in the figure, please refer to Fig. 1) connection, for according to supply voltage to fpga chip 102 and
Memory configures chip 103 and provides the second operating voltage.
Third power supply chip 104d, connect with second source chip 104c and fpga chip 102, for according to the second work
Make voltage and provides third operating voltage to fpga chip 102.
4th power supply chip 104e is connect with power interface 104a and fpga chip 102, for according to supply voltage to
Fpga chip 102 provides the 4th operating voltage.
Power management chip 104f is connect with power interface 104a and DDR3 slot, for according to supply voltage to
DDR3 memory bar provides the 5th operating voltage and the 6th operating voltage.
When it is implemented, power interface 104a is realized using DC power supply socket, main function is to for DDR3 memory
The FPGA development board 10 of item provides the power supply of 12V/2A.
Wherein, the first power supply chip 104b is realized using the power supply chip of model TPS82130, and main function is will
The supply voltage of 12V switchs to the first operating voltage of 5V, to provide 5V/3A voltage for DDR3 power management chip.
Wherein, second source chip 104c using model TPS82130 power supply chip realize, main function be by
The supply voltage of 12V switchs to the second operating voltage of 3.3V, to configure chip 103 and FPGA core for external FLASH, that is, memory
Piece 102 provides 3.3V/3A operating voltage.Power supply chip
Wherein, third power supply chip 104d using model TPS7A7001 power supply chip realize, main function be by
The second operating voltage of 3.3V switchs to the third operating voltage of 1.0V, to provide 1V/1.5A core voltage for fpga chip 102.
Wherein, the 4th power supply chip 104e using model TPS82130 power supply chip realize, main function be by
The supply voltage of 12V switchs to the 4th operating voltage of 1.5V, to provide the IO voltage of 1.5V/3A for fpga chip 102.
Wherein, the power management chip for the model TPS51116 that power management chip 104f is used is realized, is mainly made
With being that the supply voltage of 12V is switched to the 5th operating voltage of 1.5V and the 6th operating voltage of 0.75V, for DDR3 memory bar
Two kinds of operating voltages of 1.5V/10A and 0.75V/3A are provided.
Wherein, download module 105 is realized using existing JTAG download module.Since the transmission of JTAG download interface meets state
TCK, TMS of border standard JTAG protocol, TDI signal timing, and the TDO signal of JTAG protocol is detected and received simultaneously, therefore its
Support internal SRAM and two kinds of downloading modes of outside FLASH.
Wherein, network module 106 by 2 RJ45 connectors, 2 PHY chips, 2 25MHz crystal oscillators, status display LED and
Resistor-capacitor unit composition realizes the two-way Ethernet interface setting for the FPGA development board 10 of DDR3 memory bar.
When it is implemented, PHY chip is real using the B50610C1KML Ethernet chip of Broadcom company production
Existing, Ethernet chip B50610C1KML can support 10M, 100M, 1000M ethernet communication.It should be noted that
In the utility model embodiment, shown by 2 RJ45 connectors, 2 PHY chip B50610C1KML, 2 25MHz crystal oscillators, states
Show that the specific structure of the network module 107 of LED and resistor-capacitor unit composition can refer to the prior art, details are not described herein again.
In the present embodiment, network module 106 is set on the FPGA development board 10 for DDR3 memory bar, realizes needle
Network interface setting to the FPGA development board 10 of DDR3 memory bar, and user is made to download fpga chip exploitation by network
Bit stream file when test.
Wherein, clock module 107 uses frequency to have source crystal oscillator realization for 50MHz, and main function is for fpga chip
102 provide the driving clock of programming in logic.
In the present embodiment, the FPGA development board 10 provided by the utility model for DDR3 memory bar mainly passes through base
In domestic FPGA manufacturer high cloud GW2A-55K chip and design, and the DDR3 dimm socket of onboard standard so that being directed to
The needs of FPGA development board 10 of DDR3 memory bar had both met high-speed data acquisition and had handled in real time, at the same also facilitate to design into
Row verifying and secondary development, reduce research and development and the time cost of user.
Further, as one preferred embodiment of the utility model, as shown in figure 3, being directed to the FPGA of DDR3 memory bar
Development board 10 further includes memory module 108.
Wherein, memory module 108 is connect with fpga chip 102, for storing user data.
Wherein, in the utility model embodiment, memory module 108 realizes that the SD card module is by SD using SD card module
Deck and peripheral resistor-capacitor unit composition, can be communicated with fpga chip 102 by clock line, order wire and data line, realize SD card
Read-write, while there is plug-in card detection function.When it is implemented, SD card seat uses the SD-503182 model of MOLEX company production
Deck realizes that the model pushes away -8 contact miniature SD card seat of pushing-type.
Further, as one preferred embodiment of the utility model, as shown in figure 3, being directed to the FPGA of DDR3 memory bar
Development board 10 further includes RJ45 connector 109, and RJ45 connector 109 is connect with fpga chip 102, is used for and fpga chip 102
Carry out the Low Voltage Differential Signal network cable transmission of high speed signal.
Further, as one preferred embodiment of the utility model, as shown in figure 3, being directed to the FPGA of DDR3 memory bar
Development board 10 further includes expansible input/output interface 110, indicating lamp module 111 and key module 112, and expansible input
Output interface 110, indicating lamp module 111 and key module 112 are realized with fpga chip 102.
Wherein, the double contact pin that 40 pins can be used in expansible input/output interface 110 is realized, is mainly used for facilitating user
It is extended design；Indicating lamp module 111 is realized using four LED light, is mainly used for the test case to fpga chip 102
Or working condition is indicated；Key module 112 is realized using four keys, is carried out convenient for user to fpga chip 102
When test, test application scene is selected.
In the present invention, by using include DDR3 slot, fpga chip, memory configuration chip, power module,
The FPGA development board for DDR3 memory bar of download module, network module and clock module, so that DDR3 slot grafting
DDR3 memory bar, fpga chip control DDR3 memory bar and carry out high-speed data read-write, and memory configures chip and stores fpga chip
The application program for powering on bootstrap loading, power module is fpga chip, memory configuration chip and DDR3 memory bar provide electricity
Source, download module are programmed the storage unit in fpga chip, and to the application journey stored in memory configuration chip
Sequence is downloaded, and network module provides network interface, clock module, to FPGA core for the FPGA development board for DDR3 memory bar
Piece provides the driving clock of programming in logic, so that the FPGA development board for DDR3 memory bar of the onboard DDR3 slot,
Not only the needs of can having met high-speed data acquisition and having handled in real time, but also the difficulty of pcb board Networking Design is reduced, and also facilitate
Verifying and secondary development are carried out to design, reduce research and development and the time cost of user.
The above is only the preferred embodiment of the utility model only, is not intended to limit the utility model, all at this
Made any modifications, equivalent replacements, and improvements etc., should be included in the utility model within the spirit and principle of utility model
Protection scope within.
Claims (10)
1. a kind of FPGA development board for DDR3 memory bar, which is characterized in that the FPGA for DDR3 memory bar is developed
Plate includes:
DDR3 slot is used for grafting DDR3 memory bar；
Fpga chip is connect with the DDR3 slot, carries out high-speed data read-write for controlling the DDR3 memory bar；
Memory configures chip, connect with the fpga chip, for storing the application for powering on bootstrap loading of the fpga chip
Program；
Power module is connect, for being the FPGA with the fpga chip, memory configuration chip and the DDR3 slot
Chip, memory configuration chip and the DDR3 memory bar provide power supply；
Download module is connect with the fpga chip, for being programmed to the storage unit in the fpga chip and right
The application program stored in the memory configuration chip is downloaded；
Network module is connect with the fpga chip, for providing network for the FPGA development board for DDR3 memory bar
Interface；
Clock module is connect with the fpga chip, for providing the driving clock of programming in logic to the fpga chip.
2. the FPGA development board according to claim 1 for DDR3 memory bar, which is characterized in that described in DDR3
Deposit the FPGA development board of item further include:
Memory module is connect, for storing user data with the fpga chip.
3. the FPGA development board according to claim 1 for DDR3 memory bar, which is characterized in that the fpga chip
Model GW2A-55K.
4. the FPGA development board according to claim 1 for DDR3 memory bar, which is characterized in that the memory configuration
The model W25Q64DW of chip.
5. the FPGA development board according to claim 1 for DDR3 memory bar, which is characterized in that the DDR3 slot is
Dimm socket.
6. the FPGA development board according to claim 1 for DDR3 memory bar, which is characterized in that described in DDR3
The FPGA development board for depositing item further includes RJ45 connector, and the RJ45 connector is connect with the fpga chip, for it is described
The Low Voltage Differential Signal network cable transmission of fpga chip progress high speed signal.
7. the FPGA development board according to claim 1 for DDR3 memory bar, which is characterized in that the power module packet
It includes:
Power interface, for being connect with external power supply source, to provide supply voltage to the power module；
First power supply chip is connect with the power interface and the DDR3 slot, for according to the supply voltage to institute
The DDR3 power management chip stated in DDR3 memory bar provides the first operating voltage；
Second source chip connect with the fpga chip, the power interface and the memory configuration chip, is used for root
The second operating voltage is provided to the fpga chip and memory configuration chip according to the supply voltage；
Third power supply chip is connect with the second source chip and the fpga chip, for according to second work
Voltage provides third operating voltage to the fpga chip；
4th power supply chip is connect with the power interface and the fpga chip, for according to the supply voltage to institute
It states fpga chip and the 4th operating voltage is provided；
Power management chip is connect with the power interface and the DDR3 slot, for according to the supply voltage to institute
It states DDR3 memory bar and the 5th operating voltage and the 6th operating voltage is provided.
8. the FPGA development board according to claim 7 for DDR3 memory bar, which is characterized in that the first power supply core
The model of piece, the second source chip and the 4th power supply chip is TPS82130.
9. the FPGA development board according to claim 7 for DDR3 memory bar, which is characterized in that the third power supply core
The model TPS7A7001 of piece.
10. the FPGA development board according to claim 7 for DDR3 memory bar, which is characterized in that the power management
The model TPS51116 of chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201821397900.4U CN208861280U (en) | 2018-08-28 | 2018-08-28 | A kind of FPGA development board for DDR3 memory bar |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201821397900.4U CN208861280U (en) | 2018-08-28 | 2018-08-28 | A kind of FPGA development board for DDR3 memory bar |
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| CN208861280U true CN208861280U (en) | 2019-05-14 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110989815A (en) * | 2019-12-09 | 2020-04-10 | 思尔芯(上海)信息科技有限公司 | Power supply monitoring method and system based on development board |
-
2018
- 2018-08-28 CN CN201821397900.4U patent/CN208861280U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110989815A (en) * | 2019-12-09 | 2020-04-10 | 思尔芯(上海)信息科技有限公司 | Power supply monitoring method and system based on development board |
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