CN212364517U - Compatible development board - Google Patents
Compatible development board Download PDFInfo
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- CN212364517U CN212364517U CN202020081737.1U CN202020081737U CN212364517U CN 212364517 U CN212364517 U CN 212364517U CN 202020081737 U CN202020081737 U CN 202020081737U CN 212364517 U CN212364517 U CN 212364517U
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Abstract
The utility model discloses a compatible development board, compatible development board includes mainboard, daughter board one, daughter board two, the mainboard includes: a power supply module: the socket module is connected with the socket module and provides corresponding voltage for normal work of the socket module; a socket module: the socket module is connected with the socket module and is used for connecting the first daughter board and the second daughter board and testing signals; a downloading module: the socket module is connected with the socket module and can download the bit stream files in the daughter board I and the daughter board II; a reset module: and the power supply is connected with the socket module and is used for resetting the input level. The utility model discloses in, through the setting of mainboard, daughter board one, daughter board two, realize the separation with basic circuit module such as download module, power module of development board and FPGA chip one, two circuit module of FPGA chip, realize connecting again through socket module, both can test the aassessment to FPGA chip one, can test the aassessment to FPGA chip two again, improved the compatibility of development.
Description
Technical Field
The utility model relates to a development board technical field especially relates to a compatible development board.
Background
The development board (demo board) is a circuit board for developing embedded systems, and includes a series of hardware components such as a central processing unit, a memory, an input device, an output device, a data path/bus and an external resource interface, etc., the development board is generally customized by an embedded system developer according to development requirements and can be researched and designed by a user, the development board is hardware and software for a beginner to understand and learn a system, and simultaneously a part of the development board also provides a basic integrated development environment, software source codes and a hardware schematic diagram, etc., common development boards include 51, ARM, FPGA and development DSP boards, along with the development of the Chinese science and technology industry, a domestic FPGA is slowly developed, the situation of vigorous development is presented in recent two years, the domestic replacement of the FPGA chips of the previous imported brands (such as Altera, Xilinx and Lattice) becomes an inevitable trend of being unblocked, however, at present, the development board can only be welded and installed with a fixed type FPGA, and the development board can only test and evaluate the chip fixed on the development board and cannot test and evaluate two or more compatible chips.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a: the compatibility development board is provided in order to solve the problem of single compatibility of the development board.
In order to achieve the above purpose, the utility model adopts the following technical scheme:
a compatibility development board comprises a main board, a first daughter board and a second daughter board, wherein the main board comprises:
a power supply module: the socket module is connected with the socket module and provides corresponding voltage for normal work of the socket module;
a socket module: the first sub-board and the second sub-board are connected;
a downloading module: the socket module is connected with the socket module and can download the bit stream files in the daughter board I and the daughter board II;
a clock module: the socket module is connected with the power supply module and is used for providing a working clock for the power supply module;
a reset module: the power supply is connected with the socket module and is used for resetting the input level;
a switch module: the socket module is connected with the socket module and is used for controlling the opening and closing of the mainboard;
LED lamp module: the switch module is connected with the socket module and the switch module and is used for displaying the working state of the mainboard;
the first daughter board comprises a first FPGA chip, the second daughter board comprises a second FPGA chip, and the first daughter board and the second daughter board are connected with the main board through the socket module.
As a further description of the above technical solution:
the power module adopts an LDO power chip to realize the conversion from 5V to 3.3V or 3.3V to 2.5V or 3.3V to 1.0V, the power supply current can reach 2A, and the input voltage range is 1.5V-6.0V.
As a further description of the above technical solution:
the LED lamp module is provided with 6 green LED lamps and two red LED lamps, and the user can display the required state through the LED lamps.
As a further description of the above technical solution:
the switch module is provided with 6 slide switches and 6 key switches, the slide switches can be used for controlling input during user testing, and a user can manually control to input low level to the corresponding FPGA pins through the key switches.
As a further description of the above technical solution:
the socket module is provided with 4 DC3-40P sockets with 2.54mm spacing and 1 DC3-200P socket with 1.0mm spacing, the DC3-40P sockets can be used for testing signals, and the DC3-200P sockets are used for plugging a first daughter board and a second daughter board.
As a further description of the above technical solution:
the first FPGA chip adopts a high cloud GW1N-UV9UG169 chip, and the first daughter board is provided with 1 DC3-200P contact pins with a distance of 1.0 mm.
As a further description of the above technical solution:
the FPGA chip II adopts an Altera 10M08SCU169 chip, and the daughter board I is provided with 1 DC3-200P contact pin with the distance of 1.0 mm.
To sum up, owing to adopted above-mentioned technical scheme, the beneficial effects of the utility model are that:
1. the utility model discloses in, through the setting of mainboard, daughter board one, daughter board two, realize the separation with basic circuit module such as download module, power module of development board and FPGA chip one, two circuit module of FPGA chip, realize connecting again through socket module, both can test the aassessment to FPGA chip one, can test the aassessment to FPGA chip two again, improved the compatibility of development.
2. The utility model discloses in, through the setting of mainboard and daughter board one, daughter board two, unite two into one two development daughter boards, realize the function of two development daughter boards on a mainboard, effectively reduced development board cost of manufacture, and structural design scientific and reasonable has very big use and popularization meaning.
Drawings
Fig. 1 shows a schematic structural diagram of a compatibility development board provided according to an embodiment of the present invention;
fig. 2 shows a schematic structural diagram of a compatibility development board main board provided according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a compatibility development board according to an embodiment of the present invention;
fig. 4 shows a schematic structural diagram of a compatibility development board two provided according to an embodiment of the present invention;
illustration of the drawings:
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.
Referring to fig. 1-4, the present invention provides a technical solution: the utility model provides a compatible development board, compatible development board includes mainboard, daughter board one, daughter board two, and the mainboard includes:
a power supply module: the socket module is connected with the socket module and provides corresponding voltage for normal work of the socket module;
a socket module: the first sub-board and the second sub-board are connected;
a downloading module: the socket module is connected with the socket module and can download the bit stream files in the daughter board I and the daughter board II;
a clock module: the socket module is connected with the power supply module and is used for providing a working clock for the power supply module;
a reset module: the power supply is connected with the socket module and is used for resetting the input level;
a switch module: the socket module is connected with the socket module and is used for controlling the opening and closing of the mainboard;
LED lamp module: the switch module is connected with the socket module and the switch module and is used for displaying the working state of the mainboard;
the first daughter board comprises a first FPGA chip, the second daughter board comprises a second FPGA chip, and the first daughter board and the second daughter board are connected with the main board through the socket module.
Specifically, as shown in fig. 2, the power module adopts an LDO power chip to realize the conversion from 5V to 3.3V, or 3.3V to 2.5V, or 3.3V to 1.0V, the supply current can reach 2A, the input voltage range is 1.5V-6.0V, the DC5V input has overcurrent protection and reverse protection functions, and the overcurrent protection current is 1A.
Specifically, as shown in fig. 2, the LED lamp module is provided with 6 green LED lamps and two red LED lamps, and the user can display a desired state through the LED lamps, so that the user can directly obtain a mainboard test state between color indications of the LED lamps.
Specifically, as shown in fig. 2, the switch module is provided with 6 sliding switches and 6 key switches, the sliding switches can be used for control input during user testing, a user can manually control to input a low level to a corresponding FPGA pin through the key switches, and the low level is used as test control input.
Specifically, as shown in fig. 2, the socket module is provided with 4 DC3-40P sockets with a distance of 2.54mm and 1 DC3-200P socket with a distance of 1.0mm, the DC3-40P sockets can be used for testing signals, the DC3-200P sockets are used for plugging a first daughter board and a second daughter board, the DC3-200P sockets realize user function expansion and testing, and the DC3-200P sockets realize compatible connection between the first daughter board and the second daughter board and the main board.
Specifically, as shown in fig. 3, the first FPGA chip adopts a first high cloud GW1N-UV9UG169 chip, and the first daughter board is provided with 1 DC3-200P pin with a distance of 1.0mm, so as to connect the first high cloud GW1N-UV9UG169 chip with the DC3-200P socket.
Specifically, as shown in fig. 4, the second FPGA chip adopts an Altera 10M08SCU169 chip, and the first daughter board is provided with 1 DC3-200P pin with a distance of 1.0mm, so as to connect the Altera 10M08SCU169 chip with a DC3-200P socket.
The above, only be the concrete implementation of the preferred embodiment of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art is in the technical scope of the present invention, according to the technical solution of the present invention and the utility model, the concept of which is equivalent to replace or change, should be covered within the protection scope of the present invention.
Claims (7)
1. The utility model provides a compatibility development board, its characterized in that, compatibility development board includes mainboard, daughter board one, daughter board two, the mainboard includes:
a power supply module: the socket module is connected with the socket module and provides corresponding voltage for normal work of the socket module;
a socket module: the first sub-board and the second sub-board are connected;
a downloading module: the socket module is connected with the socket module and can download the bit stream files in the daughter board I and the daughter board II;
a clock module: the socket module is connected with the power supply module and is used for providing a working clock for the power supply module;
a reset module: the power supply is connected with the socket module and is used for resetting the input level;
a switch module: the socket module is connected with the socket module and is used for controlling the opening and closing of the mainboard;
LED lamp module: the switch module is connected with the socket module and the switch module and is used for displaying the working state of the mainboard;
the first daughter board comprises a first FPGA chip, the second daughter board comprises a second FPGA chip, and the first daughter board and the second daughter board are connected with the main board through the socket module.
2. The compatibility development board of claim 1, wherein the power module employs an LDO power chip to implement a conversion from 5V to 3.3V or 3.3V to 2.5V or 3.3V to 1.0V, a supply current is up to 2A, and an input voltage range is 1.5V-6.0V.
3. The compatibility development board according to claim 1, wherein the LED lamp module is provided with 6 green LED lamps and two red LED lamps, and a user can display a desired status through the LED lamps.
4. The compatibility development board according to claim 1, wherein the switch module is provided with 6 sliding switches and 6 key switches, the sliding switches can be used for user control input during testing, and a user can manually control to input a low level to a corresponding FPGA pin through the key switches.
5. The compatibility development board of claim 1, wherein the socket module is provided with 4 DC3-40P sockets with a pitch of 2.54mm and 1 DC3-200P sockets with a pitch of 1.0mm, the DC3-40P sockets can be used for testing signals, and the DC3-200P sockets can be used for connecting the first daughter board and the second daughter board.
6. The compatibility development board of claim 1, wherein said first FPGA chip is a high cloud GW1N-UV9UG169 chip, and said first daughter board is provided with 1.0mm pitch DC3-200P pins.
7. The compatibility development board of claim 1, wherein said FPGA chip two is an Altera 10M08SCU169 chip, and said daughter board one is provided with 1 DC3-200P pins with a 1.0mm pitch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020081737.1U CN212364517U (en) | 2020-01-15 | 2020-01-15 | Compatible development board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020081737.1U CN212364517U (en) | 2020-01-15 | 2020-01-15 | Compatible development board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212364517U true CN212364517U (en) | 2021-01-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020081737.1U Active CN212364517U (en) | 2020-01-15 | 2020-01-15 | Compatible development board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN212364517U (en) |
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2020
- 2020-01-15 CN CN202020081737.1U patent/CN212364517U/en active Active
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