CN218647100U - Interface test circuit and interface test system - Google Patents
Interface test circuit and interface test system Download PDFInfo
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- CN218647100U CN218647100U CN202222523843.2U CN202222523843U CN218647100U CN 218647100 U CN218647100 U CN 218647100U CN 202222523843 U CN202222523843 U CN 202222523843U CN 218647100 U CN218647100 U CN 218647100U
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Abstract
An interface test circuit and an interface test system are disclosed. The switching circuit is connected between the first interface and the second interface by setting a first interface adaptive to an interface of first equipment and a second interface adaptive to an interface of second equipment, and the control circuit controls the switching circuit to enable the first interface and the second interface to be switched on or off. Therefore, the connection state of the interface is controlled through the switch circuit, and the test difficulty and the test cost are reduced.
Description
Technical Field
The utility model relates to an electronic equipment technical field especially relates to an interface test circuit and interface test system.
Background
With the development of electronic technology, USB has become a common interface in production and development processes. The device is convenient for software downloading, various application tests and the like, provides a lot of convenience, and can be in butt joint with storage equipment such as a mobile hard disk or a USB flash disk as a data copying interface to realize data copying. When the USB device is connected to the USB port of the electronic device, the electronic device first needs to detect whether the USB device is connected to the USB port, and then can exchange data with the USB device.
In the prior art, a mechanical structure is usually used to plug and unplug a USB device, so as to perform a loading/unloading stability test on the USB device. However, the mechanical structure, such as a mechanical arm and a fixed rack, is bulky, and the structure control is complicated, and requires a professional industrial computer and professional software control, which results in high cost. Meanwhile, certain errors exist in mechanical plugging, so that the interface of the tested equipment or the USB equipment is easily damaged, and the subsequent maintenance cost is extremely high.
SUMMERY OF THE UTILITY MODEL
In view of this, the embodiment of the present invention provides an interface test circuit and an interface test system, which can reduce the test difficulty and the test cost.
In a first aspect, an embodiment of the present invention provides an interface test circuit, the interface test circuit includes:
the first interface is matched with the interface of the first equipment;
the second interface is matched with the interface of the second equipment;
a switch circuit connected between the first interface and the second interface; and
a control circuit configured to control the switching circuit to turn on or off the first and second interfaces.
In some embodiments, the first interface is configured to connect with a first device, the second interface is configured to connect with a second device;
the first device is a device to be tested, and the second device is a USB device.
In some embodiments, the interface of the first device and the second device is universal serial bus USB2.0, and the first interface and the second interface include a first data pin and a second data pin.
In some embodiments, the switching circuit comprises:
the two ends of the first switch are respectively connected with the first data pins of the first interface and the second interface; and
and two ends of the second switch are respectively connected with the second data pins of the first interface and the second interface.
In some embodiments, the interface of the first device and the second device is universal serial bus USB3.0;
the first interface or the second interface comprises a first data pin, a second data pin, a third data pin, a fourth data pin, a fifth data pin and a sixth data pin.
In some embodiments, the switching circuit comprises:
a first switch circuit connected between a first data pin and a second data pin of the first interface and the second interface; and
and the second switch circuit is connected between the third data pin, the fourth data pin, the fifth data pin and the sixth data pin of the first interface and the second interface.
In some embodiments, the first switching circuit comprises:
the two ends of the third switch are respectively connected with the first data pins of the first interface and the second interface; and
and two ends of the fourth switch are respectively connected with the second data pins of the first interface and the second interface.
In some embodiments, the second switching circuit comprises:
two ends of the fifth switch are respectively connected with the third data pins of the first interface and the second interface;
two ends of the sixth switch are respectively connected with the fourth data pins of the first interface and the second interface;
a seventh switch, two ends of which are respectively connected with the fifth data pins of the first interface and the second interface; and
and two ends of the eighth switch are respectively connected with the sixth data pins of the first interface and the second interface.
In some embodiments, the control circuit is configured to receive a control signal sent by an upper computer and generate an enable signal according to the control signal to control the switch circuit.
In a second aspect, an embodiment of the present invention provides an interface test system, the interface test system includes:
a first device;
a second device;
interface test circuitry as described in the first aspect; and
and the upper computer is connected with the control circuit of the interface test circuit and is configured to send a control signal to the control circuit.
The utility model discloses technical scheme through set up with the first interface of the interface looks adaptation of first equipment and with the second interface of the interface looks adaptation of second equipment, connect switch circuit between first interface and second interface, control circuit control switch circuit so that first interface and second interface switch on or turn-off. Therefore, the connection state of the interface is controlled through the switch circuit, and the test difficulty and the test cost are reduced.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 is a schematic diagram of a pin of a USB2.0 interface according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a pin of a USB3.0 interface according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an interface test system according to an embodiment of the present invention;
fig. 4 is a circuit diagram of an interface test system according to a first embodiment of the present invention;
fig. 5 is a circuit diagram of an interface test system according to a second embodiment of the present invention.
Detailed Description
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.
Meanwhile, it should be understood that, in the following description, a "circuit" refers to a conductive loop constituted by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that the two be absent intermediate elements.
Unless the context clearly requires otherwise, throughout the description, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".
In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
USB (Universal Serial Bus) is an external Bus standard, as a high-speed Serial Bus, its extremely high transmission speed can meet the application environment requirement of high-speed data transmission, and the Bus also has the advantages of simple power supply, convenient installation and configuration, simple and easy expansion port, diversified transmission modes, good compatibility, etc.
Common USB interface includes USB1.X/2.0 (standard model, small-size model and miniature model), USB3.0, USB Type-C etc. and wherein, USB1.X is similar with USB 2.0's interface pin, the embodiment of the utility model provides an use USB2.0 and USB 3.0's interface test to explain as the example, but the embodiment of the utility model provides an application scene does not do the restriction to interface test circuit and interface test system, and it can be other interfaces except USB, also can be other models of USB interface.
Fig. 1 is a schematic diagram of a pin of a USB2.0 interface according to an embodiment of the present invention. In the embodiment shown in FIG. 1, the USB2.0 interface includes four pins, V respectively BUS Data-, data +, GND. Wherein, V BUS For the power supply pin, data-and Data + are Data pins, and GND is the power ground pin.
Further, V BUS And GND is used for providing a 5V power supply, and the current can reach 500mA. While Data-and Data + are used for USB Data transfer. Data-and Data + are a set of differential signals, support half-duplex communication, and realize Data unidirectional transmission at any given time through Data-and Data + bidirectional transmission pipelines.
For convenience of explanation, data-will be referred to as a first Data pin and Data + will be referred to as a second Data pin hereinafter.
Fig. 2 is a schematic diagram of a pin of the USB3.0 interface according to an embodiment of the present invention. In the embodiment shown in FIG. 2, the USB2.0 interface includes nine pins, V respectively BUS Data +, GND1, SSRX-, SSRX +, GND2, SSTX-, and SSTX +. Wherein, V BUS The Data-and-Data + are power supply pins, the GND is a power supply grounding pin, the SSRX-and-SSRX + are high-speed receiving pins, the GND2 is a signal grounding pin, and the SSTX-and-SSTX + are high-speed sending pins.
Further, the USB3.0 interface can realize USB2.0 communication through Data-and Data +, is used for ultra-high speed communication through four pins of SSRX-, SSRX +, SSTX-and SSTX +, and realizes full-duplex communication.
For convenience of description, data-is referred to as a first Data pin, data + is referred to as a second Data pin, and SSTX-, SSTX +, SSRX-, SSRX + are a third Data pin, a fourth Data pin, a fifth Data pin, and a sixth Data pin, respectively.
Fig. 3 is a schematic structural diagram of an interface test system according to an embodiment of the present invention. In the embodiment shown in fig. 3, the interface test system is used for testing a USB interface, and specifically includes a first device 1, a second device 2, an interface test circuit 3, and an upper computer 4.
In this embodiment, the first device 1 and the second device 2 are devices having USB interfaces, where one of the first device 1 and the second device 2 is a device to be tested, and the other is a USB device. That is, the first device 1 is a device to be tested, and the second device 2 is a USB device, or the first device 1 is a USB device, and the second device 2 is a device to be tested.
The device to be tested is the device to be tested. For example, assuming that a USB interface of a vehicle machine in a vehicle needs to be tested, the vehicle machine is a device to be tested.
The USB device can have a data storage function through a USB flash disk, a vehicle data recorder and other devices with USB interfaces, so that the device to be tested can read information of the USB device.
And during testing, connecting the USB interface of the device to be tested with the USB interface of the USB device so that the device to be tested reads the USB device. And obtaining the test result of the device to be tested according to the read result of the device to be tested on the USB device.
The test items include the stability of loading or unloading of the USB device by the device to be tested, for example, whether the device to be tested can read the USB device within a predetermined time after the USB interface of the device to be tested and the USB interface of the USB device are connected, whether the device to be tested can detect disconnection of the USB device within a predetermined time after the USB interface of the device to be tested and the USB interface of the USB device are disconnected, and whether the device to be tested has abnormal phenomena such as stumbling, system crash and the like when the USB interface of the device to be tested and the USB interface of the USB device to be tested are frequently and alternately disconnected and connected.
It should be understood that the embodiment of the present invention is not limited to the test items, and other test items that need to disconnect or connect the USB interface of the device to be tested and the USB interface of the USB device are all applicable to the embodiment of the present invention. For example, the device under test tests the plugging response time of the USB device, and whether the function of the USB interface is normal.
It should also be understood that the embodiments of the present invention are not limited to the types of the device under test and the USB device, and they may be set according to specific test requirements. For example, when it is necessary to test whether the storage function of the USB storage device is normal, at this time, the USB storage device is a device to be tested, and the device for reading the USB storage device is a USB device.
In this embodiment, the interface test circuit 3 is connected between the first device 1 and the second device 2, and is used for connecting the first device 1 and the second device 2.
In this embodiment, the upper computer 4 is connected to the interface test circuit 3, and is configured to send a control signal to the interface test circuit 3, so that the interface test circuit 3 controls connection between the first device and the second device to be switched on or off according to the control signal.
Further, the upper computer 4 is an electronic device with a data processing function, a tester can configure a corresponding test logic on the upper computer 4, and the upper computer 4 generates a control signal according to the test logic and sends the control signal to the interface test circuit.
The upper computer 4 may be implemented by a notebook computer, a desktop computer, or the like.
The embodiment of the utility model provides a through setting up with the first interface of the interface looks adaptation of first equipment and with the second interface of the interface looks adaptation of second equipment, with switch circuit connection between first interface and second interface, control circuit control switch circuit so that first interface and second interface switch on or turn-off. Therefore, the connection state of the interface is controlled through the switch circuit, and the test difficulty and the test cost are reduced.
Fig. 4 is a circuit diagram of an interface test system according to a first embodiment of the present invention. In the embodiment shown in fig. 4, the interface test system is used for testing a USB2.0 interface, and specifically includes a first device 1, a second device 2, an interface test circuit 3, and an upper computer 4. The interface test circuit 3 is connected between the first device 1 and the second device 2, and the upper computer 4 is connected to the interface test circuit 3 and configured to send a control signal to the interface test circuit 3, so that the interface test circuit 3 controls connection between the first device 1 and the second device 2 to be turned on or off according to the control signal.
In the present embodiment, the interface test circuit 3 includes a first interface 31, a second interface 32, a switch circuit 33, and a control circuit 34.
The first interface 31 and the second interface 32 are adapted to the interface of the device to be tested. In this embodiment, the interface of the device to be tested is a USB2.0 interface.
For convenience of explanation, in fig. 4, the first interface 31 and the second interface 32 show only USB Data transmission pins Data-and Data +.
In this embodiment, the first device 1 has a USB2.0 interface, and the Data transfer pins Data-and Data + of the USB2.0 interface are connected to the USB Data transfer pins Data-and Data + of the first interface 31, respectively. Second device 2 has a USB2.0 interface, and the Data transfer pins Data-and Data + of the USB2.0 interface are connected with the USB Data transfer pins Data-and Data + of second interface 32, respectively.
It should be understood that, the embodiment of the present invention does not limit the types and connection modes of the interfaces of the first device 1, the second device 2, the first interface 31 and the second interface 32, and the first interface 31 and the first device 1 can be directly connected to each other, and can also be connected to each other through other USB cables, and similarly, the second interface 32 and the second device 2 can be directly connected to each other, and can also be connected to each other through other USB cables. Taking the direct connection as an example, one of the interface of the first device 1 and the first interface 31 is a USB2.0 socket, the other is a USB2.0 plug, and one of the interface of the second device 2 and the second interface 32 is a USB2.0 socket, the other is a USB2.0 plug. For example, taking the first device 1 as a device to be tested and the second device 2 as a USB device as an example for explanation, the interface of the first device 1 is a USB2.0 socket, and correspondingly, the first interface 31 is a USB2.0 plug; the interface of the second device 2 is a USB2.0 plug, and correspondingly, the second interface 32 is a USB2.0 socket.
It should also be understood that, because the USB3.0 is compatible with the USB2.0 interface, therefore, the technical solution of the embodiment of the present invention can also be implemented when the first interface and/or the second interface in the embodiment of the present invention are replaced by the USB3.0 interface.
In the present embodiment, the switch circuit 33 is connected between the first interface 31 and the second interface 32. The switch circuit 33 includes a first switch K1 and a second switch K2. One end of the first switch K1 is connected to a first Data pin of the first interface, and the other end is connected to a first Data pin of the second interface, where the first Data pin is a negative Data-of Data transmission pin. Correspondingly, one end of the second switch K2 is connected to the second Data pin of the first interface, and the other end is connected to the second Data pin of the second interface, where the second Data pin is a positive Data + of the Data transmission pin. Thus, when both the first switch K1 and the second switch K2 are turned on, the first interface 31 and the second interface 32 are turned on, that is, the first device 1 and the second device 2 are turned on. When the first switch K1 and the second switch K2 are turned off, the first interface 31 and the second interface 32 are turned off, that is, the first device 1 and the second device 2 are turned off. Thereby, the control of the on or off of the first device 1 and the second device 2 can be achieved by controlling the switching circuit.
In some embodiments, the switch circuit is an integrated switch chip, such as a chip of a CH442E model of WCH (south kyoton constant), where the CH442E is an analog switch chip rated for a 5V power supply voltage, can support a 3.3V or lower power supply voltage, is a DPDT (double pole double throw) low-resistance broadband bidirectional analog switch chip, includes 2-channel DPDT single pole double throw analog, has a high bandwidth and a low on-resistance, and can be used for USB signal transmission. It should be understood that the embodiment of the present invention does not limit the implementation manner of the switch circuit, and other circuits or chips that can be used for USB transmission are also applicable to the embodiment of the present invention.
In the present embodiment, the control circuit 34 is configured to control the switch circuit 33 so that the first interface 31 and the second interface 32 are turned on or off.
Further, the control circuit 34 is configured to receive a control signal sent by the upper computer 4, and generate an enable signal according to the control signal to control the switch circuit 33.
Further, the enable signal is active at a high level and inactive at a low level.
In some embodiments, the control circuit may be implemented by a programmable relay. Specifically, the programmable relay stores some typical relay logic control programs in an internal memory in advance, combines and calls the typical relay logic control programs through a user program, the user program adopts ladder diagram or functional diagram language programming through a panel, is visual, simple and easy to understand, inputs switching value signals through buttons, switches and the like, and can carry out arithmetic operation, logic operation, analog quantity operation, timing, adding/subtracting counting, frequency measurement and the like on the input signals through a sequence execution program. In addition, the hardware is standardized, and only the program needs to be changed to change the control function.
It should be understood that the embodiment of the present invention is not limited to the implementation manner of the control circuit, and may also be implemented in other manners, for example, a relay is combined with a PLC (Programmable Logic Controller).
In the present embodiment, the upper computer 4 is configured to send a control signal to the control circuit.
The programmable relay SmartRelay is a relay module controlled by a single chip microcomputer, and a user can design the relay for special purposes through a graphical programming interface under a Windows (operating system). The user does not have to stock many varieties of relay modules and SmartRelay can replace almost all relay modules. The SmartRelay is provided with several common relay module designs such as a trigger relay, a latch relay, a clutch relay, a delay relay and the like in the attached programming software, and the SmartRelay becomes a relay module required by a user when the SmartRelay is downloaded into the SmartRelay. The SmartRelay is not limited in programming times, the user can program the SmartRelay into any mode required, and the programming configuration of the SmartRelay can be recorded in the hard disk of the computer for the next programming. SmartRelay has three input ends and three output ends which are not influenced mutually. The inputs may be configured to either rising edge trigger or falling edge trigger. The three outputs are two open collector outputs and a relay output (common, normally open, normally closed), respectively. The power supply of SmartRelay is 8-12 VDC. SmartRelay's user programming software can run in Windows98SE, windows2000, windows ME, windows XP and other operating systems.
Further, assuming that the switch circuit 33 is a switch chip including an enable pin, when the enable signal input to the enable pin is active, the first switch K1 and the second switch K2 are turned on, and when the enable signal input to the enable pin is inactive, the first switch K1 and the second switch K2 are turned off. First, the switch circuit and the programmable relay are connected, so that the output of the programmable relay is connected to the enable pin of the switch circuit, that is, the output signal of the programmable relay is used as the enable signal of the switch circuit. Secondly, install SmartRelay programming software on host computer 4 to be connected programmable relay and host computer through the signal line, when host computer 4 detected SmartRelay, programming software will establish with SmartRelay and be connected, can dispose programmable relay SmartRelay through programming software, wherein, the configuration information of user through programming software input is write as the control signal of the embodiment of the utility model. And after receiving the configuration information, the programmable relay SmartRelay executes corresponding configuration to output an enabling signal. For example, the control signal includes a trigger mode (rising edge trigger or falling edge trigger) of the relay, a start mode of each output terminal, a stop mode of each output terminal, a timer, and the like.
Therefore, the first equipment and the second equipment can be controlled to be connected or disconnected according to preset logic only by inputting corresponding configuration through a configuration interface of the upper computer, so that corresponding testing is realized.
The embodiment of the utility model provides a through the setting with the first interface of the interface looks adaptation of first equipment and with the second interface of the interface looks adaptation of second equipment, with switch circuit connection between first interface and second interface, control circuit control switch circuit so that first interface and second interface switch on or turn-off. Therefore, the connection state of the interface is controlled through the switch circuit, and the test difficulty and the test cost are reduced.
Fig. 5 is a circuit diagram of an interface test system according to a second embodiment of the present invention. In the embodiment shown in fig. 5, the interface test system is used for testing a USB2.0 or USB3.0 interface, and specifically includes a first device 1, a second device 2, an interface test circuit 3, and an upper computer 4. The interface test circuit 3 is connected between the first device 1 and the second device 2, and the upper computer 4 is connected to the interface test circuit 3 and configured to send a control signal to the interface test circuit 3, so that the interface test circuit 3 controls connection between the first device 1 and the second device 2 to be turned on or off according to the control signal.
In the present embodiment, the interface test circuit 3 includes a first interface 31, a second interface 32, a first switch circuit 33a, a second switch circuit 33b, and a control circuit 34.
The first interface 31 and the second interface 32 are adapted to an interface of a device to be tested, in this embodiment, the interface of the device to be tested is a USB3.0 interface.
For convenience of illustration, in fig. 5, the first interface 31 and the second interface 32 only show USB3.0 Data transmission pins, which are Data-, data +, SSRX-, SSRX +, SSTX-, and SSTX +, respectively. Wherein, data-, data + are used for USB2.0 Data transmission, SSRX-and SSRX + are high-speed receiving pins, and SSTX-and SSTX + are high-speed sending pins.
In this embodiment, the first device 1 has a USB3.0 interface, and each pin is connected to Data-, data +, SSRX-, SSRX +, SSTX-, and SSTX + of the first interface, respectively. Similarly, the second device 2 has a USB3.0 interface, and each pin is connected with Data-, data +, SSRX-, SSRX +, SSTX-and SSTX + of the second interface respectively. Wherein, the interface types and the connection modes of the first device 1, the second device 2, the first interface 31, and the second interface 32 are similar to those of fig. 4, and the embodiment of the present invention is not described herein again.
In the present embodiment, the first switch circuit 33a is connected between the first interface 31 and the second interface 32. The first switch circuit 33 includes a third switch K3 and a fourth switch K4. One end of the third switch K3 is connected to the first Data pin of the first interface 31, and the other end is connected to the first Data pin of the second interface 32, where the first Data pin is a negative Data-of Data transmission pin. Correspondingly, one end of the fourth switch K4 is connected to the second Data pin of the first interface 31, and the other end is connected to the second Data pin of the second interface 32, where the second Data pin is a positive Data + Data of the Data transmission pin. Thus, when the third switch K3 and the fourth switch K4 are both turned on, the first interface 31 and the second interface 32 are turned on, that is, the Data-and Data + pins of the first device 1 and the second device 2 are turned on. When the third and fourth switches K3 and K4 are turned off, the Data-and Data + pins of the first and second interfaces 31 and 32 are turned off.
In this embodiment, the second switch circuit 33b is connected between the third data pin, the fourth data pin, the fifth data pin and the sixth data pin of the first interface 31 and the second interface 32. The second switch circuit comprises a fifth switch K5, a sixth switch K6, a seventh switch K7 and an eighth switch K8. Two ends of the fifth switch K5 are respectively connected to the third data pins of the first interface 31 and the second interface 32, and the third data pin is a high-speed sending pin negative electrode SSTX-. Two ends of a sixth switch K6 are respectively connected to fourth data pins of the first interface 31 and the second interface 32, where the fourth data pin is a high-speed transmission pin positive electrode SSTX +. Two ends of the seventh switch K7 are respectively connected to the fifth data pin K5 of the first interface 31 and the second interface 32, and the fifth data pin K5 is a high-speed receiving pin negative pole SSRX-. Two ends of the eighth switch K8 are respectively connected to the sixth data pins of the first interface 31 and the second interface 32, and the sixth data pin K6 is a high-speed receiving pin positive electrode SSRX +. The fifth switch K5, the sixth switch K6, the seventh switch K7 and the eighth switch K8 are turned on or off synchronously, so that when the fifth switch K5, the sixth switch K6, the seventh switch K7 and the eighth switch K8 are turned on, the pins SSRX-, SSRX +, SSTX-and SSTX + of the first interface 31 and the second interface 32 are turned on. When the fifth, sixth, seventh and eighth switches K5, K6, K7 and K8 are turned off, the high speed pins SSRX-, SSRX +, SSTX-and SSTX + of the first and second interfaces 31 and 32 are turned off.
Further, each of the switches in the first switch circuit 33a and the second switch circuit 33b is configured to be turned on or off synchronously, whereby the USB3.0 interface between the first interface and the second interface is turned on when each of the switches in the first switch circuit 33a and the second switch circuit 33b is turned on. When each of the switches in the first switch circuit 33a and the second switch circuit 33b is turned off, the USB3.0 interface between the first interface and the second interface is turned off.
In some embodiments, the first and second switching circuits are integrated switching chips.
It should be noted that, the embodiment of the present invention is described by taking two switch circuits to respectively control the USB2.0 Data transmission pin (Data-and Data +) and the high speed transmission pin (SSRX-, SSRX +, SSTX-and SSTX +), but the embodiment of the present invention does not limit the number of the switch circuits, for example, the USB2.0 Data transmission pin (Data-and Data +) and the high speed transmission pin (sstrx-, SSRX +, x-and SSTX +) may also be controlled by one switch circuit, or implemented by three or more switch circuits.
In the present embodiment, the control circuit 34 is configured to control the switches in the first switch circuit 33a and the second switch circuit 33b to be turned on or off, so that the first interface 31 and the second interface 32 are turned on or off.
Further, the control circuit 34 is configured to receive a control signal sent by the upper computer 4, and generate an enable signal according to the control signal to control the switch circuit 33.
Further, the enable signal is active at a high level and inactive at a low level.
The implementation manner of the control circuit may be similar to that of fig. 4, and the embodiment of the present invention is not described herein again.
The embodiment of the utility model provides a through setting up with the first interface of the interface looks adaptation of first equipment and with the second interface of the interface looks adaptation of second equipment, with switch circuit connection between first interface and second interface, control circuit control switch circuit so that first interface and second interface switch on or turn-off. Therefore, the connection state of the interface is controlled through the switch circuit, and the test difficulty and the test cost are reduced.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. An interface test circuit, the interface test circuit comprising:
the first interface is matched with the interface of the first equipment;
the second interface is matched with the interface of the second equipment;
a switch circuit connected between the first interface and the second interface; and
a control circuit configured to control the switching circuit to turn on or off the first and second interfaces.
2. The interface test circuit of claim 1, wherein the first interface is configured to connect with a first device and the second interface is configured to connect with a second device;
the first device is a device to be tested, and the second device is a USB device.
3. The interface test circuit of claim 1, wherein the interface of the first device and the second device is a Universal Serial Bus (USB) 2.0, the first interface and the second interface comprising a first data pin and a second data pin.
4. The interface test circuit of claim 3, wherein the switching circuit comprises:
two ends of the first switch are respectively connected with the first data pins of the first interface and the second interface; and
and two ends of the second switch are respectively connected with the second data pins of the first interface and the second interface.
5. The interface test circuit of claim 1, wherein the interface of the first device and the second device is a Universal Serial Bus (USB) 3.0;
the first interface or the second interface comprises a first data pin, a second data pin, a third data pin, a fourth data pin, a fifth data pin and a sixth data pin.
6. The interface test circuit of claim 5, wherein the switching circuit comprises:
a first switching circuit connected between first and second data pins of the first and second interfaces; and
and the second switch circuit is connected between the third data pin, the fourth data pin, the fifth data pin and the sixth data pin of the first interface and the second interface.
7. The interface test circuit of claim 6, wherein the first switching circuit comprises:
the two ends of the third switch are respectively connected with the first data pins of the first interface and the second interface; and
and two ends of the fourth switch are respectively connected with the second data pins of the first interface and the second interface.
8. The interface test circuit of claim 6, wherein the second switching circuit comprises:
two ends of the fifth switch are respectively connected with the third data pins of the first interface and the second interface;
two ends of the sixth switch are respectively connected with the fourth data pins of the first interface and the second interface;
two ends of the seventh switch are respectively connected with the fifth data pins of the first interface and the second interface; and
and two ends of the eighth switch are respectively connected with the sixth data pins of the first interface and the second interface.
9. The interface test circuit of claim 1, wherein the control circuit is configured to receive a control signal sent by a host computer and generate an enable signal to control the switch circuit according to the control signal.
10. An interface test system, the interface test system comprising:
a first device;
a second device;
the interface test circuit of any of claims 1-9; and
and the upper computer is connected with the control circuit of the interface test circuit and is configured to send a control signal to the control circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202222523843.2U CN218647100U (en) | 2022-09-22 | 2022-09-22 | Interface test circuit and interface test system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202222523843.2U CN218647100U (en) | 2022-09-22 | 2022-09-22 | Interface test circuit and interface test system |
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| CN218647100U true CN218647100U (en) | 2023-03-17 |
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