CN202887556U - FPGA experiment development board - Google Patents
FPGA experiment development board Download PDFInfo
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- CN202887556U CN202887556U CN 201220504928 CN201220504928U CN202887556U CN 202887556 U CN202887556 U CN 202887556U CN 201220504928 CN201220504928 CN 201220504928 CN 201220504928 U CN201220504928 U CN 201220504928U CN 202887556 U CN202887556 U CN 202887556U
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- fpga
- microprocessor
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- development board
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Abstract
The utility model discloses an FPGA experiment development board, comprising an FPGA minimum system, a bus interface, an input device, an output device, and a power supply circuit used for supplying various power consuming devices with power. The FPGA minimum system comprises a microprocessor and a crystal oscillation circuit, a reset circuit, a JTAG interface circuit, an ASP interface circuit and a test circuit, which are connected with the microprocessor. The bus interface comprises a PS/2 interface and an RS-232 bus interface, which are connected with the microprocessor. The input device comprises a 4x4 matrix keyboard and an independent button, which are connected with input terminals of the microprocessor. The output device comprises a nixie tube and a VGA display, which are connected with output terminals of the microprocessor. The FPGA experiment development board is simple in structure, reasonable in design, convenient in wiring, and flexible and convenient in utilization; the FPGA experiment development board is beneficial for students to quickly master FPGA microprocessor technologies which are developing rapidly at present; and the FPGA experiment development board is low in cost, good in utilization effect, and convenient for popularization and utilization.
Description
Technical field
The utility model belongs to the experimental facilities technical field, especially relates to a kind of FPGA experimental development board of multi.
Background technology
Along with the fast development of computer technology and semiconductor technology, the embedded microcontrollers such as single-chip microcomputer have been obtained widely in every field and have been used.The FPGA microprocessor has been widely used in the fields such as wireless product, PDA, GPS, consumer electronics, automotive electronics, Industry Control, medical product, smart card.Traditional FPGA experimental box with all module collections on a circuit board, only needing to carry out simple operations according to laboratory manual when the student tests gets final product, and, the program that oneself can only be finished is loaded on the microprocessor in the FPGA experimental box and tests, the student only can make amendment to program, but can not well understand the annexation of hardware circuit, can not understand well the contact between the software and hardware, so be unfavorable for grasping this gate technique, also be unfavorable for the cultivation of students ' actual situation manipulative ability.
The utility model content
Technical problem to be solved in the utility model is for above-mentioned deficiency of the prior art, a kind of FPGA experimental development board of multi is provided, it is simple in structure, reasonable in design, easy-to-connect, flexible and convenient to use, be conducive to the FPGA microprocessor technology that the student grasps rapidly current develop rapidly, realize that cost is low and result of use good, be convenient to promote the use of.
For solving the problems of the technologies described above, the technical solution adopted in the utility model is: a kind of FPGA experimental development board of multi, it is characterized in that: comprise the FPGA minimum system, bus interface, input equipment, output device and be the power circuit of each power unit power supply, described FPGA minimum system comprises microprocessor and the crystal oscillating circuit that joins with microprocessor, reset circuit, the jtag interface circuit, ASP interface circuit and test circuit, described bus interface comprises PS/2 interface and the RS-232 bus interface of joining with microprocessor, described input equipment comprises 4 * 4 matrix keyboards and the independent button that the input end with microprocessor joins, and described output device comprises charactron and the VGA display that the output terminal with microprocessor joins.
Above-mentioned a kind of FPGA experimental development board of multi is characterized in that: described microprocessor is the FPGA device of Cyclone series.
Above-mentioned a kind of FPGA experimental development board of multi is characterized in that: described microprocessor is chip EP1C3T144C8N.
Above-mentioned a kind of FPGA experimental development board of multi is characterized in that: described test circuit is the LED lamp.
Above-mentioned a kind of FPGA experimental development board of multi is characterized in that: be connected with USB interface on the described power circuit.
Above-mentioned a kind of FPGA experimental development board of multi is characterized in that: described independent button is comprised of two buttons.
Above-mentioned a kind of FPGA experimental development board of multi is characterized in that: described charactron and VGA display all join by the output terminal of IDC10 connecting line and microprocessor.
The utility model compared with prior art has the following advantages:
1, the utility model circuit structure is simple, and is reasonable in design, easy-to-connect.
2, the utility model both can be processed into finished product and directly offer student's use, also can be made into the development board external member and offer the Students ' Learning use, the development board external member is made of the components and parts that need on circuit diagram of the present utility model, the pcb board that produces and the pcb board to weld, and is flexible and convenient to use.
3, use the utility model to test, the circuit that the student can either grasp the FPGA experimental development board of multi connects, can grasp again the FPGA programming, can be good at understanding the annexation of hardware circuit and the contact between the software and hardware, be conducive to the student and grasp rapidly this gate technique, also be beneficial to the cultivation of students ' actual situation manipulative ability.
4, of the present utility model practical, realize that than traditional experimental box cost is low and result of use good, be convenient to promote the use of.
In sum, the utility model is simple in structure, and is reasonable in design, and easy-to-connect is flexible and convenient to use, is conducive to the FPGA microprocessor technology that the student grasps rapidly current develop rapidly, realizes that cost is low and result of use good, is convenient to promote the use of.
Below by drawings and Examples, the technical solution of the utility model is described in further detail.
Description of drawings
Fig. 1 is schematic block circuit diagram of the present utility model.
Description of reference numerals:
1-FPGA minimum system; 1-1-microprocessor; 1-2-crystal oscillating circuit;
1-3-reset circuit; 1-4-jtag interface circuit; 1-5-ASP interface circuit;
1-6-test circuit; 2-bus interface; 2-1-PS/2 interface;
2-2-RS-232 bus interface; 3-input equipment; 3-1-4 * 4 matrix keyboard;
3-2-independent button; 4-output device; 4-1-charactron;
4-2-VGA display; 5-power circuit; 6-USB interface.
Embodiment
As shown in Figure 1, the utility model comprises FPGA minimum system 1, bus interface 2, input equipment 3, output device 4 and be the power circuit 5 of each power unit power supply, described FPGA minimum system 1 comprises microprocessor 1-1 and the crystal oscillating circuit 1-2 that joins with microprocessor 1-1, reset circuit 1-3, jtag interface circuit 1-4, ASP interface circuit 1-5 and test circuit 1-6, described bus interface 2 comprises PS/2 interface 2-1 and the RS-232 bus interface 2-2 that joins with microprocessor 1-1, described input equipment 3 comprises 4 * 4 matrix keyboard 3-1 and the independent button 3-2 that the input end with microprocessor 1-1 joins, and described output device 4 comprises charactron 4-1 and the VGA display 4-2 that the output terminal with microprocessor 1-1 joins.
In the present embodiment, the FPGA device that described microprocessor 1-1 is Cyclone series.Particularly, described microprocessor 1-1 is chip EP1C3T144C8N.Whether described test circuit 1-6 is the LED lamp, be used for test FPGA minimum system 1 and can work.Be connected with USB interface 6 on the described power circuit 5, like this so that the utility model both can adopt the 5V DC power supply, the USB interface that also can adopt the USB cable to connect computer is powered, and is flexible and convenient to use.Described independent button 3-2 is comprised of two buttons.Described charactron 4-1 and VGA display 4-2 all join by the output terminal of IDC10 connecting line and microprocessor 1-1.
During implementation, described power circuit 5 is by being used for becoming the 3.3V reduction voltage circuit of 3.3V voltage to become the 1.5V reduction voltage circuit of 1.5V voltage to consist of the 3.3V voltage transitions with being used for the 5V voltage transitions, particularly, 3.3V reduction voltage circuit can adopt chip ASM1117-3.3 to realize, the 1.5V reduction voltage circuit can adopt chip ASM1117-1.5 to realize.In the utility model, chip EP1C3T144C8N is powered jointly by 1.5V reduction voltage circuit and 3.3V reduction voltage circuit, and all the other power units are powered by the 3.3V reduction voltage circuit.
When the utility model used, the experiment teacher can provide the development board external member to the student, and external member comprises needs the components and parts that weld on circuit diagram of the present utility model, the pcb board that produces and the pcb board, namely consisted of the components and parts of each functional unit in the utility model.After the student takes the development board external member, can first learning circuit figure, then according to the annexation in the circuit diagram components and parts are welded on the pcb board, so just finished making of the present utility model.After completing, the student can test core of the present utility model by test circuit 1-6, be whether FPGA minimum system 1 can work, when FPGA minimum system 1 can work, the student just can be according to concrete course content, the program that oneself is finished is loaded on the microprocessor 1-1 and tests, the use of study 4 * 4 matrix keyboard 3-1 and independent button 3-2, the use of study charactron 4-1 and VGA display 4-2, and the use of study PS/2 interface 2-1 and RS-232 bus interface 2-2.
Use the utility model to test, the circuit that the student can either grasp the FPGA experimental development board of multi connects, can grasp again the FPGA programming, be conducive to the FPGA microprocessor technology that the student grasps rapidly current develop rapidly, the student can be got inside the character that one is playing rapidly in the work in future.
The above; it only is preferred embodiment of the present utility model; be not that the utility model is imposed any restrictions; every any simple modification, change and equivalent structure of above embodiment being done according to the utility model technical spirit changes, and all still belongs in the protection domain of technical solutions of the utility model.
Claims (7)
1. FPGA experimental development board of multi, it is characterized in that: comprise FPGA minimum system (1), bus interface (2), input equipment (3), output device (4) and be the power circuit (5) of each power unit power supply, described FPGA minimum system (1) comprises microprocessor (1-1) and the crystal oscillating circuit (1-2) that joins with microprocessor (1-1), reset circuit (1-3), jtag interface circuit (1-4), ASP interface circuit (1-5) and test circuit (1-6), described bus interface (2) comprises PS/2 interface (2-1) and the RS-232 bus interface (2-2) of joining with microprocessor (1-1), described input equipment (3) comprises 4 * 4 matrix keyboards (3-1) and the independent button (3-2) that the input end with microprocessor (1-1) joins, and described output device (4) comprises charactron (4-1) and the VGA display (4-2) that the output terminal with microprocessor (1-1) joins.
2. according to a kind of FPGA experimental development board of multi claimed in claim 1, it is characterized in that: described microprocessor (1-1) is the FPGA device of Cyclone series.
3. according to a kind of FPGA experimental development board of multi claimed in claim 2, it is characterized in that: described microprocessor (1-1) is chip EP1C3T144C8N.
4. according to a kind of FPGA experimental development board of multi claimed in claim 1, it is characterized in that: described test circuit (1-6) is the LED lamp.
5. according to a kind of FPGA experimental development board of multi claimed in claim 1, it is characterized in that: be connected with USB interface (6) on the described power circuit (5).
6. according to a kind of FPGA experimental development board of multi claimed in claim 1, it is characterized in that: described independent button (3-2) is comprised of two buttons.
7. according to a kind of FPGA experimental development board of multi claimed in claim 1, it is characterized in that: described charactron (4-1) and VGA display (4-2) all join by the output terminal of IDC10 connecting line and microprocessor (1-1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220504928 CN202887556U (en) | 2012-09-27 | 2012-09-27 | FPGA experiment development board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220504928 CN202887556U (en) | 2012-09-27 | 2012-09-27 | FPGA experiment development board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202887556U true CN202887556U (en) | 2013-04-17 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220504928 Expired - Fee Related CN202887556U (en) | 2012-09-27 | 2012-09-27 | FPGA experiment development board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202887556U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103217618A (en) * | 2013-04-16 | 2013-07-24 | 青岛中星微电子有限公司 | Device and method for testing field programmable gate array (FPGA) development board |
| CN104346978A (en) * | 2013-07-23 | 2015-02-11 | 华中科技大学 | FPGA-based microcomputer interface hardware experiment platform |
-
2012
- 2012-09-27 CN CN 201220504928 patent/CN202887556U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103217618A (en) * | 2013-04-16 | 2013-07-24 | 青岛中星微电子有限公司 | Device and method for testing field programmable gate array (FPGA) development board |
| CN103217618B (en) * | 2013-04-16 | 2015-09-09 | 青岛中星微电子有限公司 | A kind of apparatus and method of testing FPGA development board |
| CN104346978A (en) * | 2013-07-23 | 2015-02-11 | 华中科技大学 | FPGA-based microcomputer interface hardware experiment platform |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130417 Termination date: 20130927 |