CN104346978A - FPGA-based microcomputer interface hardware experiment platform - Google Patents
FPGA-based microcomputer interface hardware experiment platform Download PDFInfo
- Publication number
- CN104346978A CN104346978A CN201310311009.XA CN201310311009A CN104346978A CN 104346978 A CN104346978 A CN 104346978A CN 201310311009 A CN201310311009 A CN 201310311009A CN 104346978 A CN104346978 A CN 104346978A
- Authority
- CN
- China
- Prior art keywords
- fpga
- core
- chip
- circuit
- 8086cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09B—EDUCATIONAL OR DEMONSTRATION APPLIANCES; APPLIANCES FOR TEACHING, OR COMMUNICATING WITH, THE BLIND, DEAF OR MUTE; MODELS; PLANETARIA; GLOBES; MAPS; DIAGRAMS
- G09B23/00—Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes
- G09B23/06—Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes for physics
- G09B23/18—Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes for physics for electricity or magnetism
- G09B23/183—Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes for physics for electricity or magnetism for circuits
- G09B23/186—Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes for physics for electricity or magnetism for circuits for digital electronics; for computers, e.g. microprocessors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Optimization (AREA)
- Algebra (AREA)
- Computational Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Analysis (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Pure & Applied Mathematics (AREA)
- Business, Economics & Management (AREA)
- Educational Administration (AREA)
- Educational Technology (AREA)
- Theoretical Computer Science (AREA)
- Electronic Switches (AREA)
Abstract
The invention discloses an FPGA-based microcomputer interface hardware experiment platform. The experiment platform includes a core circuit, an interface circuit and a peripheral circuit; the core circuit includes an FPGA chip, an FPGA configuration chip and a crystal oscillator, the FPGA chip is used for realizing the functions of a 8086CPU, the FPGA configuration chip is used for storing configuration information of an FPGA, and the crystal oscillator is used for providing an FPGA clock signal; and the FPGA chip includes a 8086CPU core, an UART core, an ROM and an SRAM, the UART core is used for serial port communication, the ROM is used for an instruction jump to the SRAM after electrification, and the SRAM stores run programs which all adopt VHDL hardware description language to compile. The FPGA-based microcomputer interface hardware experiment platform having complete functions of the 8086CPU not only supports routine microcomputer principle and interface experiments, but also supports advanced experiments such as an operating system loading process and BIOS programming.
Description
Technical field
The present invention relates to Microcomputer Interfacing Technology field, be specifically related to a kind of microcomputer interface hardware experiment platform, meet the requirement of experiment of student at " Principle of the computer and interface course ".
Background technology
" Principle of the computer and interface " course is an important Core curriculum of current numerous domestic university computer subject, this course is the course that a practicality is very strong, its computer experiment and Course Exercise two links are important steps of teaching, and therefore the quality of experiment porch really grasps Principles of Microcomputers to student and interfacing has very large impact.
Seen " Principle of the computer and interface " experiment porch technically, mainly contains four kinds below: (1) utilizes software to carry out analog hardware environment, the operating process that student tests in virtual environment in the market.(2) by pci bus or the isa bus driving chamber of standard microcomputer.For based on pci bus, first adopt CPLD/FPGA Programmable Technology design PCI-ISA bus switching circuit.Isa bus signal after isa bus or conversion is driven, and is supplied to outside experimental box use with DB62 form.(3) single-chip microcomputer or other non-8086CPU types is utilized simply to substitute or simulation 8086CPU.(4) 8086CPU chip structure experiment porch is utilized.
(1) kind method is because allow student test in virtual environment completely, and student cannot contact real hardware, so experiment effect is very poor.(2) kind method and (3) kind method can not depart from completely and the connection of PC and control in whole experimentation, comprise experimental arrangement and can not depart from operational process.These two kinds of methods are limit due to its hardware configuration and are not supported such as some advanced experiments such as operating system loading procedure, BIOS programming.(4) kind method have employed 8086CPU to realize, but belongs to the product at the beginning of the eighties at the end of the seventies in last century due to this CPU and the companion chip (example 8284 chip) that is associated, stops production already.Can only use the second-hand chip of the machine of tearing open, quality cannot ensure, also cannot volume production.
Summary of the invention
For the above defect of prior art, the invention provides one and there is the complete Full Featured microcomputer interface hardware experiment platform of 8086CPU, not only support conventional Principles of Microcomputers and interface experiment, also support the advanced experiment of such as operating system loading procedure, BIOS programming and so on, this invention overcomes pure software simulation or experimentation in existing method can not depart from the control of standard microcomputer or the limitation of the 8086CPU stopping production nothing supply of material completely.
A kind of microcomputer interface hardware experiment platform, comprise core circuit, interface circuit and peripheral circuit, peripheral circuit is connected through winding displacement with interface circuit, and interface circuit is connected through winding displacement with core circuit; Core circuit comprises fpga chip, FPGA configuring chip and crystal oscillator, and fpga chip is for realizing the function of 8086CPU, and FPGA configuring chip is for preserving the configuration information of FPGA, and crystal oscillator is used for providing FPGA clock signal; Fpga chip comprises 8086CPU core, UART core, ROM and SRAM, 8086CPU core is all connected with UART core, ROM with SRAM by data bus, address bus and control bus, UART core is used for serial communication, after ROM is used for powering on, instruction jumps to SRAM, SRAM is used for depositing working procedure, and 8086CPU core, UART core, ROM and SRAM all adopt VHDL hardware description language to write.
Further, described fpga chip adopts XC3S500E chip, and described FPGA configuring chip adopts XCF04SVOG20C configuring chip, and described crystal oscillator adopts 50M crystal oscillator.
Further, described peripheral circuit comprises LED, toggle switch, A/D module, D/A module, button, loudspeaker and FPGA power-switching circuit.
Further, described A/D module adopts AD0809 chip, and described D/A module adopts DA0832 chip.
Further, described interface circuit comprises 8259,8255 and 8253 chips.
It is different that the present invention overcomes the hardware environment (true 80x86 microcomputer environment) that domestic experiment porch hardware environment used (simulation 80x86 environment) and teaching material say.One completely independently Microcomputer Interface Experimental Platform is provided, student can be made to be absorbed in the Nature-Understanding of microcomputer interface experimental principle, carry out autonomous operating system experiment design, fully open up the thinking of student, thus the research and development ability of exercise student ' and practical operative ability.Specifically, technical characterstic of the present invention and beneficial effect are embodied in:
1) achieving 8086CPU core with VHDL hardware description language in FPGA inside makes Experiment of Principles of Microcomputers platform completely independently to run by PC with UART core.
2) compared with traditional experiment porch, above-mentioned experiment porch can realize the experiment that other scheme does not realize, as transplantation experiments and the BIOS experiment of operating system.
3) this invention is while the Principles of Microcomputers interfacing and correlated curriculum teaching request of satisfied routine, student can also be made to be deep into hardware bottom layer and go the hardware understanding bottom specifically how to work.
4) this invention can also be used for the Course Exercise of student, graduation project and electronic contest while the Principles of Microcomputers correlated curriculum teaching request of satisfied routine.
5) core circuit and interface circuit carry out being connected with winding displacement and make the structure of circuit very clear by this experiment porch, are convenient to the architecture of students microcomputer.
Accompanying drawing explanation
Fig. 1 is experiment porch the general frame of the present invention;
Fig. 2 is the functional block diagram that fpga chip of the present invention inside realizes;
Fig. 3 is 8086CPU core schematic diagram of the present invention;
Fig. 4 is UART core schematic diagram of the present invention;
Fig. 5 is FPGA circuit theory diagrams of the present invention;
Fig. 6 is A/D module circuit diagram of the present invention;
Fig. 7 is D/A module circuit diagram of the present invention;
Fig. 8 is key-press module circuit diagram of the present invention;
Fig. 9 is FPGA configuring chip circuit diagram of the present invention;
Figure 10 is FPGA power-switching circuit schematic diagram of the present invention;
Figure 11 is the crystal oscillating circuit schematic diagram of core circuit of the present invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.In addition, if below in described each embodiment of the present invention involved technical characteristic do not form conflict each other and just can mutually combine.
The 8086CPU part VHDL language description that experiment porch of the present invention is most crucial also realizes in fpga chip inside, whole FPGA is just equivalent to a 8086CPU, only inside fpga chip, also incorporate UART core, such FPGA be exactly one can the microcomputer of independent operating, various Experiment of Principles of Microcomputers can be completed based on this independently microcomputer.
As shown in Figure 1, the novel Microcomputer Interface Experimental Platform based on FPGA provided by the invention, comprise core circuit, interface circuit and peripheral circuit, core circuit comprises fpga chip, FPGA configuring chip and crystal oscillator.Interface kernel circuit comprises interface chip group, and peripheral circuit comprises LED, toggle switch, A/D module, D/A module, button, loudspeaker and FPGA power-switching circuit.Peripheral circuit is connected through winding displacement with interface circuit, and interface circuit is connected through winding displacement with core circuit.The present invention provides a preferred embodiment, core circuit comprises XC3S500E fpga chip, XCF04SVOG20C configuring chip and 50M crystal oscillator, interface circuit comprises 8259,8255,8253 chips, peripheral circuit comprises LED, toggle switch, button, AD/DA module, loudspeaker and FPGA power-switching circuit.
As shown in Figure 2, the core that the fpga chip inside of core circuit of the present invention generates comprises 8086CPU core, UART core, ROM and SRAM, 8086CPU core is all connected with UART core, ROM with SRAM by data bus, address bus and control bus, UART core is used for serial communication, and after ROM is used for powering on, instruction jumps to SRAM, and SRAM is used for depositing working procedure.They are all write with VHDL hardware description language, are then downloaded in fpga chip by Xilinx ISE Design Suite12.2 software downloader.
As shown in Figure 3,8086CPU core part of the present invention comprises the basic all functions of 8086CPU, and unique difference is the data bus of the 8086CPU describing out with VHDL is unidirectional, be divided into input and output, and the data bus of 8086CPU in kind is two-way.
As shown in Figure 4, the hard serial communication protocol that UART core part of the present invention comprises, only needs an additional level shift chip just can realize when needs serial ports communicates with microcomputer time again.
As shown in Figure 5, fpga chip pin circuitry figure of the present invention, extracts the FPGA pin used, and concrete extracts the pin extracted from core circuit plate in the mode of arranging pin exactly.
As shown in Figure 6, A/D module adopts AD0809 chip, and AD0809 is 8 A/D converters of CMOS, adopts Approach by inchmeal principle to carry out A/D conversion, there are Multipexer switch and A/D to change two large divisions in chip, can change the input analog voltage signal timesharing of 8 tunnels 0 to 5V.Analog multichannel switch is made up of 8 path analoging switch and 3 bit address latch decoders, can any road in gating 8 tunnel analog input, 3 bit address signal ADDA, ADDB, ADDC latch by address latch signal ALE, then by a decoding scheme gating road wherein, selected passage carries out A/D conversion.A/D conversion portion comprises comparer, successive approximation register (SAR), 256R resistor network, stub electronic switch, control and sequential circuit etc.ADC0809 exports and has TTL tri-state latch buffer in addition, can directly link on cpu data bus.
As shown in Figure 7, D/A module adopts DA0832 chip, and it is by 8 input registers, 8 DAC registers and one 8 D/A converter three part compositions.R-2R resistor network is adopted in D/A converter.LE signal is the internal control signal of each input register, as LE=1, receives input data; As LE=0, inner lock storage data.
As shown in Figure 8, be the circuit diagram of matrix press-key, each group matrix keyboard is driven by the pull-up resistor of 10K.
As shown in Figure 9, be FPGA configuring chip circuit of the present invention, configuring chip circuit pin comprises TMS, TCK, TD1, TD0, GND and VCC, and completes the programming of configuring chip content by Xilinx ISE Design Suite12.2.
As shown in Figure 10, be FPGA power-switching circuit of the present invention, comprise 5V and turn 3.3V, 5V turns 2.5V, and 3.3V turns 1.2V.
As shown in figure 11, be the crystal oscillating circuit in fpga core circuit of the present invention, crystal oscillator VCC end is connected with power supply by inductance.
The above, only that specific embodiment of the invention case is described, and be not used to limit of the present invention can practical range, all equivalences that all those skilled in the art complete under the spirit do not departed from indicated by the present invention and principle change or modify, and must be covered by the scope of the claims in the present invention.
Claims (5)
1. a microcomputer interface hardware experiment platform, comprise core circuit, interface circuit and peripheral circuit, peripheral circuit is connected through winding displacement with interface circuit, interface circuit is connected through winding displacement with core circuit, it is characterized in that, core circuit comprises fpga chip, FPGA configuring chip and crystal oscillator, and fpga chip is for realizing the function of 8086CPU, FPGA configuring chip is for preserving the configuration information of FPGA, and crystal oscillator is used for providing FPGA clock signal; Fpga chip comprises 8086CPU core, UART core, ROM and SRAM, 8086CPU core is all connected with UART core, ROM with SRAM by data bus, address bus and control bus, UART core is used for serial communication, after ROM is used for powering on, instruction jumps to SRAM, SRAM is used for depositing working procedure, and 8086CPU core, UART core, ROM and SRAM all adopt VHDL hardware description language to write.
2. microcomputer interface hardware experiment platform according to claim 1, is characterized in that, described fpga chip adopts XC3S500E chip, and described FPGA configuring chip adopts XCF04SVOG20C configuring chip, and described crystal oscillator adopts 50M crystal oscillator.
3. microcomputer interface hardware experiment platform according to claim 1 and 2, is characterized in that, described peripheral circuit comprises LED, toggle switch, A/D module, D/A module, button, loudspeaker and FPGA power-switching circuit.
4. microcomputer interface hardware experiment platform according to claim 3, is characterized in that, described A/D module adopts AD0809 chip, and described D/A module adopts DA0832 chip.
5. microcomputer interface hardware experiment platform according to claim 1 and 2, is characterized in that, described interface circuit comprises 8259,8255 and 8253 chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310311009.XA CN104346978A (en) | 2013-07-23 | 2013-07-23 | FPGA-based microcomputer interface hardware experiment platform |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310311009.XA CN104346978A (en) | 2013-07-23 | 2013-07-23 | FPGA-based microcomputer interface hardware experiment platform |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104346978A true CN104346978A (en) | 2015-02-11 |
Family
ID=52502487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310311009.XA Pending CN104346978A (en) | 2013-07-23 | 2013-07-23 | FPGA-based microcomputer interface hardware experiment platform |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104346978A (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020095619A (en) * | 2001-06-15 | 2002-12-28 | 주식회사 마이다스엔지니어링 | ASIC design trainer |
| JP2003156995A (en) * | 2001-11-20 | 2003-05-30 | Andor System Support Co Ltd | Remote education system for experiment and practice of digital circuit |
| CN2845324Y (en) * | 2005-04-27 | 2006-12-06 | 谢步明 | MVB equipment network interface card based on FPGA |
| CN201725180U (en) * | 2010-05-24 | 2011-01-26 | 安徽理工大学 | Self-tuning PID controller based on FPGA |
| CN201820383U (en) * | 2010-09-16 | 2011-05-04 | 深圳信息职业技术学院 | FPGA (field programmable gate array) teaching system |
| CN102289974A (en) * | 2011-08-17 | 2011-12-21 | 中南民族大学 | Novel microcomputer interface experimental platform based on PCI and FPGA |
| CN202887556U (en) * | 2012-09-27 | 2013-04-17 | 西安科技大学 | FPGA experiment development board |
| CN103064328A (en) * | 2012-12-15 | 2013-04-24 | 中国科学院近代物理研究所 | Digital pulse power supply synchronous timing trigger system |
-
2013
- 2013-07-23 CN CN201310311009.XA patent/CN104346978A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020095619A (en) * | 2001-06-15 | 2002-12-28 | 주식회사 마이다스엔지니어링 | ASIC design trainer |
| JP2003156995A (en) * | 2001-11-20 | 2003-05-30 | Andor System Support Co Ltd | Remote education system for experiment and practice of digital circuit |
| CN2845324Y (en) * | 2005-04-27 | 2006-12-06 | 谢步明 | MVB equipment network interface card based on FPGA |
| CN201725180U (en) * | 2010-05-24 | 2011-01-26 | 安徽理工大学 | Self-tuning PID controller based on FPGA |
| CN201820383U (en) * | 2010-09-16 | 2011-05-04 | 深圳信息职业技术学院 | FPGA (field programmable gate array) teaching system |
| CN102289974A (en) * | 2011-08-17 | 2011-12-21 | 中南民族大学 | Novel microcomputer interface experimental platform based on PCI and FPGA |
| CN202887556U (en) * | 2012-09-27 | 2013-04-17 | 西安科技大学 | FPGA experiment development board |
| CN103064328A (en) * | 2012-12-15 | 2013-04-24 | 中国科学院近代物理研究所 | Digital pulse power supply synchronous timing trigger system |
Non-Patent Citations (5)
| Title |
|---|
| 古丽米拉、张婧婧、海拉提: "微机原理与接口技术的开放型实验设计", 《计算机教育》 * |
| 张晶、李心广: "EDA 技术在微机接口技术实验教学中的应用", 《微电子技术》 * |
| 汤书森、马义德: "现代计算机组成原理课程特点与实验教学新模式探索", 《高等理科教育》 * |
| 董少明: "《单片机原理与应用技术》", 31 August 2009, 北京理工大学出版社 * |
| 谢伟: "《北京工业大学硕士学位论文》", 1 May 2011 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Ojo et al. | A review of low-end, middle-end, and high-end iot devices | |
| CN102289974A (en) | Novel microcomputer interface experimental platform based on PCI and FPGA | |
| CN105224345B (en) | A kind of programmable logic device remote update system and its method | |
| CN202563782U (en) | Singlechip experiment teaching development system | |
| CN204288623U (en) | A kind of multifunction electronic experiment integrated board | |
| CN104216324B (en) | Related methods of synthetic aperture radar task management controller | |
| CN203376909U (en) | Novel microcomputer principle and interface experiment system based on FPGA | |
| CN103117797A (en) | High-speed load data analog source | |
| Harris et al. | MIPSfpga: using a commercial MIPS soft‐core in computer architecture education | |
| CN202502660U (en) | Programmable digital logic circuit basic experiment plate | |
| Mesri | Design and user guide for the single chip mote digital system | |
| CN202373179U (en) | Novel microcomputer interface experiment platform based on PCI and FPGA | |
| CN104346978A (en) | FPGA-based microcomputer interface hardware experiment platform | |
| CN204808308U (en) | FPGACPLD procedure downloader based on programmable logic chip | |
| CN204808307U (en) | FPGACPLD procedure downloader based on USB singlechip | |
| CN203950176U (en) | A kind of wireless sensor network node hardware platform that can online reconfiguration | |
| CN112053615A (en) | Embedded experiment teaching system and teaching method | |
| CN202171889U (en) | Portable universal CPLD/FPGA teaching experimental instrument | |
| Liu | A hardware and software cooperative design of SoC IP | |
| CN109637312A (en) | A kind of on piece Digital Electronics Experiment system | |
| CN206133556U (en) | A computer central processing unit for teaching experiment | |
| CN103324589A (en) | SD (secure digital memory card) control system | |
| CN101286181B (en) | On site programmable gate array on-chip programmable system based on DW8051 core | |
| CN204087580U (en) | A kind of teaching EDA and SOPC brassboard of portable four line unifications | |
| CN203644279U (en) | Virtual instrument experiment system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150211 |
|
| WD01 | Invention patent application deemed withdrawn after publication |