CN103885843A - Method for processing safety parallel buses between DSP (digital signal processor) and CPLD (complex programmable logic device) - Google Patents
Method for processing safety parallel buses between DSP (digital signal processor) and CPLD (complex programmable logic device) Download PDFInfo
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- CN103885843A CN103885843A CN201310064802.4A CN201310064802A CN103885843A CN 103885843 A CN103885843 A CN 103885843A CN 201310064802 A CN201310064802 A CN 201310064802A CN 103885843 A CN103885843 A CN 103885843A
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Abstract
The invention discloses a method for processing safety parallel buses between a DSP (digital signal processor) and a CPLD (complex programmable logic device). The method includes implementing a recovery mechanism on an address distribution portion, a data bus portion and a communication safety portion. By the method, the safety problem caused by communication errors among parallel buses of the DSP can be effectively solved, and the DSP is enabled to be capable of finding reasons for the communication errors among the buses.
Description
Technical field
The present invention relates to a kind of can being applied in the system such as safety signal system, industry control message system, the disposal route of the safe parallel bus based between digital signal processor (DSP) and CPLD (CPLD).
Background technology
Digital signal processor DSP chip is due to reliable in quality, superior performance and being used in security system in a large number, and in digital signal processor DSP system, parallel bus is because transmitted data amount is large, speed is fast, disposal route be simply widely used.Typical digital signal processor DSP parallel bus Physical layer as shown in Figure 1, comprise address (Address Bus), data (Data Bus), read to control (Read Control), write four groups of signals of control (Write Control), these four groups of signals complete the read-write operation of main digital signal processor DSP to peripheral hardware according to specific sequential.When write operation, digital signal processor DSP first provides address signal, then write control signal is dragged down, and simultaneously by data data writing bus, is located at write signal rising edge outward by data reading.When read operation, digital signal processor DSP first provides address signal, then read control signal is dragged down, and is located at read signal negative edge outward by data data writing bus, digital signal processor DSP at read signal rising edge by data reading.When read-write, in digital signal processor DSP bus, sequential refers to Fig. 2 and Fig. 3.
Complex programmable logic device (CPLD), as the programmable logical device of one, often can help digital signal processor DSP to complete the function that digital signal processor DSP cannot cover with the form of peripheral hardware.As, can realize with complex programmable logic device (CPLD) the expansion of digital signal processor DSP IO pin, can utilize the crystal oscillator of complex programmable logic device (CPLD) to realize the monitoring to digital signal processor DSP clock, or can realize outer watchdog function with complex programmable logic device (CPLD).
Consider that complex programmable logic device (CPLD) consumes resource in the time processing complex time sequence logic more, so the connected mode between complex programmable logic device (CPLD) is main mainly with parallel bus at digital signal processor DSP at present.Be that digital signal processor DSP corresponding digital signals processor DSP in the rising edge of read control signal gathers complex programmable logic device (CPLD) sends the data of address, complex programmable logic device (CPLD) corresponding digital signals processor DSP in data are latching to complex programmable logic device (CPLD) by the rising edge of write control signal sends in the register of address.
But, be the safety that can not effectively guarantee communication by this bus mode.Especially in track transportation industry, owing to being subject to strong external interference, there is the Data flipping of single-bit or many bits in being easy on parallel bus, makes wrong data be read and write or greatly increase to the probability of wrong address read-write.If to this not fully protection, likely there is the situation of car crash in digital signal processor DSP system.
Summary of the invention
Technical matters to be solved by this invention is to provide the disposal route of safe parallel bus between a kind of DSP and CPLD, and it can effectively solve the safety problem because garble causes between digital signal processor DSP parallel bus.
In order to solve above technical matters, the invention provides the disposal route of safe parallel bus between a kind of DSP and CPLD; Comprise: to address distribution portion, data bus part and communication security are replied mechanism.
Beneficial effect of the present invention is: can effectively solve due to the safety problem that between digital signal processor DSP parallel bus, garble causes, can make digital signal processor DSP find garble reason between bus.
Between digital signal processor DSP and complex programmable logic device (CPLD), address and data are all coded message, and digital signal processor DSP must be carried out a read-write to complex programmable logic device (CPLD) particular state register LSR in the time executing write operation again, if the LSR value of reading is not equal to state encoding 1, digital signal processor DSP will think that write operation is failed, and digital signal processor DSP must be carried out the verification of complex programmable logic device (CPLD) data to judge data correctness in the time carrying out read operation.
In the time that digital signal processor DSP is write data to complex programmable logic device (CPLD), complex programmable logic device (CPLD) by first recording address and data to LAR and LDR and check the address of bringing in from digital signal processor DSP, if made mistakes, recording status coding 1 is to LSR, otherwise check the address that digital signal processor DSP is brought in, if made mistakes, recording status encodes 2 to LSR, otherwise recording status coding 3 to LSR and execution associative operation.
At digital signal processor DSP during to complex programmable logic device (CPLD) read data, first complex programmable logic device (CPLD) will check the address of bringing in from digital signal processor DSP, if made mistakes, output error encodes 1 to data bus, otherwise sends normal function value.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Fig. 1 is common parallel bus schematic diagram, comprises data bus, address bus and read-write control signal.
Fig. 2 is the read/write operation sequential schematic diagram of digital signal processor DSP.
The Physical layer of Fig. 3 parallel bus-read sequential schematic diagram.
Fig. 4 is that communication security is replied schematic diagram of mechanism.
Fig. 5 is during for digital signal processor DSP write operation, digital signal processor DSP and complex programmable logic device (CPLD) operational flowchart separately.
Fig. 6 is during for digital signal processor DSP read operation, digital signal processor DSP and complex programmable logic device (CPLD) operating process schematic diagram separately.
Embodiment
The invention discloses a kind of can being applied in the system such as safety signal system, industry control message system, the disposal route of the safe parallel bus based between digital signal processor (DSP) and CPLD (CPLD).This bus, on the basis of digital signal processor DSP parallel bus Physical layer, stipulates the disposal route of bus, effectively shield bus mistake and the safety problem that produces of the digital signal processor DSP system that has made to apply the design.The present invention, on the basis of digital signal processor DSP parallel bus, adds safe disposal route, has effectively avoided miscommunication between digital signal processor DSP and complex programmable logic device (CPLD) and the safety problem that produces.The present invention has designed a kind of disposal route of safe parallel bus, and the disposal route of being somebody's turn to do has been arranged the address assignment of address bus, and the coding requirement of data bus and associated safety are replied mechanism.
1, address bus part
Digital signal processor DSP address bus can be divided into block address (3bit) and general address (19bit), adds up to 22bit.In order to make address that checking feature can be provided, the low 4bit of address bus is designed to the CRC code of front 18bit.CRC polynomial expression is 10011, for example, is 101 o'clock in block address, gets rid of full 0 and complete 1 address outer (security system does not allow use), and all available address are:
101_00_0000_0000_0001_1101
101_00_0000_0000_0010_1000
101_00_0000_0000_0011_1011
……
101_11_1111_1111_1101_0000
101_11_1111_1111_1110_0101
When complex programmable logic device (CPLD) is received address, to detecting that address does CRC check, if check results is incorrect, complex programmable logic device (CPLD) thinks that address is invalid.
2, data bus part
Data on data bus (16bit) are all coded data, and coding intensity can be made adjusting according to practical application.For example digital signal processor DSP can be arranged with complex programmable logic device (CPLD): in the time sending a special value in the address wire of digital signal processor DSP in a certain agreement, (can be that a special value is as 50AF, also can be 12bit and add 4bitCRC code), complex programmable logic device (CPLD) will complete a certain function.
Do not meet previous about definite value when complex programmable logic device (CPLD) detects above-mentioned data, or corresponding verification is obstructed out-of-date, complex programmable logic device (CPLD) thinks that data check makes mistakes.
3, communication security is replied mechanism
In complex programmable logic device (CPLD), realize the register of 3 16bit, be respectively cycle status register (LSR), upper cycle address register (LAR), upper cycle data register (LDR).
For complex programmable logic device (CPLD), when each digital signal processor DSP is write data to complex programmable logic device (CPLD), complex programmable logic device (CPLD) all will record former Input Address to LAR, record former input data to LDR, and first verification address, if address right, checking data, otherwise LSR will represent that address makes mistakes with state encoding 1.If data check is made mistakes, LSR will represent that data make mistakes with state encoding 2, otherwise LSR will represent that address date is all correct with state encoding 3.If the state of LSR is not state encoding 3, complex programmable logic device (CPLD) can executable operations or failure to the safe side side (jumping to the safe state of acquiescence).
For digital signal processor DSP, each digital signal processor DSP is write after data to complex programmable logic device (CPLD), digital signal processor DSP must read the value of LSR register in a complex programmable logic device (CPLD), in the time reading as state encoding 3, digital signal processor DSP just continues write operation next time, otherwise whether digital signal processor DSP has unexpected address/data by the value of LAR and LDR in failure to the safe side side or the complex programmable logic device (CPLD) that reads back to differentiate.
And digital signal processor DSP is during to complex programmable logic device (CPLD) read data, whether the address that complex programmable logic device (CPLD) meeting check digit signal processor DSP sends is correct, and send correlation function encoded radio to be transferred to digital signal processor DSP or an error in address that fixing error coded 1 is sent with notice digital signal processor DSP according to this check results, and this error coded 1 is different from any function value.Digital signal processor DSP also can carry out data check while receiving the data that complex programmable logic device (CPLD) sends.Only have in the time of the corresponding valid data in Input Data Verification is correct and belong to that digital signal processor DSP sends address, digital signal processor DSP just can be thought and receive successfully.As shown in Figure 4.
The present invention can effectively solve due to the safety problem that between digital signal processor DSP parallel bus, garble causes, and can make digital signal processor DSP find garble reason between bus.
Just introduce the specific embodiment of the present invention in conjunction with Fig. 5, Fig. 6 below.
When digital signal processor DSP is carried out write operation, first send coded address and coded data, complex programmable logic device (CPLD) by the address on record trunk and data to LAR LDR and detect address and the verification correctness of data, as correctly carried out correlation function, otherwise failure to the safe side side record are represented to the correlation behavior of check errors is encoding to LSR.And digital signal processor DSP can be read LSR to judge the whether success of this write operation, as unsuccessful, by the value of reading LAR LDR register in complex programmable logic device (CPLD) to differentiate error reason.
When digital signal processor DSP is carried out read operation, first send address date, complex programmable logic device (CPLD) will detect address check correctness, as correctly sent correlation function value, otherwise send error coded 1 to data bus.First digital signal processor DSP can judge in the time obtaining data whether these data are error coded, if not further differentiating this data encoding verification correctness.In the time data bit error coded or data encoding check errors being detected, digital signal processor DSP can think that these data that obtain are insincere, thereby abandons these data of reading or failure to the safe side side.
The present invention is not limited to embodiment discussed above.Above the description of embodiment is intended in order to describe and illustrate the technical scheme the present invention relates to.Apparent conversion based on the present invention enlightenment or substitute and also should be considered to fall into protection scope of the present invention.Above embodiment is used for disclosing best implementation method of the present invention, to make those of ordinary skill in the art can apply numerous embodiments of the present invention and multiple alternative reaches object of the present invention.
Claims (4)
1. the disposal route of safe parallel bus between a DSP and CPLD; It is characterized in that, comprising: to address distribution portion (1), data bus part (2) and communication security are replied mechanism (3).
2. the disposal route of safe parallel bus between DSP as claimed in claim 1 and CPLD, it is characterized in that: between digital signal processor DSP and complex programmable logic device (CPLD), address and data are all coded message, and digital signal processor DSP must be carried out a read-write to complex programmable logic device (CPLD) particular state register LSR in the time executing write operation again, if the LSR value of reading is not equal to state encoding 1, digital signal processor DSP will think that write operation is failed, and digital signal processor DSP must be carried out the verification of complex programmable logic device (CPLD) data to judge data correctness in the time carrying out read operation.
3. the disposal route of safe parallel bus between DSP according to claim 2 and CPLD, it is characterized in that: in the time that digital signal processor DSP is write data to complex programmable logic device (CPLD), complex programmable logic device (CPLD) by first recording address and data to LAR and LDR and check the address of bringing in from digital signal processor DSP, if made mistakes, recording status coding 1 is to LSR, otherwise check the address that digital signal processor DSP is brought in, if made mistakes, recording status coding 2 is to LSR, otherwise recording status coding 3 to LSR and execution associative operation.
4. the disposal route of safe parallel bus between DSP according to claim 3 and CPLD, it is characterized in that: at digital signal processor DSP during to complex programmable logic device (CPLD) read data, first complex programmable logic device (CPLD) will check the address of bringing in from digital signal processor DSP, if made mistakes, output error encodes 1 to data bus, otherwise sends normal function value.
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Application publication date: 20140625 |