CN112052113B - Communication link layer message single event effect fault tolerance method and device - Google Patents
Communication link layer message single event effect fault tolerance method and device Download PDFInfo
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Abstract
The invention discloses a single event effect fault-tolerant method and a single event effect fault-tolerant device for a communication link layer message. The method does not depend on an external processor, can avoid serious problems of SV and GOOSE message misoperation, protection misoperation and the like caused by the influence of single event effect on the FPGA, and greatly improves the reliability of secondary equipment of the power system.
Description
Technical Field
The invention relates to an integrated chip single event effect error detection and correction method, in particular to a communication link layer message single event effect error tolerance method and device.
Background
With the technical development of high performance integrated circuits, it has become a mainstream trend to adopt high performance integrated circuit chips such as a general purpose processor (CPU), a programmable gate array (FPGA), and the like in secondary equipment of an electric power system. However, compared with the conventional circuit, the digital chip using the integrated circuit has low working voltage and complex design, and under the same conditions, especially with the improvement of the integrated chip process, the reduction of the device nuclear voltage and the sharp increase of the gate number, a series of Single Event effects such as Single Event Upset (SEU), single Event interruption and Single Event transient pulse in the integrated chip become more and more obvious. The space radiation interference resistance of an integrated circuit in the secondary equipment of the power system gradually becomes the bottleneck of the reliability of the secondary equipment of the power system, so certain measures must be taken to improve the space radiation fault-tolerant capability of the secondary equipment of the power system and improve the operation reliability of the equipment.
As a typical embedded system, the secondary equipment of the power system needs to provide different communication interfaces simultaneously and access mass communication data in parallel. Common bus communication modes in the power system include industrial ethernet, CAN, SPI, UART, dedicated communication interfaces and the like, each bus mode has a relatively independent architecture, great differences exist in the aspects of a physical layer, a data link layer and the like, interconnection and intercommunication among different bus interfaces are difficult, and service data are difficult to share in equipment. The FPGA is used as a carrier of a bus interface, the real-time performance and concurrency of the working of the FPGA circuit can be fully utilized, protocol conversion is carried out among all buses, and communication, exchange and sharing of various real-time and non-real-time data are realized. Therefore, in the integrated chip adopted by the secondary equipment of the power system, a programmable gate array (FPGA) is taken as one of representatives, has a series of advantages of overloading, expansion flexibility, parallel high processing performance and the like, can meet the requirements of communication interface expansion, parallel mass real-time data processing and high customization requirements of the power system, and becomes an indispensable basic chip of the secondary equipment of the power system. Therefore, in the single event effect fault-tolerant design of the integrated chip of the secondary equipment of the power system, the single event effect fault-tolerant design of the FPGA chip must be researched.
The FPGA chip is affected by different function modules with single event effect, and the affected consequences are different, for example, if the data communication link is affected by the single event effect, the transmitted communication data can be damaged at random, so that the device obtains or outputs data errors, the device can be alarmed or locked, the system can be quitted, even the output wrong SV and GOOSE data cause the problems of protection device misoperation and the like, and the system safety is seriously affected.
Most researches on the existing FPGA chip single event effect resistance error detection and correction method and system are focused on aerospace application in a high-irradiation environment, the modes are multiple, the error detection and correction capability is strong, and the method mainly comprises bit stream read-back and write-through, error detection and correction design and triple modular redundancy design.
The current FPGA SEU flash-resistant design for aerospace is introduced in the thesis SRAM type FPGA SEU-resistant design for aerospace. The basic principle of the mode is that bit stream readback of data in a configuration RAM area is carried out through an FPGA chip configuration interface, then the bit stream readback is compared with original configuration data, and if inconsistency occurs, reconfiguration is initiated to carry out error recovery. However, the universal read-back and check mode needs to check all configuration data, and the time interval for error detection and correction is long, generally about tens of milliseconds, and cannot meet the requirement of fault-tolerant real-time performance that the control operation frequency of the secondary equipment of the power system is above kHz level.
The thesis "SRAM type FPGA SEU mitigation and verification technology analysis" gives a general error detection and correction design of error correction coding technology. The method is that after the content of a data transmission channel and an RAM area is added with check information according to a certain rule, error detection and error correction are carried out through the check information. The basic principle is that a data transmitting end stores or transmits a symbol sequence after source coding and attaches parity symbols such as Hamming codes, and the parity symbols are associated with information symbols in a certain way. At the data receiving end, whether the data relation between the data bit and the check bit corresponds to each other can be detected according to a corresponding encoding principle, so that the data is subjected to error detection and certain error recovery. Although the method has less resource consumption and certain error detection and correction capability, the method is only suitable for the message error detection and correction of the receiving end and has no fault-tolerant capability for the message sending end.
Because communication is used as one of main functions of the FPGA, the direct adoption of system-level triple modular redundancy can greatly improve the hardware design cost, and is not suitable for secondary equipment of a cost-sensitive power system.
In conclusion, for the single event effect fault-tolerant design of the link communication link of the FPGA chip of the secondary equipment of the power system, the method can only carry out the single event effect fault-tolerant design on the configuration data and the storage area, cannot cover the whole communication link, and cannot solve the system safety problem caused by the output of error messages.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to provide a communication link layer message single event effect fault-tolerant method and a communication link layer message single event effect fault-tolerant device which are suitable for secondary equipment of a power system and can cover the whole communication link so as to solve the system safety problem caused by error message output.
The technical scheme is as follows: the invention discloses a single event effect fault-tolerant method for a communication link layer message, which comprises the following steps:
(1) The CPU writes the application data into an application message buffer and waits for a command to be sent;
(2) When the message sending module starts sending the link layer message, sending a frame header;
(3) Reading application data by byte in an application message buffer area, sending the read application data to a physical layer through a message sending module, and stopping sending when an invalid information segment is encountered; meanwhile, the frame check codes are calculated in real time according to a frame check code generation rule;
(4) In the process of real-time parallel computing frame check codes, a message receiving and reading-back module firstly judges whether a frame is valid; if the frame is valid, the message receiving and reading-back module reads back the link layer message, analyzes the read-back link layer message and extracts real-time read-back data;
(5) The message real-time check comparison module reads the application data at the same position of the application message buffer after the message receiving read-back module starts to extract the real-time application data;
(6) The message real-time check comparison module carries out real-time bit-by-bit comparison on the application data read in the step (5) and the real-time read-back data extracted in the step (4) according to the sequence, and judges whether the application data is consistent with the real-time read-back data; if the real-time comparison result shows that the currently compared application data is inconsistent with the real-time read-back data, judging that the application data is abnormal; otherwise, judging the test result to be normal; then, outputting a real-time comparison result;
(7) And the message error processing module performs single event effect error processing on the abnormal comparison result output by the message real-time verification comparison module.
The application message buffer area adopts a dual-port RAM controller, one port of the dual-port RAM controller is used for sending application data to a message sending module, and the other port of the dual-port RAM controller is used for sending application data to a message real-time verification comparison module.
In the step (1), the application data is written into the application message buffer area through a communication bus.
In the step (3), the message sending module performs message framing on the application data according to a link layer message communication frame format and then sends the application data to a physical layer.
In the step (7), the message error processing module performs single event effect error processing on the abnormal comparison result output by the message real-time verification comparison module by adopting an error quality processing method or an error message error correction method.
In the step (7), the single event effect error processing is specifically to change frame quality information in a link layer message frame format.
In the step (7), when the message error processing module adopts an error quality processing method to process the single event effect error, after the step (6) judges that the single event effect error is abnormal, the message error processing module outputs frame quality abnormal information; then, the message sending module reads the message quality information output by the message error processing module while sending the invalid field, and sends the frame quality information after the invalid field is sent; finally, sending a frame check code of real-time parallel computation; and (5) when the step (6) is judged to be normal, outputting the information with normal frame quality by the message error processing module.
In step (7), when the message error processing module adopts an error message error correction method to perform single event effect error processing, a message sending data register is arranged between the output end of the link layer message and the physical layer interface.
When the message error processing module adopts an error message error correction method to process the single event effect error, after the step (6) judges that the error is abnormal, the message state processing module directly sends correct data to a message sending data register according to the error detection information provided in the step (6) so as to replace the error data, and the message is normally sent.
The link layer message communication frame format comprises a frame header, application data, an invalid information segment, a frame quality information segment and a frame check code.
The invention also comprises a single event effect fault-tolerant device of the message of the communication link layer, which comprises an application message buffer area, a message sending module, a message receiving and reading-back module, a message real-time checking and comparing module and a message error processing module; the application message buffer is connected to the physical layer through a message sending module; the input end of the message receiving and reading-back module is connected between the message sending module and the physical layer, the output end of the message receiving and reading-back module is connected with the message real-time checking and comparing module, and the message real-time checking and comparing module is also connected with the application message buffer area; a message error processing module is connected between the message real-time checking and comparing module and the message sending module; after the application message buffer area reads the application data, the message sending module performs message framing on the application data according to a link layer message communication frame format and then sends the application data to a physical layer, and the message receiving and reading-back module reads back and analyzes a link layer message to extract real-time read-back data; the message real-time check comparison module reads the application data at the same position of the application message buffer area, compares the read application data with the real-time read-back data in real time bit by bit, and judges the consistency of the data; and the message error processing module processes the abnormal data.
The application message buffer area adopts a dual-port RAM controller, one port of the dual-port RAM controller is used for sending application data to a message sending module, and the other port of the dual-port RAM controller is used for sending application data to a message real-time verification comparison module.
Has the advantages that: compared with the prior art, the invention has the beneficial effects that: (1) All the functional logic modules are realized in the FPGA chip, do not depend on external equipment, are not only suitable for a CPU component adopting the FPGA chip, but also can be applied to an ADC and a communication component; (2) The link layer message can be subjected to real-time error detection, error message processing is realized in the sending period, and the real-time performance is high; (3) When the error detection of the link layer message is carried out, the error detection is directly carried out on the final output message, all links of the link layer message communication are covered, the detection coverage is wide, the reliability is higher, the false exit of the false message is effectively prevented, and the problems that the power system safety is seriously influenced by various types of false actions, refusal actions, sampling value errors and the like are avoided.
Drawings
FIG. 1 is a flow chart of the present invention;
FIG. 2 is a schematic diagram of a message error processing module according to the present invention when processing by an error quality processing method;
fig. 3 is a schematic diagram of an architecture of the message error processing module according to the present invention when the message error processing module is processed by an error message error correction method.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and specification.
As shown in fig. 2, the fault-tolerant apparatus for single event effect of a communication link layer packet of the present invention includes an application packet buffer, a packet sending module, a packet receiving and reading-back module, a packet real-time checking and comparing module, and a packet error processing module. The application message buffer is connected with the physical layer through a message sending module. The input end of the message receiving and reading back module is connected between the message sending module and the physical layer, and the output end of the message receiving and reading back module is connected with the message real-time checking and comparing module. And a message error processing module is connected between the message real-time checking and comparing module and the message sending module. The message real-time checking and comparing module is also connected with the application message buffer area. Wherein, the application message buffer area adopts a dual-port RAM controller with the size of 2kB. One port of the dual-port RAM controller is used for sending application data to the message sending module, and the other port of the dual-port RAM controller is used for sending application data to the message real-time checking and comparing module. The message sending module realizes the interrupt trigger sending control.
The application message buffer zone is used for realizing the caching of application data; the message sending module realizes the interrupt triggering sending control, and performs message framing on the application data according to the link layer message communication frame format to send the application data to the physical layer; the message receiving and reading-back module realizes real-time message reading-back through a message reading-back channel; the message real-time check comparison module compares the application data in the read-back message with the data in the application buffer zone bit by bit and outputs a comparison result; the message error processing module realizes that the error detection information output by the real-time checking and comparing module carries out single event effect error processing by an error processing method. The error processing method comprises an error quality processing method and an error message error correction method, and the two methods can be respectively and independently realized.
As shown in fig. 1, the single event effect fault-tolerant method for a communication link layer message of the present invention includes the following steps:
(1) The CPU writes the application data into an application message buffer area of a corresponding port through a communication bus and waits for a sending command;
(2) When the link layer message starts to be sent, sending a frame header;
(3) Reading application data by byte in an application message buffer area, sending the read application data to a physical layer through a message sending module, and stopping sending when an invalid information segment is encountered; meanwhile, the frame check codes are calculated in real time according to a frame check code generation rule; the message sending module performs message framing on the application data according to a link layer message communication frame format and then sends the application data to a physical layer. The link layer message communication frame format comprises a frame header, application data, an invalid information segment, a frame quality information segment and a frame check code.
(4) In the process of real-time parallel computing frame check codes, a message receiving and reading-back module firstly judges whether a frame is valid; if the frame is valid, the message receiving and reading-back module reads back the link layer message according to the link layer protocol, analyzes the read-back link layer message according to the link layer message communication frame format, and extracts real-time read-back data;
(5) After the message receiving and reading-back module starts to extract the real-time application data, the other port of the message real-time checking and comparing module reads the application data at the same position of the application message buffer area;
(6) The message real-time check comparison module carries out real-time bit-by-bit comparison on the application data read in the step (5) and the real-time read-back data extracted in the step (4) according to the sequence, and judges whether the application data is consistent with the real-time read-back data; if the real-time comparison result shows that the currently compared application data is inconsistent with the real-time read-back data, judging that the application data is abnormal; otherwise, judging the test result to be normal; then, outputting a real-time comparison result;
(7) And the message error processing module adopts an error quality processing method or an error message error correction method to carry out single event effect error processing on the abnormal comparison result output by the message real-time verification comparison module. The single event effect error processing is specifically to change frame quality information in a link layer message frame format.
As shown in fig. 1 and 2, the error handling quality method includes a link layer message communication frame format and a corresponding error handling module. When the message error processing module adopts an error quality processing method to process the single event effect error, after the step (6) judges that the frame quality is abnormal, the message error processing module outputs frame quality abnormal information 1; then, the message sending module reads the message quality information output by the message error processing module while sending the invalid field, and sends the frame quality information after the invalid field is sent; finally, sending the CRC-32 frame check code of real-time parallel computation; and (5) when the step (6) is judged to be normal, the message error processing module outputs frame quality normal information 0.
As shown in fig. 1 and fig. 3, the error message correction method includes a message sending data register and a corresponding error processing module. When the message error processing module adopts an error message error correction method to process the single event effect error, a message sending data register is arranged between the output end of the link layer message and a physical layer interface. And (4) after the step (6) judges that the message is abnormal, the message state processing module directly sends correct data to a message sending data register according to the error detection information provided in the step (6) so as to replace the error data, and the message is normally sent.
The method is applied to an intelligent bus relay protection device. The intelligent bus relay protection device is designed in a plug-in mode and comprises a power supply board card, a CPU board card, an SV board card, a GOOSE board card and an input/output board card. The CPU board card realizes the realization of a relay protection algorithm and outputs a protection action signal, and the SV and GOOSE board card realizes the communication of SV and GOOSE messages based on an IEC61850 protocol. The CPU board card, the SV board card and the GOOSE board card comprise an FPGA, and the single event effect fault-tolerant method is adopted.
The CPU board card adopts a 'CPU + FPGA' architecture. The FPGA is Xilinx FPGA of a certain model, the CPU and the FPGA communicate through an AXI high-speed bus, and the protection application is realized in a CPU general processor. The FPGA mainly realizes a time-setting and time-keeping module based on an external time-setting signal and a real-time communication Ethernet module integrating three networks of 3 paths of SV, GOOSE and MMS. The single event effect fault-tolerant method is realized in the FPGA, and the method is adopted for SV and GOOSE message transmission.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The present invention is not limited to the above embodiments, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are included in the scope of the claims of the present invention which are filed as the application.
Claims (11)
1. A communication link layer message single event effect fault-tolerant method is characterized by comprising the following steps:
(1) The CPU writes the application data into an application message buffer area and waits for a sending command;
(2) When the message sending module starts sending the link layer message, sending a frame header;
(3) Reading application data by bytes in the application message buffer area, sending the read application data to a physical layer through a message sending module, and stopping sending when an invalid information segment is encountered; meanwhile, the frame check codes are calculated in real time according to a frame check code generation rule;
(4) In the process of real-time parallel computing frame check codes, a message receiving and reading-back module firstly judges whether a frame is valid; if the frame is valid, the message receiving and reading-back module reads back the link layer message, analyzes the read-back link layer message and extracts real-time read-back data;
(5) The message real-time check comparison module reads the application data at the same position of the application message buffer after the message receiving read-back module starts to extract the real-time application data;
(6) The message real-time check comparison module carries out real-time bit-by-bit comparison on the application data read in the step (5) and the real-time read-back data extracted in the step (4) according to the sequence, and judges whether the application data is consistent with the real-time read-back data; if the real-time comparison result shows that the currently compared application data is inconsistent with the real-time read-back data, judging that the application data is abnormal; otherwise, judging the test result to be normal; then, outputting a real-time comparison result;
(7) And the message error processing module carries out single event effect error processing on the abnormal comparison result output by the message real-time checking and comparing module.
2. The communication link layer message single event effect fault-tolerant method according to claim 1, characterized in that: in the step (1), the application data is written into the application message buffer area through a communication bus.
3. The communication link layer message single event effect fault-tolerant method according to claim 1, characterized in that: in the step (3), the message sending module performs message framing on the application data according to a link layer message communication frame format and then sends the application data to a physical layer.
4. The communication link layer message single event effect fault-tolerant method according to claim 1, characterized in that: in the step (7), the message error processing module performs single event effect error processing on the abnormal comparison result output by the message real-time verification comparison module by adopting an error quality processing method or an error message error correction method.
5. The communication link layer message single event effect fault-tolerant method according to claim 1, characterized in that: in the step (7), the single event effect error processing is specifically to change frame quality information in a link layer message frame format.
6. The communication link layer message single event effect fault-tolerant method according to claim 4, characterized in that: in the step (7), when the message error processing module adopts an error quality processing method to process the single event effect error, after the step (6) judges that the single event effect error is abnormal, the message error processing module outputs frame quality abnormal information; then, the message sending module reads the message quality information output by the message error processing module while sending the invalid field, and sends the frame quality information after the invalid field is sent; finally, sending a frame check code of real-time parallel computation; and (4) when the step (6) is judged to be normal, the message error processing module outputs the information with normal frame quality.
7. The communication link layer message single event effect fault-tolerant method according to claim 4, characterized in that: in step (7), when the message error processing module adopts an error message error correction method to perform single event effect error processing, a message sending data register is arranged between the output end of the link layer message and the physical layer interface.
8. The communication link layer message single event effect fault-tolerant method according to claim 7, characterized in that: when the message error processing module adopts an error message error correction method to process the single event effect error, after the step (6) judges that the error is abnormal, the message state processing module directly sends correct data to a message sending data register according to the error detection information provided in the step (6) so as to replace the error data, and the message is normally sent.
9. The communication link layer message single event effect fault-tolerant method according to claim 3, characterized in that: the link layer message communication frame format comprises a frame header, application data, an invalid information segment, a frame quality information segment and a frame check code.
10. A fault-tolerant device of a single event effect fault-tolerant method of a communication link layer message according to any one of claims 1 to 9, characterized in that: the system comprises an application message buffer area, a message sending module, a message receiving and reading-back module, a message real-time checking and comparing module and a message error processing module; the application message buffer is connected to the physical layer through a message sending module; the input end of the message receiving and reading-back module is connected between the message sending module and the physical layer, the output end of the message receiving and reading-back module is connected with the message real-time checking and comparing module, and the message real-time checking and comparing module is also connected with the application message buffer area; a message error processing module is connected between the message real-time checking and comparing module and the message sending module;
after the application message buffer area reads the application data, the message sending module performs message framing on the application data according to a link layer message communication frame format and sends the application data to a physical layer, and the message receiving and reading-back module reads back and analyzes a link layer message to extract real-time read-back data; the message real-time check comparison module reads the application data at the same position of the application message buffer area, compares the read application data with the real-time read-back data in real time bit by bit, and judges the consistency of the data; and the message error processing module processes the abnormal data.
11. The fault tolerant device of claim 10: and the application message buffer area adopts a dual-port RAM controller, one port of the dual-port RAM controller is used for sending application data to the message sending module, and the other port of the dual-port RAM controller is used for sending the application data to the message real-time checking and comparing module.
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| CN107015880A (en) * | 2016-01-28 | 2017-08-04 | 京微雅格（北京）科技有限公司 | A kind of FPGA circuitry and its configuration file processing method |
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