CN114825293A - Relay protection device and method for preventing single event upset - Google Patents
Relay protection device and method for preventing single event upset Download PDFInfo
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- CN114825293A CN114825293A CN202210620733.XA CN202210620733A CN114825293A CN 114825293 A CN114825293 A CN 114825293A CN 202210620733 A CN202210620733 A CN 202210620733A CN 114825293 A CN114825293 A CN 114825293A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/26—Sectionalised protection of cable or line systems, e.g. for disconnecting a section on which a short-circuit, earth fault, or arc discharge has occured
- H02H7/261—Sectionalised protection of cable or line systems, e.g. for disconnecting a section on which a short-circuit, earth fault, or arc discharge has occured involving signal transmission between at least two stations
- H02H7/262—Sectionalised protection of cable or line systems, e.g. for disconnecting a section on which a short-circuit, earth fault, or arc discharge has occured involving signal transmission between at least two stations involving transmissions of switching or blocking orders
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Abstract
The invention discloses a relay protection device and a method for preventing single event upset, wherein the relay protection device comprises at least 4 cores, the cores comprise a receiving and transmitting core and at least 3 logic cores, and the dominant frequency of each core is more than or equal to 1.2 GHz; the method comprises the following steps: the receiving and sending core receives external data and carries out preprocessing; the preprocessing comprises basic analysis of data and addition of CRC (cyclic redundancy check) codes at the tail of the data; each logic core carries out CRC (cyclic redundancy check) on the preprocessed data, and if the CRC is correct, export data calculation is carried out; carrying out export preprocessing on the data after the export calculation is finished; the export pretreatment comprises adding CRC codes to the data; and performing CRC (cyclic redundancy check) on the data subjected to export preprocessing by the transceiving check, if the data is qualified, performing export logic judgment on the data, and if the data is qualified, exporting the data. According to the invention, data verification is arranged in multiple links of the relay protection device, and data changed due to single event upset can be effectively eliminated, so that the operation risk of a main power grid is reduced.
Description
Technical Field
The invention relates to a relay protection device and method for preventing single event upset, and belongs to the technical field of relay protection of power systems.
Background
Particle radiation brought by high-energy particles (protons, electrons, heavy ions and the like) in the atmospheric environment can seriously affect electronic devices, and after an integrated circuit component in the relay protection device is bombarded by the high-energy particles, the state of the integrated circuit component is possibly inverted, and the effect is called single-particle inversion effect. If the state of the component is turned over in error, the integrated circuit component can be unstable in work and even generate fatal errors, and acquisition errors are caused, which is particularly serious in the field of relay protection. Therefore, it is more and more important how to design and implement the integrated circuit device so as to reduce the influence caused by single event upset.
Meanwhile, the relay protection device is a first defense line of the power system, has four basic requirements of selectivity, speed, sensitivity and reliability, and directly guarantees the operation safety of a main power grid for safe and stable operation of the power grid, particularly a medium-high voltage relay protection device, so that the false action influence caused by single event upset is avoided in the medium-high voltage relay protection device, and reliable software and hardware design is particularly important.
Disclosure of Invention
The technical problem to be solved by the invention is to overcome the defects of the prior art and provide the relay protection device and the method for preventing the single event upset.
In order to achieve the above object, a first aspect of the present invention provides a relay protection device for preventing single event upset, the relay protection device having at least four cores, the cores of the relay protection device including:
the receiving and sending core is used for receiving and sending data, adding a CRC (cyclic redundancy check) code to the received data and carrying out CRC check on the data to be exported;
and the logic cores are used for carrying out logic operation, adding CRC check codes to the data after the logic operation and carrying out CRC check on the received data, and at least 3 logic cores are arranged;
and each logic core is in communication connection with the transceiving core.
Further, the number of core processors is 4.
Further, the main frequency of each core processor is greater than or equal to 1.2 GHz.
In a second aspect, the present invention provides a method for preventing single event upset based on the relay protection device of the first aspect, including the following steps:
the receiving and sending core receives external data and carries out preprocessing; the preprocessing comprises the steps of carrying out basic analysis on data and adding a CRC (cyclic redundancy check) code at the tail of the data;
each logic checks the preprocessed data to perform CRC check, and if the check is correct, the export data is calculated;
each logic core carries out export preprocessing on the data after the export calculation is finished; the export pretreatment comprises adding CRC codes to data;
and performing CRC (cyclic redundancy check) on the data subjected to export preprocessing by the transceiving check, if the data is qualified, performing export logic judgment on the data, and if the data is qualified, exporting the data.
Further, the data received by the transceiving core comprises: switching value data and analog value data.
Further, the data is subjected to export logic judgment, and if the data is qualified, the data is exported, which includes:
and comparing the data in the three logic cores in sequence by two into one group, exporting the consistent result if the comparison result is consistent, and not exporting the result if the comparison result is not consistent after all comparisons are finished.
The invention achieves the following beneficial effects:
(1) the mode of multi-core (four-core and above) operation is divided into the independent operation of the receiving and transmitting core and the logic core, so that the independent operation of a plurality of relay protection logics is realized without mutual interference.
(2) The method ensures the correctness of the input data of the device by adding the CRC code from the original received data and adds the verification on the source, so that whether the data is correct or not can be identified in the subsequent transmission, and the condition that the data is damaged by single event upset without perception is avoided.
(3) The reliability of data transmission among multiple cores is ensured by a mode of transmitting data with CRC codes between the receiving and transmitting cores and the logic core, so that the possibility that data is tampered and the calculation logic is wrong due to the fact that a component is subjected to single event upset in data transmission inside the device is avoided.
(4) The influence of single event upset on certain nuclear logic is avoided through the 'two-out-of-three software' logic judgment of the export data, the probability that two single event upsets occur in the same device at the same time is basically 0, the reliability of the export of the relay protection device is guaranteed, and the four-property requirement of relay protection is met.
Drawings
Fig. 1 is a block diagram of an architecture of a multi-core processor in a relay protection device and a method for preventing single event upset according to an embodiment of the present invention;
fig. 2 is a flowchart of data transmission with CRC check between cores of a multi-core processor in the relay protection device and method for preventing single event upset according to the embodiment of the present invention;
fig. 3 is a schematic diagram of verifying data after export preprocessing by a transceiver core in the relay protection device and method for preventing single event upset according to the embodiments of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
The nouns of the prior art explain: CRC: cyclic Redundancy Check (CRC).
The first embodiment is as follows:
the embodiment of the invention provides a relay protection device for preventing single event upset, which at least comprises four core processors, wherein each core processor comprises a receiving-transmitting core and a logic core, the receiving-transmitting core is in communication connection with the logic core, the receiving-transmitting core is used for receiving and transmitting data, a CRC (cyclic redundancy check) code is added for the data when the data are received, the CRC is performed before a data outlet, the CRC code is added at the source of data processing, the identification of whether the data are correct or not is facilitated in subsequent transmission, and the situation that the data are damaged by the single event upset without being sensed can be avoided; the logic core is used for carrying out logic operation on data and carrying out CRC (cyclic redundancy check) on the received data, the logic core carries out logic operation after receiving the data from the receiving and sending core, a CRC check code is added on the data after the logic operation is finished, then the data are sent to the receiving and sending core for sending operation, as the probability that two single event upsets occur simultaneously in the same device is 0, in order to ensure the reliability of the data at the outlet of the relay protection device and facilitate the logical judgment of 'two out of three in software', the logic cores are at least three and carry out logic operation respectively and independently without interference, in the embodiment of the invention, on the basis of confirming the existing operation, the cost is saved simultaneously, the relay protection device adopts a relay protection device with 4 core processors, the main frequency of each core processor is not less than 1.2GHz, wherein 3 core processors are logic cores, and 1 core processor is a transceiving core.
Example two:
based on the relay protection device for preventing single event upset provided by the first embodiment, the second embodiment of the invention provides a method for preventing single event upset, as shown in fig. 1 to fig. 3, the relay protection device at least comprises four core processors, one core is used as a receiving and sending core in the relay protection device for receiving and sending data, and the rest cores are used as logic cores and are respectively in communication connection with the receiving and sending cores for logic calculation and processing, so that independent operation of multiple relay protection logics is realized without mutual interference; according to the invention, the CRC code is added from the originally received data, so that the correctness of the input data can be effectively ensured, and the correctness of the data can also be ensured in the subsequent transmission by adding the verification mode at the source, so that the condition that the single event cannot be sensed when the single event is overturned is avoided; according to the invention, the CRC check code is added when the data is transmitted between the transceiving core and the logic core, so that the reliability of data transmission among a plurality of cores can be effectively ensured, the data is prevented from being tampered due to the fact that a component is subjected to single event upset when the data in the device is transmitted, and the calculation logic error is prevented; according to the invention, the logical judgment of 'two out of three software' is carried out on the outlet data before the outlet, and the probability that two single event upsets occur at the same time in the same device is basically 0, so that the reliability of the outlet of the relay protection device can be effectively ensured through the judgment of 'two out of three software', and the requirement of the four characteristics of relay protection is met.
A second embodiment of the present invention provides a method for preventing single event upset, as shown in fig. 1, in order to ensure completion of "two out of three software" logical judgment as described in the first embodiment, a relay protection device having at least four core processors is selected, and in the embodiment of the present invention, on the premise of ensuring function implementation, a relay protection device having four cores is selected to save industrial cost; one core is used as a receiving and sending core for receiving and sending data, the other three cores are used as logic cores for carrying out relay protection logic operation, each logic core is in communication connection with the receiving and sending core, and each logic core independently runs the relay protection logic operation without mutual interference.
As shown in fig. 2, on the basis, after the external switching value data and the analog data enter the relay protection device, the receiving and sending core in the relay protection device receives the external data, and after receiving the data, the received data is basically analyzed, then a CRC check code is added at the end of the data after the basic analysis is completed, and then the data attached with the CRC check code is put into the inter-core shared memory for use by three logic cores.
When each logic core operates, firstly, data to be used is taken out from the shared memory among the cores, then the data is checked by the CRC code, if the data is checked to be qualified, the data is prepared to be exported, export data calculation is carried out on the data to be exported, and if the data is not checked to be qualified, the data is not exported; through the design, the invention can effectively avoid the miscalculation phenomenon of the computational logic when the data is incorrect due to the single event upset.
After the output data is calculated by each logic core, adding a CRC (cyclic redundancy check) code at the tail of the output data, and storing the output data attached with the CRC code into the inter-core shared memory again so as to facilitate the receiving and transmitting cores to read;
as shown in fig. 3, after the transceiving core reads data, first performing CRC check on the data, after the CRC check is qualified, performing export logic judgment on the data, and if the data is qualified, exporting the data, specifically including the following steps:
comparing the acquired data in the three logic cores in sequence by two groups, if the comparison results are consistent, exporting the consistent results, and if the comparison results are not consistent after all comparisons are finished, not exporting the results, during specific implementation, firstly arbitrarily appointing the three logic cores to be a logic core 1, a logic core 2 and a logic core 3 respectively, and naming the logic cores is mainly convenient for verification description without special appointed requirements; then comparing the data of the logic core 1 and the logic core 2, and if the two data are consistent, directly taking the data as export data to export; otherwise, comparing the data of the logic cores 1 and 3, and if the data of the logic cores are consistent, outputting; otherwise, continuously comparing the data of the logic cores 2 and 3, if the data are consistent, exporting, and if the data are not consistent, not exporting; in the invention, the software three-out-of-two logic judgment can avoid the misoperation of the outlet, because the single event influences the component data of one core processor at most, and cannot influence a plurality of core processors simultaneously, and the method can effectively avoid the influence of the single event upset on the outlet data.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (6)
1. A protective relaying device for preventing single event upset, characterized in that:
the relay protection device is provided with at least four cores, and the cores of the relay protection device comprise:
the receiving and sending core is used for receiving and sending data, adding a CRC (cyclic redundancy check) code to the received data and carrying out CRC check on the data to be exported;
and the logic cores are used for carrying out logic operation, adding CRC check codes to the data after the logic operation and carrying out CRC check on the received data, and at least 3 logic cores are arranged;
and each logic core is in communication connection with the transceiving core.
2. The relay protection device for preventing single event upset according to claim 1, wherein:
the number of core processors is 4.
3. The relay protection device for preventing single event upset according to claim 1, wherein:
the main frequency of each core processor is greater than or equal to 1.2 GHz.
4. The method for preventing the relay protection device from the single event upset as claimed in claims 1 to 3, wherein the method comprises the following steps:
the method comprises the following steps:
the receiving and sending core receives external data and carries out preprocessing; the preprocessing comprises basic analysis of data and addition of CRC (cyclic redundancy check) codes at the tail of the data;
each logic checks the preprocessed data to perform CRC check, and if the check is correct, the export data is calculated;
each logic core carries out export preprocessing on the data after the export calculation is finished; the export pretreatment comprises adding CRC codes to data;
and performing CRC (cyclic redundancy check) on the data subjected to export preprocessing by the transceiving check, if the data is qualified, performing export logic judgment on the data, and if the data is qualified, exporting the data.
5. The method for preventing single event upset according to claim 4, wherein:
the data received by the transceiving core comprises: switching value data and analog value data.
6. The method for preventing single event upset according to claim 4, wherein:
and carrying out export logic judgment on the data, and if the data is qualified, exporting the data, wherein the export logic judgment comprises the following steps:
and comparing the data in the three logic cores in sequence by two into one group, exporting the consistent result if the comparison result is consistent, and not exporting the result if the comparison result is not consistent after all comparisons are finished.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210620733.XA CN114825293A (en) | 2022-06-02 | 2022-06-02 | Relay protection device and method for preventing single event upset |
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| CN202210620733.XA CN114825293A (en) | 2022-06-02 | 2022-06-02 | Relay protection device and method for preventing single event upset |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116631492A (en) * | 2023-07-25 | 2023-08-22 | 中国电力科学研究院有限公司 | Relay protection method and system based on multi-core processor chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116631492A (en) * | 2023-07-25 | 2023-08-22 | 中国电力科学研究院有限公司 | Relay protection method and system based on multi-core processor chip |
| CN116631492B (en) * | 2023-07-25 | 2023-09-26 | 中国电力科学研究院有限公司 | Relay protection method and system based on multi-core processor chip |
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