CN111914498A

CN111914498A - Time division multiplexing ADIO hardware implementation method of MCU external chip

Info

Publication number: CN111914498A
Application number: CN202010375645.9A
Authority: CN
Inventors: 王忆文; 任睿捷; 何旭东; 李南希
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2020-05-07
Filing date: 2020-05-07
Publication date: 2020-11-10

Abstract

The invention belongs to the field of integrated circuits, and particularly designs a circuit structure of ADIO based on time division multiplexing of a storage type chip interacting with an MCU. The invention discloses a time division multiplexing bus hardware circuit structure based on an MCU external storage chip, which comprises: a 16-bit data address bus; the decoding module is used for transmitting data address information of interaction between the chip and the MCU; the main storage module is used for receiving control signals and instructions transmitted to the interior of the chip by the MCU and generating internal control enabling signals at the same time; the slave storage module is used for storing data which are generated in the MCU operation process and need to be stored; the data protection module is used for storing programs required by the MCU in the using process and facilitating the reading of the MCU; for outputting the state judgment bit of the memory module in the programming state. The invention can provide a simplified bus design idea of the MCU external storage chip, reduces the pins of the chip by using a time division multiplexing method, reduces the chip area, has certain expandability and has the characteristic of reusability in a plurality of MCU external storage chips.

Description

Time division multiplexing ADIO hardware implementation method of MCU external chip

Technical Field

The invention belongs to the field of integrated circuits, and particularly relates to a time division multiplexing ADIO hardware circuit architecture design based on an MCU external interface storage chip.

Background

In the field of integrated circuit design, the main cost of a chip is composed of design cost and manufacturing cost, and the most fundamental factor determining the manufacturing cost is the chip area, and the smaller the chip area is, the manufacturing cost is greatly reduced, so that the multiplexing technology is a good method for designing the chip so as to reduce the chip area.

The microcontroller, also known as MCU, along with the continuous increase of demand, MCU's structure and function are also complicated gradually, and its peripheral circuit also becomes huge, in order to reduce the scale of peripheral circuit, need have a section to the external chip of storage of MCU, this chip has memory module, can be used for depositing MCU start-up procedure and operation in-process intermediate data to reduce the use of peripheral memory chip, conveniently interact with other chips simultaneously.

The MCU usually adopts a time division multiplexing address data bus, and in order to be better connected with the MCU, the MCU external interface chip also adopts the time division multiplexing address data bus, so that the time division multiplexing data address bus suitable for the MCU external interface chip is designed, and the realization of the normal read-write function of the MCU on the chip after the MCU is connected with the MCU becomes very important.

Disclosure of Invention

The invention aims to provide a method for realizing a time division multiplexing bus for an MCU external storage chip, which has the characteristics of improving the circuit performance and high reusability, and the technical scheme of the invention is as follows:

the output interface of each module needs signal lines provided by other modules to be as follows: the two signal lines are respectively used for enabling the main storage module and the auxiliary storage module and are provided by the decoding module, and only one enabling signal can be enabled at a high level at the same time. RD _ req, which is provided by the decode block as a read request signal line of the MCU. memory _ busy, which is provided by the data protection module as a busy state determination that any memory module is in an erase or write state. ALE, the signal is provided to the chip by the MCU and is used as an enabling signal of data input latch.

The method comprises the steps that judgment signals MMemory _ busy and SMemory _ busy for judging whether a storage module is in a busy state are respectively designed in two storage modules, the two enable signals are respectively in a high level when a main storage module or a slave storage module is in the busy state and in a low level when a memory _ busy signal is changed into the low level, the setting of the step is to avoid that another storage module is read when the main storage module or the slave storage module is in the busy state, and the enable signal of the storage module in the busy state is changed into the low level when the state is changed, so that the judgment of which storage module is in the busy state cannot be judged.

After the chip obtains the write-in command, namely the ALE signal becomes high level, the data is written into the corresponding storage module after passing through the decoding module. The following steps are taken to determine when the chip receives a read data command, as shown in fig. 1: if no storage module is busy, the read operation is directly carried out, if the storage module is busy, whether the corresponding storage module needs to be read is judged firstly, if yes, the data in the data protection module is output, and if not, the data in the corresponding module is output.

In the implementation example of the invention, the output scene of the data protection module is mainly judged by the following steps, wherein the first step is that the main storage module is busy and effective, the read request is effective and the main storage module is enabled to be effective; the second is that the slave memory module is busy and active, the read request is active and the slave memory module is enabled and active.

In an embodiment of the present invention, the main storage module output is controlled by an enable signal line, the main storage module is busy inactive and the read request is active, the main storage module is enabled active.

In an embodiment of the present invention, the slave memory module output is controlled by an enable signal line, the slave memory module is busy inactive and the read request is active, the slave memory module is enabled active.

Compared with the prior art, the invention has the advantages that the used control logic is less, the master storage module and the slave storage module can be separately controlled, the reusability is higher, and the time sequence is more optimized by using the combinational logic.

Drawings

FIG. 1 shows the determination steps required for reading data by a chip.

Fig. 2 is a truth table for the output port of the data protection module.

FIG. 3 is a timing diagram of a main memory module busy with a read request from the memory module.

Fig. 4 is a block diagram of the main module structure.

FIG. 5 is a general hardware interface circuit framework of a time division multiplexing bus suitable for an MCU external memory chip.

Detailed Description

The technical scheme in the embodiment of the invention is clearly and specifically described below with reference to the attached drawings of the specification:

fig. 1 is a general block diagram of an MCU external interface chip according to the present invention, which includes a decoding module, a data protection module, and a master/slave memory module.

Fig. 2 is a flowchart illustrating a basic judgment process that the MCU needs to pass after sending a read request to the chip when the chip is connected to the MCU, which is detailed as follows:

(1) the MCU reading request is sent to the chip, whether a storage module is in a busy state or not is judged at first grade, and if not, data corresponding to a corresponding address is found out through the decoding module and is output;

(2) if the memory module is in a busy state, entering the memory module needing to be read for judgment, and if the memory module needing to be read is not in the busy state, outputting the data;

(3) if the corresponding storage module is in a busy state, the internal part judges whether the state bit is finished, and simultaneously outputs the state bit in the data protection module as data until the internal corresponding storage module is finished in the busy state, and outputs the data of the corresponding address.

Fig. 3 is a timing diagram showing a main memory module in a busy state in a design, when a slave memory module is read, in order to avoid that it cannot be determined which memory module is busy due to mutual exclusion of mmemory _ en and smemory _ en, a flag bit is enabled by a memory _ busy signal and a program or erase signal received inside the memory module, indicating that the memory module is in the busy state, and a busy signal of the corresponding busy memory module is also changed to a low level until the memory _ busy signal is changed to a low level.

Fig. 4 is a quinary carnot diagram of the control output of the data protection module under the combined action of five signals.

Fig. 5 shows the hardware interface circuit framework suitable for the MCU external interface chip. Four modules are mounted in a 16-bit data address bus, and data input of the MCU is firstly latched by an ALE signal and latched into a decoding module. When data is output, the external ALE signal is latched firstly, and then the data is output by the data protection module, the main storage module or the auxiliary storage module after the judgment process, so that the purposes of time division multiplexing and normal read-write function are achieved.

Claims

1. The utility model provides a time division multiplexing ADIO circuit structure based on can regard as MCU external storage formula chip, its characterized in that has constructed a time division multiplexing's address data bus structure suitable for MCU external interface memory chip, time division multiplexing structure include: a 16-bit data address multiplexing bus; the decoding module is used for transmitting data address information of interaction between the chip and the MCU; the main storage module is used for receiving control signals and instructions transmitted by the MCU and generating internal control enabling signals at the same time; the slave storage module is used for storing data which are generated in the MCU operation process and need to be stored; the data protection module is used for storing programs required by the MCU in the using process and facilitating the reading of the MCU; the state judgment bit is used for outputting a state judgment bit of the storage module in a programming state; and the input and output interfaces of each module are connected to the bus.

2. The time division multiplexing ADIO circuit structure of an MCU external interface memory chip according to claim 1, wherein the 16-bit address data bus is used as a unique bus of the whole memory chip to transmit data and addresses simultaneously, the bus is connected with the decoding module, the main memory module, the auxiliary memory module and the data protection module simultaneously, the bus transmits the data sent by the MCU into the decoding module and transmits the data required to be sent into the MCU by the main memory module, the auxiliary memory module and the data protection module into the MCU.

3. The time division multiplexing ADIO circuit structure of storage chip with MCU external interface as claimed in claim 1, wherein the decoding module obtains the request data of MCU through 16-bit data address bus, and generates corresponding enable main storage module signal mmemory _ en, enable slave storage module signal smemory _ en, read enable request RD _ req, storage module request signal erase enable request erase _ en, write enable request wr _ en and the data to be written in the storage module.

4. The time-division multiplexing ADIO circuit structure of an MCU external interface memory chip as recited in claim 1, wherein the data protection module, the main memory module and the slave memory module have output interfaces connected to the bus, when any memory module is in a programming state or an erasing state, the memory module in the state is called a busy state, and a memory _ busy signal line in the data protection module will be changed to a high active state.

5. The time division multiplexing ADIO circuit structure of MCU external interface memory chip of claim 2, 3, 4 wherein the input data enters the chip through the input interface of the decoding module, the output data is controlled by the output interface circuit of the data protection module, the main memory module and the slave memory module together to achieve the following control objectives:

(1) if the storage modules are not in a busy state, directly outputting the data in the corresponding storage modules;

(2) if the memory module is in a busy state, making the following determination: if the data to be read is the data in the storage module in a busy state, the output ports of the master storage module and the slave storage module are not enabled, and the output in the data protection module is enabled and the output state bit is judged; if the data to be read is the storage module which is not in the busy state, enabling the output port of the corresponding storage module and outputting the corresponding data, and disabling the output ports of the other modules.