CN104050121B - Double receipts are double sends out programmable A RINC429 communication interface chip - Google Patents

Abstract

A kind of double receipts pair that the present invention proposes send out programmable A RINC429 communication interface chip, it is desirable to provide a kind of data transmission is soon, stable and reliable in work, have bigger versatility pair and receive double HT429 communication chip sent out.The technical scheme is that: controller CPU carries out data communication by two-way three-state data/address bus and three bit address lines with HT429 interface chip, controller CPU is controlled depositor, buffer occupancy state depositor, duty depositor and 4 data register by address above mentioned line and data wire be written and read operation to transmission controller, the reception of HT429 chip internal communications interface unit；The HT429 chip data to receiving carry out parity check sum volume label check, and satisfactory data input ARINC429 is received data storage；CPU carries out write operation to two ARINC429 transmission data memory FIFO respectively by the communications interface unit of HT429 chip to be completed to send to the data of two sendaisles, read data fifo and complete the data receiver of two passages, constitute double receipts pair and send out HT429 communication chip.

Description

Double receipts are double sends out programmable A RINC429 communication interface chip

Technical field

The present invention relates to a kind of a kind of ARINC429 interface being primarily adapted for use in aeroengine electronic controller a large amount of use Chip, particularly has the communication chip able to programme of multiple communication speed, can realize double ARINC of the double receipts of ARINC429 429 Communication specific ICs.

Background technology

Along with development and the appearance of microcomputer of digital technology, increasing avionic device has used Aeronautical data bus carries out communication.Wherein ARINC429 has become avionics system as a kind of digital carrier system and has led to The aircraft industry standard of news regulation.ARINC429 is to define avionic device and system and the one being in communication with each other each other Specification, is the technical standard being delivered and obtaining use by ARINC (United States radio technology company) in 1977 for 09 month. ARINC429 uses a kind of one-way data transfer standard.Avionics data bus is described as " open loop " and passes by ARINC429 technical standard Send pattern.This type bus is described as supporting the either simplex bus of multiple collector.A bus can only have a transmission Device, transmitter is constantly in transmission signal condition: or send 32 words, or spacing wave.And a bus is at least One receptor, can have up to 20.It is a pair unidirectional, differential coupling, twisted-pair shielded wire in ARINC429 bus. Signal voltage range on every line is between+5V to-5V.Article one, line is referred to as A (or+), and another line claims For B (or-).Pattern on circuit is bipolarity NRZ.Existing product respectively has spy to ARINC429 circuit form Point, interface has Based PC I, ISA, PC/104 and VXI, onboard processing device have for MCS-51, Intel80196, Intel80386, FPGA etc., function is various, uses complexity, also certainly will cause data communication board expensive.Use Although the design of FPGA field programmable gate array can simplify hardware designs, but development difficulty is big, the cycle is long. ARINC429 is a kind of one-way fashion broadcast type number bus, and the medium of transmission is made up of twisted-pair feeder, and essence belongs to serial communication model Farmland.System specifies on a pair transmission line, does not allow bi-directional transfer of data information, and modulation system uses bipolar return-to-zero system (BPRZ) Tri-state code mode, data are Transistor-Transistor Logic levels through two grades of differential driving, prime V+, V-when sending, and ARINC429 normally passes In the range of transmission of electricity is pressed in 10 ± 1V, and having dividing of generating positive and negative voltage, signal level range can characterize 3 states, logic Level"1" voltage 7.25:11V (between A B), logical zero level voltage-7.25:-11V (between AB), empty shape State level voltage-0.5:0.5V (between AB), when transmitting data continuously, at least inserts an empty shape between every 32 words State is isolated, and bus data transfer order is 1,2,3,4,5,6,7,8,9,10,11,12,13 ... 32. ARINC429 bus interface card major function is to play function served as bridge between ARINC429 bus and pci bus, it is achieved The reception of 429 bus data information and transmission.Presently commercially available ARINC429 interface chip transmitter based on FPGA and ARINC429 Bus Interface Chip special chip is double single-shot special chips of receiving mostly, and single reception frequency acquisition sends FIFO memory only has 8 32 words, does not receive FIFO, does not receive data tag and filters audit function.It is at present Meet double communication needs of double receipts, aviation ARINC429 communication commonly used FPGA, DSP and high speed submersible processor etc. Realizing, these implementations need software and hardware technology complex, and power consumption is relatively big, and versatility is poor.

Summary of the invention

It is an object of the invention to the weak point existed for prior art, it is provided that a kind of data transmission is fast, and working stability can Lean on, it is possible to reduce use ARINC429 communication chip and peripheral circuit, alleviate programming and require and difficulty have the most general Property, especially it is capable of the double HT429 Communication specific IC receiving double of engine electronic control ARINC429.

The above-mentioned purpose of the present invention can be reached by following measures.A kind of double receipts are double sends out the communications of programmable A RINC429 Interface chip, includes two communications interface units carrying out communication with controller CPU, it is characterised in that: two are in parallel ARINC429 receives unit and the serial data received is converted to parallel data, by parity check sum volume label check unit pair The complete data of each reception channel reception carry out parity check sum volume label check, undesirable data are abandoned, conform to The data input ARINC429 asked receives data memory FIFO, the controller CPU communication interface by HT429 chip Unit reads the data receiving data memory FIFO；The communications interface unit of the HT429 chip data to there being 8 addresses Space, three bit address line AD1～AD3, the two-way three-state data/address bus D0 of this communications interface unit and controller CPU～ D15 is connected transmission of control signals, response signal and reset RST clock, and controller CPU is to HT429 chip communication interface list The transmission of unit controls depositor, reception controls depositor, relief area seizure condition depositor and duty depositor and is written and read Operation, completes the Initialize installation to HT429 chip and status poll；Controller CPU is connect by the communication of HT429 chip Mouth unit sends data memory FIFO to two ARINC429 respectively and carries out write operation, completes the number to two sendaisles According to transmission；Controller CPU reads 1 reception data of HT429 chip internal by the communications interface unit of HT429 chip Memorizer data fifo completes the data receiver of two passages, thus constitutes double HT429 communication chip receiving double.

The present invention has the advantages that compared to prior art.

HT429 chip of the present invention is to fully meet double ARINC429 interface chip receiving double, is encapsulated as JLCC44, Applicable temperature scope is-55 DEG C-125 DEG C, and operating voltage range is 4.5V-5.5V.Can simultaneously and outside two dresses by this chip Put and realize duplex data communication, use chip of the present invention can reduce use ARINC429 communication chip and peripheral circuit, fall The work load of low controller CPU.

The present invention carries out parity check sum volume label check, undesirable number to the data that each reception channel reception is complete According to abandoning, satisfactory data enter and receive data buffer FIFO, thus significantly reduce controller CPU communication Interface unit is born, and alleviates requirement and the difficulty of programming.

The present invention uses to be had the transmission of larger capacity and receives Data Buffer Memory FIFO, engine electronic control CPU can disposably send or receive the data of multiple word the short time, and remaining task is just automatically performed by HT429 chip and sends out Send or reception task.Thus HT429 chip has when communication sends data that to take controller CPU time short, when receiving data There is the bigger slack time to wait controller CPU process, data will not be lost because CPU task is heavy.

HT429 chip of the present invention can arbitrarily arrange transmission or receive communication speed communication, this chip each channel communications speed Can arbitrarily be set to one of 1M, 100K, 12.5K tri-kinds, two sendaisle communication speeds of two transmitting elements can not Unanimously, such chip of the present invention can realize the device of communication speed different from two flexibly and carries out duplex signaling.

HT429 chip of the present invention is the ARINC429 communication chip with PLC technology, three bit address lines of this chip Constitute the address space of 8 16 bit data.Electronic controller CPU is written and read operation to chip address space can complete two Individual passage send and receive data, additionally can read and write reception label data, send control depositor, receive control deposit Device, relief area seizure condition depositor, duty depositor etc., the operation to these depositors can be with flexible configuration chip Function so that this chip has bigger versatility.

This chip initiation arranges and is simply easily programmed, and takies cpu resource less during work.Through substantial amounts of reality Work is observed, and this chip operation is reliable and stable, is completely suitable for air communications field.

HT429 interface chip perfect in shape and function of the present invention, excellent performance, flexible and convenient to use, control simple and reliable, energy side Just communicate with various CPU.Arrange by the setting of internal control registers being easily accomplished chip, CPU is led to The programming of letter interface unit requires simple, does not has calculating and the setting of complexity.The peripheral circuit using this chip is also that comparison is simple Single, peripheral components is few, and pin package is suitable, arranges that pcb board is easier to.HT429 running voltage is at about 5V, chip Power consumption is relatively low, occurs without fever phenomenon, and chip capacity of resisting disturbance is strong, has no any fault at present, lead to for aviation field in work News technology provides the selection that reliability is higher.

Accompanying drawing explanation

The present invention is further described with embodiment below in conjunction with the accompanying drawings.

Fig. 1 is that double receipts of the present invention double sends out communication interface chip HT429 circuit theory schematic diagram able to programme.

Fig. 2 is the schematic diagram of HT429 chip communication interface unit in Fig. 1.

Fig. 3 is that in Fig. 1, HT429 chip receives and sends the waveform diagram of communication data.

Fig. 4 is HT429 chip and pin schematic diagram thereof.

Detailed description of the invention

The most double receipts are double, and to send out communication interface chip HT429 able to programme be the ARINC429 communication with PLC technology Chip.HT429 chip internal have two receive unit, two transmitting elements, parity check sum volume label check unit, one Individual communications interface unit, 64 × 16bit label data cell, one 32 × 32 receive data FIFO, two 16 × 32bit sends data FIFO.Controller CPU by two-way three-state data/address bus D0～D15 and three bit address line AD1～ The communications interface unit of AD3 Yu HT429 chip carries out data communication, and HT429 chip has the data space of 8 addresses, control The transmission of HT429 chip is controlled to deposit by device CPU processed by three bit address lines, 16 BDB Bi-directional Data Bus and control bus Device, receive control depositor, relief area seizure condition depositor and duty depositor are written and read operation and complete initialization and set Put and read with state；The serial data of reception is converted to parallel data by two of HT429 chip reception unit, then by The parity check sum volume label check unit of HT429 chip carries out parity check sum label to the data that each reception channel reception is complete Checking, undesirable data being abandoned, satisfactory data are input to the reception data storage of HT429 chip It is complete that FIFO, controller CPU carry out read operation by the communications interface unit of HT429 chip to reception data memory FIFO Become to receive data；Controller CPU sends number by the communications interface unit of HT429 chip to two ARINC429 in parallel Carrying out write operation according to memorizer FIFO, two transmitting elements of HT429 chip are respectively from two transmission data buffer FIFO Read data parallel series and be sent to external drive chip, complete data and send, thus constitute the double HT429 communication core sent out of double receipts Sheet.

HT429 chip has two independent reception unit, and outside three level datas are turned by chips such as other similar HI-8588 It is changed to COMS digital signal level.HT429 chip receives unit and constantly input signal pin is carried out level detection, when sending out Judging during available data whether data pulse persistent period and interval meet the requirements, the data meeted the requirements just carry out shifting processing, Judge whether when having received 32 bit data to receive, whether meet the requirements with next 32 word spaces, only data The data that bit duration, data bit interval, reception figure place, word interval all meet just enter HT429 label and odd even school Test.

HT429 chip is communicated with controller CPU by its communications interface unit, and two receive the string that unit will receive Row data are converted to parallel data, send reception data buffer FIFO after parity check sum volume label check；Two send single Unit reads data parallel series from two transmission data buffer FIFO respectively and is sent to external drive chip.Controller CPU passes through The data register 1 of HT429 chip and the read operation of data register 2 are read the number receiving data buffer FIFO According to, thus complete to receive the reading of data；Controller CPU is by data register 1 to the data register to HT429 chip The write operation of device 4 writes data to two transmission buffer FIFO, thus completes to send the write of data.

In HT429 interface chip communications interface unit shown in Fig. 2 register address be 0 be send control depositor, Address be 1 be receive control depositor, address be 2 be that data buffer zone FIFO takies situation depositor, address is 3 Being state warning information depositor, address is 4 to be data register 1, address be 5 be data register 2, address is 6 Be data register 3, address be 7 be data register 4.AD1～AD3 is three three from controller CPU Address wire, D0～D15 is that interface chip communicates with controller CPU two-way three-state data/address bus when carrying out data communication.CS For selecting control signal from the sheet of controller CPU.

Controller CPU controls depositor, reception control depositor, relief area by HT429 communications interface unit to sending Seizure condition depositor and duty depositor are written and read operation.HT429 chip parity check sum label detector unit is to two The complete data of individual reception channel reception carry out parity check sum volume label check, undesirable data are abandoned, meet the requirements Data input receive data memory FIFO.Controller CPU is posted by the data of the communications interface unit of HT429 chip Storage 1 and data register 2 read the data receiving data memory FIFO.Controller CPU is also by HT429 chip The data register 1 of communications interface unit～data register 4 be respectively written into data to two and send Data Data memorizer FIFO, two transmitting elements read data from sending data FIFO and send each word by turn according to waveform format shown in Fig. 3 32 bit data, thus constitute double HT429 communication chip receiving double.

The sequential that controller CPU writes data to chip by HT429 chip communication interface unit is: first controller Data are dealt in 16 bit data bus by CPU, and after a clock, output enable signal OE is uprised, then by controller CPU Then address AD 1～AD3 data being dealt in address wire after two clocks, read-write RW is set by controller CPU simultaneously Being set to low level, chip selection signal CS is set to low level, and then HT429 chip reads the number on D0～D15 data/address bus According to, answer signal DSACK is set to low level after completing operation by HT429 interface chip, controller after 1～2 clock Chip selection signal CS is set to high level by CPU, and answer signal DSACK is set to high level by HT429 chip simultaneously, after After 1～2 clock, read-write RW is set high level by controller CPU, cancels AD1～AD3 address, enables signal OE Signal step-down level, cancels the data in 16 bit data bus, this completes controller CPU and passes through communications interface unit Write data to the process of HT429 chip.

Reading the data sequential to controller CPU from HT429 chip, controller CPU will read HT429 chip data Address signal be put into three bit address line AD1～AD3, chip selection signal CS and enable signal OE set low level simultaneously, read-write Signal RW sets high level, and then HT429 chip internal starts the communicating requirement of processing controller CPU, correct data It is put on D0～D15 data/address bus, and chip DSACK is set to low level, when controller CPU detects HT429 core The data on readout data bus are just started, typically at answer signal during the trailing edge of answer signal DSACK of sheet output After DSACK trailing edge, 1～2 clock controller CPU reading data is complete, and then controller CPU by CS and enables letter Number OE sets high level, and answer signal DSACK is set high level by HT429 chip simultaneously, controller after a clock Read-write RW is set low level by CPU, cancels the operation address on address bus, this completes controller CPU and pass through Communications interface unit reads the process of data from HT429 chip.

When the initialization of HT429 chip, first the relief area of HT429 chip is taken situation and deposits by controller CPU Device is 0x0000, is received by reset HT429 chip internal and send relief area after performing this instruction, and HT429 chip internal is read The pointer writing label data is reset to 0, and then controller CPU arranges HT429 chip and sends control depositor is 0x0010, And write the volume label check data data register 1 to HT429 chip communication interface unit the most successively, it is ultimately written data 0xff00 represents writing volume label and checks ED.After label data write interface chip, and then controller CPU is arranged It is 0x0000 that HT429 chip relief area takies situation depositor, and then controller CPU arranges transmission control depositor and reception Control the configuration data of depositor, this completes the Initialize installation of HT429 chip.

Control depositor when controller CPU completes to send HT429 chip and receive after control depositor is arranged the most permissible Start to send communication data to peripheral control unit.First read HT429 chip relief area before controller CPU transmission often group data to account for Data with situation depositor, it is judged that send and receive buffer data how many；Then controller CPU read work state is posted The data of storage, it is judged that whether it has warning information, when its read work status data is 0x0000, represent the most any Warning information, then controller CPU write data 0x0000 alert depositor to state, and reset all of state warning information.

Controller CPU to HT429 chip sendaisle 1 report data time, first write low 16 bit data to HT429 Chip data depositor 1, then writes high 16 bit data to data register 2, so completes to write one and completes 32 words and arrive HT429 chip sendaisle 1, repeats above operation controller CPU and just can send multiple 32 digital data to HT429 core Sheet sendaisle 1.Same controller CPU to HT429 chip sendaisle 2 report data time, first write low 16 figure places According to HT429 chip data depositor 3, then write high 16 bit data and complete to data register 4, such controller CPU Write one and complete 32 words to HT429 chip sendaisle 2, repeat above operation just can send multiple 32 digital data to HT429 chip sendaisle 2.It is not make even-odd check that controller CPU write enters the data of HT429 chip, and data are sent After entering HT429 chip, when sending data, interface chip has the most all made even-odd check, and then HT429 chip is according to figure Form shown in 3 waveforms transmits data to outside similar HI-8585 communication driving chip.

When controller CPU receives communication data, first read and judge that HT429 chip internal relief area takies situation and deposits Device, high 7 displays of this register data have how many data in receiving FIFO, and then controller CPU reads inside HT429 The data that duty depositor preserves, and write data 0x0000 to HT429 chip operation state storage, empty work shape The warning information of state depositor.Controller CPU takies the number of situation depositor video data according to HT429 chip relief area Read reception buffer data.HT429 chip has done parity check and volume label data check automatically when receiving data, Every parity check sum underproof data of label data check are all abandoned, and parity check sum volume label check is underproof accordingly Warning information can show in state alarm depositor.

HT429 chip receives the reception data of passage 1 and reception passage 2 and delivers to HT429 chip internal odd even school respectively Testing and volume label check unit, the data through passed examination have all delivered to same reception data FIFO, and controller CPU reads When HT429 chip receives communication data, first read low 16 bit data of HT429 chip data depositor 1, then read High 16 bit data of data register 2, such controller CPU completes to read complete 32 words, repeats above operation Controller CPU just can read multiple 32 words and receive communication data.

For guaranteeing that CPU communications interface unit controls program and has time enough to process other task, HT429 interface chip is gathered around Having bigger data buffer zone, the size receiving data buffer FIFO is 32 words, and each passage sends data buffer The size of FIFO is 16 words, and the RAM preserving label data is 64 16bit words.

Refering to shown in Fig. 4, HT429 chip has 4 input pins, 4 output pins, and its input-output wave shape is shown in figure Shown in 3, input pin IN1A, IN1B, IN2A, IN2B receive integrated circuit HT-8588 from peripheral ARINC429 Deng chip, output pin OUT1A, OUT1B, OUT2A, OUT2B drive integrated for output to peripheral ARINC429 The chips such as circuit HI-8585.HT429 chip have 16 bidirectional data pin D0～D15,3 bit address pin AD1～ AD3, a chip select input pin CS, a read-write input pin RW, an output enable input pin OE, one 10M clock input pin CLK, an operation completes response output pin DSACK, an interrupt response output pin IRQ.Chip select input pin CS is to show during low level that controller CPU chooses this interface chip, HT429 chip and controller CPU just has data to exchange, and during HT429 chip free time, chip select pin CS is in high level state, and chip D0～D15 is external For high-impedance state.RST is reseting input signal, the HT429 chip reset when it is low level.RW is from controller The read-write of CPU, is write data when it is for low level, is to read data during for high level.OE enables letter for output Number, when enabling signal OE and being high level, ARINC429 interface chip receives D0～the D15 data of controller CPU, when Enable HT429 chip when signal OE is low level and export data to data bus D0～D15 to controller CPU. DSACK is that HT429 chip completes to export after controller CPU operates accordingly to the signal of CPU, represents HT429 core Sheet has operated.DSACK pin is high level usually, when CS chooses interface chip, after interface chip built-in function completes Being set to low level, controller CPU is once detect that its trailing edge just carries out lower step work.DSACK pulse width is general It is 1 10MHZ clock cycle, if controller CPU does not check this signal and will wait and stay always, Bu Huijin Row next-step operation.10MCLK is the operating clock signals of HT429 chip, and its frequency is 10MHZ.

Above-described is only the preferred embodiments of the present invention.It should be pointed out that, those of ordinary skill in the art is come Saying, under the premise without departing from the principles of the invention, it is also possible to make some deformation and improvement, these alterations and modifications should be regarded as belonging to In protection scope of the present invention.

Claims (10)

1. double receipts are double sends out programmable A RINC429 communication interface chips, includes two and carries out communication with controller CPU Communications interface unit and double receipts double send out communication interface chip HT429 able to programme, and HT429 chip has PLC technology ARINC429 communication chip, this HT429 chip internal has two to receive unit, two transmitting elements, parity check sum volumes Mark inspection unit, communications interface unit, 64 × 16bit label data cell, one 32 × 32 receive data FIFO, Two 16 × 32bit send data FIFO, it is characterised in that: two ARINC429 in parallel receive the serial that unit will receive Data are converted to parallel data, are carried out, by parity check sum volume label check unit, the data that each reception channel reception is complete Undesirable data are abandoned by parity check sum volume label check, and satisfactory data input ARINC429 receives data Memorizer FIFO, controller CPU read the data receiving data memory FIFO by the communications interface unit of HT429 chip； The communications interface unit of HT429 chip to there being the data space of 8 addresses, this communications interface unit and the three of controller CPU Bit address line AD1～AD3, two-way three-state data/address bus D0～D15 are connected transmission of control signals, response signal and during reset RST Clock, controller CPU controls depositor to the transmission of HT429 chip communication interface unit, reception controls depositor, relief area takies Status register and duty depositor are written and read operation, complete the Initialize installation to HT429 chip and status poll； Controller CPU sends data memory FIFO to two ARINC429 respectively by the communications interface unit of HT429 chip to be carried out Write operation, completes to send to the data of two sendaisles；Controller CPU is read by the communications interface unit of HT429 chip 1 reception data memory FIFO data of HT429 chip internal complete the data receiver of two passages, thus constitute double receipts The HT429 communication chip of double.

2. double receipts as claimed in claim 1 are double sends out programmable A RINC429 communication interface chips, it is characterised in that: HT429 core Sheet has two independent reception unit, and outside three level datas are converted to COMS digital signal level by HI-8588 chip； HT429 chip receives unit and constantly input signal pin is carried out level detection, judges that when being found to have data data pulse is held Whether continuous time and interval meet the requirements, and the data meeted the requirements just carry out shifting processing, judge when having received 32 bit data Whether receive, whether meet the requirements with next 32 word spaces, only the data bit persistent period, data bit interval, The data that reception figure place, word interval all meet just enter HT429 label and parity check unit.

3. double receipts as claimed in claim 1 are double sends out programmable A RINC429 communication interface chips, it is characterised in that: three bit address Line constitutes the address space of 8 16 bit data.

4. double receipts as claimed in claim 1 are double sends out programmable A RINC429 communication interface chips, it is characterised in that: controller CPU transmits data in 16 bit data bus, and after a clock, controller CPU will enable signal OE output and enable signal change Height, then after two clocks, address AD 1～AD3 data are dealt in address wire by controller CPU simultaneously, and controller CPU will read and write Signal RW is set to low level, and sheet selects control signal CS to be set to low level, and HT429 chip internal operates, and completes operation After chip DSACK is set to low level, after 1～2 clock, chip selection signal CS is set to high level by controller CPU, HT429 simultaneously Its DSACK is set to high level by chip, then read-write RW is set high level by controller CPU after 1～2 clock, cancels AD1～AD3 address, enables signal OE signal step-down level, cancels the data in 16 bit data bus, thus complete controller CPU write enters the data process to HT429 chip.

5. double receipts as claimed in claim 1 are double sends out programmable A RINC429 communication interface chips, it is characterised in that: controller Reading address signal is put into three bit address line AD1～AD3, CS by CPU and enable signal OE sets low level, read-write RW simultaneously Setting high level, then HT429 chip internal starts the requirement of processing controller CPU, and correct data are put on data/address bus, DSACK is set to low level simultaneously, when controller CPU detects the trailing edge of the DSACK of HT429 chip, starts to read number According to the data in bus, after a clock, CS and enable signal OE is set high level by controller CPU, and HT429 chip is simultaneously by it DSACK is set to high level, and after a clock, read-write RW is set low level by CPU communications interface unit, cancels address total Operation address on line, thus completes controller CPU and reads the process of HT429 chip data.

6. double receipts as claimed in claim 1 are double sends out programmable A RINC429 communication interface chips, it is characterised in that: at interface core In the initialization procedure of sheet, when initializing HT 429 chip, first controller CPU arranges HT429 chip communication interface unit and delays Rushing district and taking the data of situation depositor is 0x0000, and reset its internal receipt and send relief area, and read-write label pointer resets Being 0, the data then arranging transmission control depositor are 0x0010, write volume label check data the most successively to HT429 chip-count According to depositor 1, it is ultimately written data 0xff00 and represents writing volume label inspection ED.

7. double receipts as claimed in claim 1 are double sends out programmable A RINC429 communication interface chips, it is characterised in that: controller CPU sends or first reads HT429 chip relief area before reception often group data and takies the data of situation depositor, it is judged that sends and connects Receive buffer data size, controller CPU just according to this register data it is determined that transmission or receive how many data；Then control Device CPU processed reads the data of HT429 chip operation status register again, interpretation its whether have warning information, when its number read According to during for 0x0000, represent and there is no any warning information, then will write data 0x0000 and alert depositor to state, reset all State warning information.

8. double receipts as claimed in claim 1 are double sends out programmable A RINC429 communication interface chips, it is characterised in that: controller CPU to HT429 chip sendaisle 1 report data time, first write low 16 bit data to HT429 interface chip data register 1, then write high 16 bit data to data register 2, complete to write one and complete 32 words to HT429 interface chip passage 1, repeat More than operate and sent multiple digital data to HT429 chip sendaisle 1.

9. double receipts as claimed in claim 1 are double sends out programmable A RINC429 communication interface chips, it is characterised in that: controller CPU to HT429 chip sendaisle 2 report data time, first write low 16 bit data to HT429 interface chip data register 3, then write high 16 bit data to data register 4, complete to write one and complete 32 words to HT429 interface chip passage 2, repeat More than operate and sent multiple digital data to HT429 chip sendaisle 2.

10. double receipts as claimed in claim 1 are double sends out programmable A RINC429 communication interface chips, it is characterised in that: CPU communicates When interface unit receives data, first read and judge that HT429 chip relief area takies situation depositor, high 7 displays of these data Having how many data in receiving FIFO, then read the data of HT429 chip operation status register, write data 0x0000 are to shape State alarm depositor, the warning information of empty alarm depositor；Controller CPU takies feelings according to HT429 chip relief area The number of condition depositor video data reads reception buffer data；HT429 chip has done odd even school when receiving data automatically Testing inspection and label data check, the data through passed examination have all delivered to HT429 chip internal same reception data FIFO, every parity check sum underproof data of label data check are all abandoned, and parity check sum volume label check does not conforms to The corresponding warning information of lattice can show in state alarm depositor；Controller CPU reads and first reads when receiving data Low 16 bit data of HT429 chip data depositor 1, then high 16 bit data of read data register 2, such controller CPU completes to read complete 32 words, repeats above operation controller CPU and just can read the reception communication number of multiple word According to.