KR101166820B1 - A shift register - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register, and more particularly, to a shift register embedded in a liquid crystal panel capable of outputting a scan pulse having a specific waveform.

LCD, Shift Register, Scan Pulse, Distortion

Description

A shift register

1 is a view showing a conventional shift register

2 is a view showing a liquid crystal panel to which a shift register is applied according to an embodiment of the present invention;

3 is a timing diagram of signals supplied to a gate line and a data line of FIG.

4 illustrates a shift register according to a first embodiment of the present invention.

5 is a timing diagram of a scan pulse output from each stage of FIG. 4 and a signal supplied to each stage.

6 is a circuit diagram illustrating a third stage of FIG. 4.

7 is a view showing first to third stages having the circuit configuration of FIG.

8 illustrates a shift register according to a second embodiment of the present invention.

FIG. 9A is a timing diagram of scan pulses output from the stage of FIG. 8 during odd-numbered frames, and various signals supplied to the stages. FIG.

FIG. 9B is a timing diagram of scan pulses output from the stage of FIG. 8 during even-numbered frames, and various signals supplied to the stages; FIG.

FIG. 10 is a circuit diagram illustrating the third stage of FIG. 8.

FIG. 11 is a view showing first to third stages having the circuit configuration of FIG. 10. FIG.

12 is another circuit diagram of the third stage of FIG.

FIG. 13 is yet another circuit diagram of the third stage of FIG. 8.

* Explanation of symbols on the main parts of the drawings

BST1 to BSTn: first to nth stage BSTn + 1: first dummy stage

BSTn + 2: second dummy stage VDD: first voltage source

VSS: second voltage source Vout1 to Voutn + 2: first to n + 2 scan pulses

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register of a liquid crystal display, and more particularly, to a shift register embedded in a liquid crystal panel capable of outputting a scan pulse having a specific waveform.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged in an intersecting manner, and a pixel region is located in an area defined by vertically intersecting the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed on the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source electrode and a drain electrode of a thin film transistor (TFT) which is a switching element. The thin film transistor is turned on by a scan pulse applied to the gate electrode via the gate line, so that the data signal of the data line is charged to the pixel voltage.

The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying a control signal for controlling the gate driver and the data driver, And a power supply unit for supplying various driving voltages used in the plasma display apparatus.

The timing controller controls the driving timings of the gate driver and the data driver and supplies a pixel data signal to the data driver. The power supply unit boosts or depressurizes the input power source to generate driving voltages such as a common voltage VCOM, a gate high voltage signal VGH, and a gate low voltage signal VGL required by the liquid crystal display device. The gate driver sequentially supplies scan pulses to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a pixel voltage signal to each of the data lines whenever a scan pulse is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

Here, the liquid crystal panel will be described in more detail.

1 is a diagram illustrating a conventional liquid crystal panel, and FIG. 2 is a timing diagram of signals supplied to a gate line and a data line of FIG. 1.

As shown in FIG. 1, the liquid crystal panel includes a plurality of gate lines GL1, GL2, GL3, GL4,... And a plurality of data lines DL1, DL2,... It has a plurality of pixels defined by. Each pixel has a pixel electrode for displaying an image.

Pixel columns arranged on both sides with reference to an arbitrary data line DL1 are commonly supplied with a data signal from the data line DL1. That is, a pixel column (hereinafter, referred to as a first pixel column) arranged on the left side of the data line DL1 and a pixel column (hereinafter, referred to as a second pixel column) arranged on the right side of the data line DL1 will be described. The data signal from the one data line DL1 is commonly supplied.

Here, any one pixel on the first pixel column is referred to as a first pixel 200a, and one pixel on a second pixel column symmetrically positioned with respect to the first pixel 200a and the data line DL1. Let's define the pixel as the second pixel 200b. Then, the first pixel 200a and the second pixel 200b are repeatedly positioned in each pixel row. If the first pixel 200a and the second pixel 200b are defined as one group 200, each group 200 is positioned between the first pixel 200a and the second pixel 200b. You will have one data line. Meanwhile, no data line exists between the groups 200.

Each group 200 includes first to third switching elements M1 to M3.

The first and second switching devices M1 and M2 are devices for driving the first pixel 200a, and the third switching device M3 is a device for driving the second pixel 200b. .

That is, the first switching device M1 supplies the scan pulse applied to the next gate line to the gate terminal of the second switching device M2 in response to the scan pulse applied to the current gate line. As a result, the second switching device M2 is turned on, and the turned-on second switching device M2 supplies the data signal from the data line to the first pixel 200a. In detail, the second switching device M2 supplies the data signal to the pixel electrode provided in the first pixel 200a.

The third switching device M3 supplies the data signal from the data line to the second pixel 200b in response to the scan pulse applied to the current gate line.

Meanwhile, as shown in FIG. 2, scan pulses are sequentially supplied to the gate lines GL1 to GL4. Each of the scan pulses Vout1 to Vout4 includes first and second impulses PL1 and PL2 having different pulse widths. The pulse width of the second impulse PL2 is about twice as large as the pulse width of the first impulse PL1. In addition, the second impulse PL2 is output later than the first impulse PL1. Specifically, the second impulse PL2 is output after the first impulse PL1 is output and a predetermined time has elapsed.

Each scan pulse Vout1 to Vout4 configured as described above is sequentially supplied to the gate lines GL1 to GL4, wherein the scan pulses supplied to the current gate line are the scan pulses of the previous gate line and the next gate line. The scan pulse is overlapped with a predetermined section. Specifically, the first impulse PL1 of the scan pulse supplied to the current gate line overlaps the second impulse PL2 of the scan pulse supplied to the previous gate line. The second impulse PL2 of the scan pulse supplied to the current gate line overlaps the first impulse PL1 of the scan pulse supplied to the next gate line. At this time, the rising time of the first impulse PL1 and the rising time of the second impulse PL2 are equal to each other, and the polling time of the first impulse PL1 coincides with the polling time of the second impulse PL2. I never do that. That is, the polling time of the first impulse PL1 is faster than the polling time of the second impulse PL2. Therefore, the first impulse PL1 is output at the same time as the second impulse PL2, but is polled at a time corresponding to about half the pulse width of the second impulse PL2.

The operation of the first to third switching devices M1 to M3 configured as described above will be described in detail as follows.

First, as shown in FIG. 3, the first to fourth scan pulses Vout1 to Vout4 are sequentially output, and are sequentially supplied to the first to fourth gate lines GL1 to GL4.

At this time, in the first period T1, both the second impulse PL2 of the second scan pulse Vout4 and the first impulse PL1 of the third scan pulse Vout3 are kept high. Therefore, the second gate line GL2 and the third gate line GL3 are driven at the same time. In other words, in the first period T1 in which the second impulse PL2 of the second scan pulse Vout2 and the first impulse PL1 of the third scan pulse Vout3 overlap, , And the third switching elements M1, M2, M3 are all turned on. Then, the data signal supplied to the first data line DL1 is supplied to the pixel electrode A1 of the first pixel 200a through the turned-on second switching element M2. In addition, the data signal is also supplied to the pixel electrode B1 of the second pixel 200b through the turned-on third switching element M3. As a result, in the first period T1, the pixel electrode A1 of the first pixel 200a and the pixel electrode of the second pixel 200b disposed between the first gate line GL1 and the second gate line GL2. The data signal is simultaneously supplied to B1). The signal supplied to the data line DL1 in the first period T1 is a data signal corresponding to the first pixel 200a.

In the second period T2, only the second impulse PL2 of the second scan pulse Vout2 remains high. Therefore, only the second gate line GL2 is driven in the second period T2. In other words, in the second period T2, only the third switching device M3 connected to the second gate line GL2 is turned on. Therefore, the data signal from the data line DL1 is supplied only to the pixel electrode of the second pixel 200b. As a result, in the second period T2, the data signal is supplied to the pixel electrode B1 of the second pixel 200b positioned between the first gate line GL1 and the second gate line GL2. The signal supplied to the data line DL1 in the second period T2 is a data signal corresponding to the second pixel 200b.

As described above, in the first period T1, the first pixel 200a and the second pixel 200b are activated so that the first pixel 200a and the second pixel 200b simultaneously receive data signals (the first pixel 200a). ) Is supplied, but only in the second period T2, only the second pixel 200b is activated so that only the second pixel 200b corresponds to the data signal (second pixel 200b). Data signal). In this case, the data signal of the first period T1 and the data signal of the second period T2 are supplied at a time difference through one data line DL1.

On the other hand, conventionally, a shift register provided on the outside of the liquid crystal panel in order to output the scan pulse of the unusual shape as described above was used. Therefore, there is a problem that the overall size of the liquid crystal display device is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and by embedding each stage provided in the shift register on a liquid crystal panel, it is possible to reduce the size of the liquid crystal display device and to output scan pulses having a specific waveform. The purpose is to provide a shift register.

The shift register according to the present invention for achieving the above object, a plurality of clock pulses sequentially output so as to overlap a predetermined interval with different phases, the scan pulse from the previous stage, and the scan pulse from the next stage In response to the shift register having a plurality of stages for outputting a scan pulse, each stage is embedded on the liquid crystal panel, and in response to the start pulse or the scan pulse from the previous stage, the first node is connected to the second node. A first switching device for charging with a voltage source; A second switching element for discharging a second node to a first voltage source in response to the start pulse or a scan pulse from a previous stage; A third switching device configured to charge the second node with a second voltage source in response to a first clock pulse or a charging pulse synchronized with the scan pulse output from the next stage; A fourth switching element configured to discharge the first node to a first voltage source in response to a second voltage source charged in the second node; A fifth switching device configured to discharge the second node to the first voltage source in response to the second voltage source charged in the first node; A sixth switching element which discharges the first node to a first voltage source in response to a scan pulse from a next stage; A seventh switching element configured to output, as a scan pulse, a second clock pulse output before the first clock pulse in response to a second voltage source charged in the first node; And an eighth switching device configured to output the first voltage source in response to the second voltage source charged in the second node.

In addition, the shift register according to the present invention for achieving the above object, a plurality of clock pulses sequentially output to have a different phase and overlap a predetermined interval, a plurality of charge pulses sequentially output different phases A shift register having a plurality of stages for outputting scan pulses in response to a scan pulse from a previous stage and a scan pulse from a next stage, wherein each stage is embedded on a liquid crystal panel, A first switching element for charging the first node with a second voltage source in response to a scan pulse from the stage; A second switching element for discharging a second node to a first voltage source in response to the start pulse or a scan pulse from a previous stage; A third switching device configured to charge the second node with a second voltage source in response to a charging pulse; A fourth switching element configured to discharge the first node to a first voltage source in response to a second voltage source charged in the second node; A fifth switching device configured to discharge the second node to the first voltage source in response to the second voltage source charged in the first node; A sixth switching element which discharges the first node to a first voltage source in response to a scan pulse from a next stage; A seventh switching element configured to output, as a scan pulse, a second clock pulse output before the first clock pulse in response to a second voltage source charged in the first node; And an eighth switching device configured to output the first voltage source in response to the second voltage source charged in the second node.

In addition, the shift register according to the present invention for achieving the above object, a plurality of clock pulses sequentially output to have a different phase and overlap a predetermined interval, the scan pulse from the previous stage, and from the next stage A shift register having a plurality of stages for outputting scan pulses in response to the scan pulses, wherein each stage is embedded on the liquid crystal panel, and the first node is connected in response to a start pulse or a scan pulse from a previous stage. A first switching device for charging with a second voltage source; A second switching element for discharging a second node to a first voltage source in response to a start pulse or a scan pulse from a previous stage; A third switching element for discharging the third node to the first voltage source in response to a start pulse or a scan pulse from a previous stage; A fourth switching element which is turned on or turned off in response to a third voltage source having a different polarity for each frame, and charges the second node with a third voltage source at turn-on; A fifth switching element that is turned on or off in response to the third voltage source and discharges the third node to the first voltage source when turned on; A sixth switching element turned on or off in response to a fourth voltage source having a polarity opposite to that of the third voltage source and charging the third node with the fourth voltage source at turn-on; A seventh switching element turned on or off in response to the fourth voltage source and discharging the second node to the first voltage source when turned on; An eighth switching element for discharging the second node to the first voltage source in response to the second voltage source charged to the first node; A ninth switching element configured to discharge the third node to the first voltage source in response to the second voltage source charged to the first node; A tenth switching element configured to discharge the first node to the first voltage source in response to the third voltage source charged in the second node; An eleventh switching element discharging the first node to the first voltage source in response to the fourth voltage source charged to the third node; A twelfth switching element for discharging the first node to the first voltage source in response to the scan pulse from the next stage; A thirteenth switching element configured to output a scan pulse in response to a second voltage source charged in the first node and to supply the scan pulse to the gate line, the next stage, and the previous stage; A fourteenth switching element configured to supply the first voltage source to the gate line in response to the third voltage source charged in the second node; And a fifteenth switching element for supplying the first voltage source to the gate line in response to the fourth voltage source charged to the third node.

In addition, the shift register according to the present invention for achieving the above object, a plurality of clock pulses sequentially output to have a different phase and overlap a predetermined interval, the scan pulse from the previous stage, and from the next stage A shift register having a plurality of stages for outputting scan pulses in response to a scan pulse, wherein each stage is embedded on a liquid crystal panel, and the second node is connected in response to a start pulse or a scan pulse from a previous stage. A second switching element for discharging to a first voltage source; A third switching element for discharging the third node to the first voltage source in response to a start pulse or a scan pulse from a previous stage; A fourth switching element which is turned on or turned off in response to a third voltage source having a different polarity for each frame, and charges the second node with a third voltage source at turn-on; A fifth switching device configured to discharge the third node to a first voltage source in response to a third voltage source charged in the second node; A sixth switching element which is turned on or off in response to a fourth voltage source having a polarity opposite to the third voltage source, and charges a third node to the fourth voltage source when turned on; A seventh switching element discharging the second node to a first voltage source in response to a fourth voltage source charged to the third node; An eighth switching element for discharging the second node to the first voltage source in response to the second voltage source charged to the first node; A ninth switching element configured to discharge the third node to the first voltage source in response to the second voltage source charged to the first node; A tenth switching element configured to discharge the first node to the first voltage source in response to the third voltage source charged in the second node; An eleventh switching element discharging the first node to the first voltage source in response to the fourth voltage source charged to the third node; A twelfth switching element for discharging the first node to the first voltage source in response to the scan pulse from the next stage; A thirteenth switching element configured to output a scan pulse in response to a second voltage source charged in the first node and to supply the scan pulse to the gate line, the next stage, and the previous stage; A fourteenth switching element configured to supply a second voltage source to the gate line in response to the third voltage source charged in the second node; And a fifteenth switching element for supplying the second voltage source to the gate line in response to the fourth voltage source charged in the third node.

In addition, the shift register according to the present invention for achieving the above object, a plurality of clock pulses sequentially output to have a different phase and overlap a predetermined interval, the scan pulse from the previous stage, and from the next stage A shift register having a plurality of stages for outputting scan pulses in response to the scan pulses, wherein each stage is embedded on the liquid crystal panel, and the first node is connected in response to a start pulse or a scan pulse from a previous stage. A first switching device for charging with a second voltage source; A second switching element for discharging a second node to a first voltage source in response to a start pulse or a scan pulse from a previous stage; A third switching element for discharging the third node to the first voltage source in response to a start pulse or a scan pulse from a previous stage; A fourth switching element which is turned on or turned off in response to a third voltage source having a different polarity for each frame, and charges the second node with a third voltage source at turn-on; A fifth switching device configured to discharge the third node to a first voltage source in response to a third voltage source charged in the second node; A sixth switching element which is turned on or off in response to a fourth voltage source having a polarity opposite to the third voltage source, and charges a third node to the fourth voltage source when turned on; A seventh switching element discharging the second node to a first voltage source in response to a fourth voltage source charged to the third node; An eighth switching element for discharging the second node to the first voltage source in response to the second voltage source charged to the first node; A ninth switching element configured to discharge the third node to the first voltage source in response to the second voltage source charged to the first node; A tenth switching element configured to discharge the first node to the first voltage source in response to the third voltage source charged in the second node; An eleventh switching element discharging the first node to the first voltage source in response to the fourth voltage source charged to the third node; A twelfth switching element for discharging the first node to the first voltage source in response to the scan pulse from the next stage; A thirteenth switching element configured to output a scan pulse in response to a second voltage source charged in the first node and to supply the scan pulse to the gate line, the next stage, and the previous stage; A fourteenth switching element configured to supply a second voltage source to the gate line in response to the third voltage source charged in the second node; And a fifteenth switching element for supplying the second voltage source to the gate line in response to the fourth voltage source charged in the third node.

Hereinafter, a shift register according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 is a diagram illustrating a shift register according to a first embodiment of the present invention, and FIG. 5 is a timing diagram of a scan pulse output from each stage of FIG. 4 and a signal supplied to each stage.

The shift register according to the first embodiment of the present invention is composed of n stages BST1 to BSTn, and first and second dummy stages BSTn + 1 and BSTn + 2 connected to each other. Here, each of the stages BST1 to BSTn + 2 outputs one scan pulse Vout1 to Voutn + 2, and in this case, scan pulses are sequentially performed from the first stage BST1 to the second dummy stage BSTn + 1. (Vout1 to Voutn + 2) is output. In this case, the scan pulses Vout1 to Voutn output from the stages BST1 to BSTn except for the first and second dummy stages BSTn + 1 and BSTn + 2 are connected to the liquid crystal panel (not shown). The gate lines are sequentially supplied to sequentially scan the gate lines. Here, the scan pulses Vout1 to Voutn + 2 include the first impulse PL1 and the second impulse PL2 as described above. In addition, the scan pulses Vout1 to Voutn + 2 output from the stages BST1 to BSTn + 2 overlap each other.

The entire stages BST1 to BSTn + 2 of the shift registers configured as described above are circulated with the first voltage source VDD and the second voltage source VSS and have a sequential phase difference with each other. Two clock pulses of CLK4 and two charging pulses of the first to fourth charging pulses F1 to F4 are supplied. Here, the first voltage source VDD means a positive DC voltage source, and the second voltage source VSS means a negative DC voltage source.

Here, the first stage BST1 positioned at the uppermost side of the stages BST1 to BSTn + 2 may include the first voltage source VDD, the second voltage source VSS, and the first to fourth clock pulses. In addition to two clock pulses among the CLK1 to CLK4 and two charge pulses among the first to fourth charge pulses F1 to F4, the start pulse SP is supplied.

As described above, the first to fourth clock pulses CLK1 to CLK4 are delayed and outputted from each other. That is, the second clock pulse CLK2 is output after being phase-delayed than the first clock pulse CLK1, and the third clock pulse CLK3 is output by being phase-delayed than the second clock pulse CLK2. The fourth clock pulse CLK4 is output in phase delay than the third clock pulse CLK3 and the first clock pulse CLK1 is output in phase delay than the fourth clock pulse CLK4.

Meanwhile, the start pulse SP applied to the first stage BST1 among the stages BST1 to BSTn + 2 is output earlier than the clock pulses CLK1 to CLK4. In addition, the start pulse SP is output only once in one frame. That is, after the start pulse SP is first outputted every frame, the first to fourth clock pulses CLK1 to CLK4 are sequentially output. In this case, the first to fourth clock pulses CLK1 to CLK4 are sequentially output, and are also output while cycling. That is, after the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output, the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output. Therefore, the first clock pulse CLK1 is output in a period corresponding to the fourth clock pulse CLK4 and the second clock pulse CLK2. The fourth clock pulse CLK4 and the start pulse SP may be output in synchronization with each other. In this case, the fourth clock pulse CLK4 is first outputted among the first to fourth clock pulses CLK1 to CLK4.

Each of the first to fourth clock pulses CLK1 to CLK4 is continuously output at a predetermined period. Therefore, when four clock pulses are used as described above, the first to fourth stages BST1 to BST4 output the first to fourth clock pulses CLK1 to CLK4 as scan pulses. At this time, since the first to fourth clock pulses CLK1 to CLK4 are sequentially delayed as described above, the scan pulses Vout1 output from the first to fourth stages BST1 to BST4 are sequentially delayed. To Vout4) are also sequentially delayed and output. That is, the scan pulses Vout1 to Vout4 are sequentially output. The fifth stage again outputs the first clock pulse CLK1 as a scan pulse. In this case, the first clock pulse CLK1 output by the fifth stage is a pulse delayed by one period from the first clock pulse CLK1 output from the first stage BST1.

Here, each of the clock pulses CLK1 to CLK4 has the same waveform as the scan pulses Vout1 to Voutn + 2. That is, each of the first to fourth clock pulses CLK1 to CLK4 includes a first impulse PL1 and a second impulse PL2, and the first to fourth clock pulses CLK1 to CLK4 overlap each other. Is output.

Meanwhile, the shift register according to the present invention may use two or more clock pulses. That is, the shift register according to the present invention may use only the first and second clock pulses CLK1 and CLK2 among the first to fourth clock pulses CLK1 to CLK4, and the first to third clock pulses CLK1. To CLK3) only. In addition, the shift register according to the present invention may use four or more clock pulses sequentially output.

As described above, the first to fourth charging pulses F1 to F4 (CLK1 to CLK4) are phase-delayed by one pulse width and output. When the stages BST1 to BSTn + 2 are disabled, the first to fourth charging pulses F1 to F4 charge each stage by charging the second node included in each of the stages BST1 to BSTn + 2. Enables (BST1 to BSTn + 2) to output the second voltage source VSS. This will be described in more detail later.

Here, the second charging pulse CLK2 is output by being phase-delayed by one pulse width than the first charging pulse F1, and the third charging pulse F3 is one pulse than the second charging pulse F2. Phase delayed by a width and output, the fourth charge pulse (F4) is phase-delayed output by one pulse width than the third charge pulse (F3), the first charge pulse (F1) is the fourth charge pulse Phase delayed by one pulse width (F4) is output.

In this case, the first to fourth charging pulses (F1 to F4) are sequentially output, it is also output while circulating. That is, the first charging pulse F1 to the fourth charging pulse F4 are sequentially output, and then the first charging pulse F1 to the fourth charging pulse F4 are sequentially output. Therefore, the first charging pulse F1 is output in a period corresponding to the fourth charging pulse F4 and the second charging pulse F2. The fourth charging pulse F4 and the start pulse SP may be output in synchronization with each other. In this case, the fourth charging pulse F4 is first outputted among the first to fourth charging pulses F1 to F4.

Meanwhile, the shift register according to the present invention may use two or more charging pulses. That is, the shift register according to the present invention may use only the first and second charging pulses F1 and F2 among the first to fourth charging pulses F1 to F4, and the first to third charging pulses F1. To F3) only. In addition, the shift register according to the present invention may use four or more charging pulses sequentially output. These four filling pulses do not overlap each other.

The first to nth stages BST1 to BSTn and the first and second dummy stages BSTn + 1 and BSTn + 2 are node controllers for controlling charge and discharge states of the first and second nodes. And an output unit for outputting a scan pulse or a second voltage source VSS according to the states of the first and second nodes and supplying the scan pulse or the second voltage source VSS to the gate line of the liquid crystal panel.

Here, the first node and the second node are alternately charged and discharged. Specifically, when the first node is charged, the second node maintains a discharged state, and when the second node is charged The first node is maintained in a discharged state.

When the first node is in a charged state and the second node is in a discharged state, the output unit outputs a scan pulse. On the other hand, when the first node is in a discharge state and the second node is in a charged state, the output unit outputs a second voltage source VSS.

The operation of the shift register according to the first embodiment of the present invention configured as described above will be described in detail as follows.

First, when the start pulse SP from the timing controller is input to the first stage BST1, the first stage BST1 is enabled in response to the start pulse SP. Subsequently, the enabled first stage BST1 receives the first clock pulse CLK1 from the timing controller and outputs a first scan pulse Vout1. The first stage BST1 receives the first gate line and the second stage BST2. To feed. Then, the second stage BST2 is enabled in response to the first scan pulse Vout1. Subsequently, the enabled second stage BST2 receives the second clock pulse CLK2 from the timing controller and outputs a second scan pulse Vout2. The second stage BST2 receives the second gate line and the third stage BST3. Supplies). Then, the third stage BST3 is enabled in response to the second scan pulse Vout2. Subsequently, the enabled third stage BST3 receives the third clock pulse CLK3 from the timing controller and outputs a third scan pulse Vout3 Vout3, which is then applied to the third gate line and the fourth gate line. The stage BST4 and the first stage BST1 are supplied together. Then, the fourth stage BST4 is enabled in response to the third scan pulses Vout3 and Vout3, and the first stage BST1 supplies the second voltage source VSS to the first gate line. do. Subsequently, the enabled fourth stage BST4 receives the fourth clock pulse CLK4 from the timing controller and outputs a fourth scan pulse Vout4. The fourth stage BST4 receives the fourth gate line and the fifth stage BST5. And the second stage BST2 together. Then, the fifth stage is enabled in response to the fourth scan pulse Vout4, and the second stage BST2 supplies the second voltage source VSS to the second gate line. Subsequently, the enabled fifth stage receives the first clock pulse CLK1 from the timing controller and outputs a fifth scan pulse, and the fifth gate line, the sixth stage, and the third stage BST3. ) Together. Then, the sixth stage is enabled in response to the fifth scan pulse, and the third stage BST3 supplies a second voltage source VSS to the third gate line. In this manner, the sixth to nth scan pulses Vout6 to Voutn are sequentially output to the sixth to nth stages BST6 to BSTn, and they are sequentially supplied to the sixth to nth gate lines, respectively. . In this case, the adjacent scan pulses have a pulse width section overlapping by a predetermined time. Here, the first dummy stage BSTn + 1 serves to supply the n + 1th scan pulse Voutn + 1 to the n-1th stage BSTn-1 and the second dummy stage BSTn + 2. Supplies the n + 2th scan pulse Voutn + 2 to the nth stage BSTn. That is, the n + 1 and n + 2 scan pulses Voutn + 1 and Voutn + 2 output from the first and second dummy stages BSTn + 1 and BSTn + 2 are not supplied to the gate line. Only the dummy outputs serve to output the second voltage source VSS by the n-th and n-th stages BSTn-1 and BSTn.

In this way, each stage BST1 to BSTn + 2 outputs scan pulses Vout1 to Voutn + 2 and provides it as a start pulse SP to the next stage. Each of the stages BST1 to BSTn + 2 supplies a second voltage source VSS to a corresponding gate line in response to a scan pulse output from a stage located next to the next stage.

Meanwhile, a third charging pulse F3 is input to the first stage BST1, a fourth charging pulse F4 is input to the second stage BST2, and a first charging pulse is input to the third stage BST3. F1 is input, the second charging pulse F2 is input to the fourth stage BST4, and the first charging pulse F1 is input to the n-1th stage BSTn-1. The second charging pulse F2 is input to the n-th stage BSTn, the third charging pulse F3 is input to the first dummy stage BSTn + 1, and the second charging pulse F3 is input to the second dummy stage BSTn + 2. The fourth charging pulse F4 is input.

Here, the charging pulses F1 to F4 supplied to each of the stages BST1 to BSTn + 2 are output at the same time as the scan pulse output from the stage located next to the stage. For example, the third charging pulse F3 supplied to the first stage BST1 is output at the same time as the third scan pulse Vout3 Vout3 output from the third stage BST3. That is, the first stage BST1 receives the third scan pulse Vout3 and the third charging pulse F3 simultaneously from the third stage BST3. As a result, the third charging pulse F3 and the third scan pulse Vout3 from the third stage BST3 are disabled. The remaining stages operate in the same manner as the first stage BST1.

Here, a circuit configured in each of the stages BST1 to BSTn + 2 will be described in detail. Meanwhile, since the circuit configurations of the stages BST1 to BSTn + 2 are all the same, only the third stage BST3 will be described as an example.

FIG. 6 is a circuit diagram illustrating the third stage of FIG. 4.

The third stage BST3 includes the node control unit 600a and the output unit 600b as described above.

The node control unit 600a of the third stage BST3 includes first to sixth NMOS transistors Tr1 to Tr6.

The first NMOS transistor Tr1 charges the first node Q to the first voltage source VDD in response to the scan pulse from the previous stage. That is, the first NMOS transistor Tr1 charges the first node Q to the first voltage source VDD in response to the second scan pulse Vout2 from the second stage BST2. To this end, the gate terminal of the first NMOS transistor Tr1 is connected to the second stage BST2, the source terminal is connected to a power line for transmitting the first voltage source VDD, and the drain terminal is connected to the first node. It is connected to (Q).

The second NMOS transistor Tr2 discharges the second node QB to the second voltage source VSS in response to the scan pulse from the previous stage. That is, the second NMOS transistor Tr2 discharges the second node QB to the second voltage source VSS in response to the second scan pulse Vout2 from the second stage BST2. To this end, the gate terminal of the second NMOS transistor Tr2 is connected to the second stage BST2, the source terminal is connected to the second node QB, and the drain terminal transmits the second voltage source VSS. Is connected to the power supply line.

The third NMOS transistor Tr3 charges the second node QB to the first voltage source VDD in response to a clock pulse synchronized with the scan pulse output from the next stage. That is, the third NMOS transistor Tr3 responds to the first charging pulse F1 (the charging pulse synchronized with the fifth scan pulse output from the fifth stage) and sets the second node QB to the first node. Charge with a voltage source VDD. To this end, a gate terminal of the third NMOS transistor Tr3 is connected to a charging line for transmitting the first charging pulse F1, and a source terminal is connected to a power line for transmitting the first voltage source VDD. The drain terminal is connected to the second node QB.

Meanwhile, the third NMOS transistor Tr3 may receive the scan pulse output from the next next stage instead of the third charge pulse F3. At this time, the third NMOS transistor Tr3 of the third stage BST3 charges the second node QB to the first voltage source VDD in response to the fifth scan pulse from the fifth stage. As described above, when the third NMOS transistor Tr3 operates by receiving the scan pulse output from the next stage, the first to fourth charging pulses F1 to F4 are not required. Therefore, when the third NMOS transistor Tr3 operates by receiving the scan pulse output from the next stage, the shift register may be operated using only the first to fourth clock pulses CLK1 to CLK4. .

The fourth NMOS transistor Tr4 discharges the first node Q to the second voltage source VSS in response to the first voltage source VDD charged in the second node QB. To this end, a gate terminal of the fourth NMOS transistor Tr4 is connected to the second node QB, a source terminal is connected to the first node Q, and a drain terminal of the fourth voltage source VSS is connected to the first node QB. It is connected to the transmitting power line.

The fifth NMOS transistor Tr5 discharges the second node QB to the second voltage source VSS in response to the first voltage source VDD charged in the first node Q. To this end, the gate terminal of the fifth NMOS transistor Tr5 is connected to the first node Q, the source terminal is connected to the second node QB, and the drain terminal transmits the second voltage source VSS. Is connected to the power supply line.

The sixth NMOS transistor Tr6 discharges the first node Q to the second voltage source VSS in response to the scan pulse output from the next stage. That is, the sixth NMOS transistor Tr6 discharges the first node Q to the second voltage source VSS in response to the fifth scan pulse from the fifth stage. To this end, the gate terminal of the sixth NMOS transistor Tr6 is connected to the fifth stage BST5, the source terminal is connected to the first node Q, and the drain terminal of the sixth NMOS transistor Tr6 is connected to the second voltage source VSS. It is connected to the transmitting power line.

The output part 600b of the 3rd stage BST3 is equipped with the 7th and 8th NMOS transistors Tr7 and Tr8.

The seventh NMOS transistor Tr7 outputs a scan pulse in response to the first voltage source VDD charged in the first node Q. Then, it is supplied to the corresponding gate line, the front stage, and the next stage. That is, the seventh NMOS transistor Tr7 outputs the third clock pulse CLK3 as a third scan pulse Vout3 Vout3 in response to the first voltage source VDD charged in the first node Q. do. The output third scan pulses Vout3 and Vout3 are supplied to the third gate line, the first stage BST1, and the fourth stage BST4. Here, the third scan pulses Vout3 and Vout3 supplied to the first stage BST1 disable the first stage BST1 and the third scan pulses supplied to the fourth stage BST4. Vout3) Vout3 enables the fourth stage BST4. For this purpose, the gate terminal of the seventh NMOS transistor Tr7 is connected to the first node Q, the source terminal is connected to the clock line for transmitting the third clock pulse CLK3, and the drain terminal is Commonly connected to the three gate lines, the first stage BST1, and the fourth stage BST3.

The eighth NMOS transistor Tr8 outputs the second voltage source VSS in response to the first voltage source VDD charged in the second node QB. Then, the second voltage source VSS is supplied to the gate line connected to the stage to which it belongs, the stage of the previous stage, and the stage of the next stage. To this end, the gate terminal of the eighth NMOS transistor Tr8 is connected to the second node QB, and the source terminal is common to the third gate line, the first stage BST1, and the fourth stage BST4. The drain terminal is connected to a power line for transmitting the second voltage source VSS.

The first and second stages BST1 and BST2, the fourth to nth stages BST4 to BSTn, and the first and second dummy stages BSTn + 1 and BSTn + 2 are also described in the third stage BST3. Has the same configuration as

However, since there is no stage before the first stage BST1, the first and second NMOS transistors Tr1 and Tr2 included in the first stage BST1 may have a start pulse SP from the timing controller. Is supplied). That is, the first NMOS transistor Tr1 of the first stage BST1 charges the first node Q to the first voltage source VDD in response to the start pulse SP from the timing controller. The second NMOS transistor Tr2 discharges the second node QB to the second voltage source VSS in response to the start pulse SP from the timing controller.

There is no stage at the front ends of the first and second stages BST1 and BST2. Therefore, the first stage BST1 outputs the first scan pulse Vout1 and supplies it to the first gate line and the second stage BST2. Similarly, the second stage BST2 outputs the second scan pulse Vout2 and supplies it to the second gate line and the third stage BST3.

There is no stage next to the second dummy stage BSTn + 2. Therefore, drain terminals of the seventh and eighth NMOS transistors Tr7 and Tr8 of the second dummy stage BSTn + 2 are connected to gate terminals of the sixth NMOS transistor Tr6 of the nth stage BSTn. .

The operation of the shift register according to the embodiment of the present invention configured as described above is as follows.

FIG. 7 is a diagram illustrating first to third stages having the circuit configuration of FIG. 6.

First, the start pulse SP is applied to the gate terminal of the first NMOS transistor Tr1 and the gate terminal of the second NMOS transistor Tr2 to turn on the first and second NMOS transistors Tr1 and Tr2. Turn on

Then, the first voltage source VDD is supplied to the first node Q through the turned-on first NMOS transistor Tr1. In this case, as the first node Q is charged with the first voltage source VDD, the fifth and seventh NMOS transistors Tr5 and Tr7 having gate terminals connected to the first node Q turn on. Is on. Here, the second voltage source VSS is supplied to the second node QB through the turned-on fifth NMOS transistor Tr5. As a result, the second node QB is discharged to the second voltage source VSS, and the fourth and eighth NMOS transistors Tr4 and Tr8 having gate terminals connected to the second node QB are turned off. do.

As such, the first node Q of the first stage BST1 is charged to the first voltage source VDD by the start pulse SP, and the second node QB is charged to the second voltage source VSS. By discharging, the first stage BST1 is enabled.

In this state, when the first clock pulse CLK1 is supplied to the seventh NMOS transistor Tr7 of the first stage BST1, the seventh NMOS transistor Tr7 removes the first clock pulse CLK1. Outputs as one scan pulse (Vout1). In this case, since the first clock pulse CLK1 and the start pulse SP are superimposed and output, the first scan pulse Vout1 is superimposed on the start pulse SP and output.

The first scan pulse Vout1 is supplied to the first gate line and the second stage BST2. The first scan pulse Vout1 from the first stage BST1 is supplied to the first and second NMOS transistors Tr1 and Tr2 of the second stage BST2. Accordingly, the first node Q of the second stage BST2 is charged and the second node QB is discharged.

That is, the second stage BST2 is enabled by the first scan pulse Vout1. In other words, as the first stage BST1 is enabled by the start pulse SP, the second stage BST2 is enabled by the first scan pulse. In this state, when the second clock pulse CLK2 is supplied to the seventh NMOS transistor Tr7 of the second stage BST2, the seventh NMOS transistor Tr7 removes the second clock pulse CLK2. Outputs as 2 scan pulses (Vout2). In this case, since the second clock pulse CLK2 overlaps the first clock pulse CLK1, the second scan pulse Vout2 is output to overlap the first scan pulse Vout1.

The second scan pulse Vout2 is supplied to the second gate line and the third stage BST3. That is, the second scan pulse Vout2 from the second stage BST2 is supplied to the first and second NMOS transistors Tr1 and Tr2 of the third stage BST3. Accordingly, the first node Q of the third stage BST3 is charged and the second node QB is discharged. That is, the third stage BST3 is enabled by the second scan pulse Vout2. In other words, as the first stage BST1 is enabled by the start pulse SP, the third stage BST3 is enabled by the second scan pulse Vout2.

In this state, when the third clock pulse CLK3 is supplied to the seventh NMOS transistor Tr7 of the third stage BST3, the seventh NMOS transistor Tr7 removes the third clock pulse CLK3. Outputs as 3 scan pulses (Vout3). In this case, since the third clock pulse CLK3 overlaps the second clock pulse CLK2, the third scan pulse Vout3 is output to overlap the second scan pulse Vout2.

The third scan pulse Vout3 is supplied to the third gate line and the fourth stage BST4. That is, the third scan pulse Vout3 from the third stage BST3 is supplied to the first and second NMOS transistors Tr1 and Tr2 of the fourth stage BST4. Accordingly, the first node Q of the fourth stage BST4 is charged and the second node QB is discharged. That is, the fourth stage BST4 is enabled by the third scan pulse Vout3. In other words, as the first stage BST1 is enabled by the start pulse SP, the fourth stage BST4 is enabled by the third scan pulse Vout3.

In this state, when the fourth clock pulse CLK4 is supplied to the seventh NMOS transistor Tr7 of the fourth stage BST4, the seventh NMOS transistor Tr7 removes the fourth clock pulse CLK4. Outputs as 4 scan pulses (Vout4). In this case, since the fourth clock pulse CLK4 overlaps the third clock pulse CLK3, the fourth scan pulse Vout4 is output to overlap the third scan pulse Vout3.

Meanwhile, the third scan pulse Vout3 output from the third stage BST3 is also supplied to the sixth NMOS transistor Tr6 of the first stage BST1. That is, the third scan pulse Vout3 is supplied to the gate terminal of the sixth NMOS transistor Tr6 provided in the first stage BST1. At this time, the third charging pulse F3 is output in synchronization with the third scan pulse Vout3. The third charging pulse F3 is supplied to the gate terminal of the third NMOS transistor Tr3 provided in the first stage BST1. As such, as the third scan pulse Vout3 and the third charging pulse F3 are supplied to the first stage BST1, the first stage BST1 is disabled.

In detail, the third scan pulse Vout3 turns on the sixth NMOS transistor Tr6 provided in the first stage BST1. Then, the second voltage source VSS is supplied to the first node Q of the first stage BST1 through the turned-on sixth NMOS transistor Tr6. Accordingly, the first node Q of the first stage BST1 is discharged. Accordingly, the fifth and seventh NMOS transistors Tr5 and Tr7 connected to the first node Q of the first stage BST1 are turned off.

In addition, as the third charging pulse F3 is supplied to the gate terminal of the third NMOS transistor Tr3 of the first stage BST1, the third NMOS transistor Tr3 of the first stage BST1 is supplied. Is turned on. Then, the first voltage source VDD is supplied to the second node QB of the first stage BST1 through the turned-on third NMOS transistor Tr3. Accordingly, the second node QB of the first stage BST1 is charged. Accordingly, the fourth and eighth NMOS transistors Tr4 and Tr8 having gate terminals connected to the second node QB of the first stage BST1 are turned on. Here, as the second voltage source VSS is supplied to the first node Q through the turned-on fourth NMOS transistor Tr4, the discharge of the first node Q is accelerated.

In this way, the first node Q of the first stage BST1 is discharged by the third scan pulse Vout3 and the third charging pulse F3 from the third stage BST3, and the second Node QB is charged. That is, the first stage BST1 is disabled by the third scan pulse Vout3 and the third charging pulse F3 from the third stage BST3. The disabled first stage BST1 outputs the second voltage source VSS through the eighth NMOS transistor Tr8 provided therein. Then, the second voltage source VSS is supplied to the first gate line.

In this manner, each stage BST1 to BSTn + 2 is enabled by a scan pulse output from the previous stage from itself. Then, each stage BST1 to BSTn + 2 is disabled by the scan pulse from the stage located next to it.

Hereinafter, the shift register according to the second embodiment of the present invention will be described in detail.

Hereinafter, the shift register according to the second embodiment of the present invention will be described in detail.

FIG. 8 is a diagram illustrating a shift register according to a second embodiment of the present invention, FIG. 9A is a timing diagram of scan pulses output from the stage of FIG. 8 during odd-numbered frames, and various signals supplied to the stages. FIG. 9B is a timing diagram of scan pulses output from the stage of FIG. 8 during even-numbered frames, and various signals supplied to the stages.

As illustrated in FIG. 8, the shift register according to the second embodiment of the present invention includes n stages connected to each other and first and second dummy stages CSTn + 1 and CSTn + 2. . Here, all the stages CST1 to CSTn + 2 output one scan pulse Vout1 to Voutn + 2, and in this case, scan pulses are sequentially performed from the first stage CST1 to the second dummy stage CSTn + 2. (Vout1 to Voutn + 2) is output. In this case, the scan pulses Vout1 to Voutn output from the stages CST1 to CSTn except for the first and second dummy stages CSTn + 1 and CSTn + 2 are connected to the liquid crystal panel (not shown). The gate lines are sequentially supplied to sequentially scan the gate lines.

On the other hand, the entire stages CST1 to CSTn of the shift registers configured as described above are the first to fourth voltage sources VDD, VSS, VDD3, and VDD4 and the first to fourth clock pulses CLK1 to cyclic with sequential phase differences. One clock pulse of CLK4) is applied. Here, the first voltage source VDD refers to a positive DC voltage source, and the second voltage source VSS refers to a negative voltage source. The third voltage source VDD3 and the fourth voltage source VDD4 are AC voltage sources having polarities inverted for each frame. In this case, the third voltage source VDD3 has an inverted phase with respect to the fourth voltage source VDD4. That is, the third voltage source VDD3 and the fourth voltage source VDD4 have different polarities within the same frame.

Here, the first stage CST1 positioned at the uppermost side of the stages CST1 to CSTn may include the first to fourth voltage sources VDD, VSS, VDD3, and VDD4, and the first to fourth clock pulses. In addition to one of the clock pulses CLK1 to CLK4, a start pulse SP is supplied.

On the other hand, as described above, the first to fourth clock pulses CLK1 to CLK4 are delayed and outputted from each other. That is, the second clock pulse CLK2 is output after being phase-delayed than the first clock pulse CLK1, and the third clock pulse CLK3 is output by being phase-delayed than the second clock pulse CLK2. The fourth clock pulse CLK4 is output in phase delay than the third clock pulse CLK3 and the first clock pulse CLK1 is output in phase delay than the fourth clock pulse CLK4.

Meanwhile, the start pulse SP applied to the first stage CST1 among the stages CST1 to CSTn + 1 is output before the clock pulses CLK1 to CLK4. In addition, the start pulse SP is output only once in one frame. That is, after the start pulse SP is output first in every frame, the first to fourth clock pulses CLK1 to CLK4 are sequentially output. At this time, the first to fourth clock pulses CLK1 to CLK4 are sequentially output, and are also output while circulating. That is, after the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output, the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output. Therefore, the first clock pulse CLK1 is output in a period corresponding to the fourth clock pulse CLK4 and the second clock pulse CLK2. The fourth clock pulse CLK4 and the start pulse SP may be output in synchronization with each other. In this case, the fourth clock pulse CLK4 is first outputted among the first to fourth clock pulses CLK1 to CLK4.

Here, each clock pulse has the same waveform as each of the scan pulses Vout1 to Voutn + 2. That is, each of the first to fourth clock pulses CLK1 to CLK4 includes a first impulse PL1 and a second impulse PL2, and the first to fourth clock pulses CLK1 to CLK4 overlap each other. Is output. Of course, each scan pulse Vout1 to Voutn + 2 also has the same waveform as the first to fourth clock pulses CLK1 to CLK4.

Meanwhile, the shift register according to the present invention may use two or more clock pulses. That is, the shift register according to the present invention may use only the first and second clock pulses CLK1 and CLK2 among the first to fourth clock pulses CLK1 to CLK4, and the first to third clock pulses CLK1 to CLK4. You can also use only CLK3). In addition, the shift register according to the present invention may use four or more clock pulses sequentially output.

The operation of the shift register constructed as described above will be described in detail as follows.

First, when the start pulse SP from the timing controller is input to the first stage CST1, the first stage CST1 is enabled in response to the start pulse SP. Subsequently, the enabled first stage CST1 receives the first clock pulse CLK1 from the timing controller and outputs a first scan pulse Vout1. The first stage CST1 receives the first gate line and the second stage CST2. To feed. Then, the second stage CST2 is enabled in response to the first scan pulse Vout1. Subsequently, the enabled second stage CST2 receives the second clock pulse CLK2 from the timing controller and outputs a second scan pulse Vout2. The second stage CST2 receives the second gate line and the third stage CST3. Supplies). Then, the third stage CST3 is enabled in response to the second scan pulse Vout2. Subsequently, the enabled third stage CST3 receives the third clock pulse CLK3 from the timing controller and outputs a third scan pulse Vout3. The third stage CST3 receives the third gate line and the fourth stage CST4. And the first stage CST1 together. Then, the fourth stage CST4 is enabled in response to the third scan pulse Vout3, and the first stage CST1 supplies a second voltage source VSS to the first gate line. Subsequently, the enabled fourth stage CST4 receives the fourth clock pulse CLK4 from the timing controller and outputs a fourth scan pulse Vout4, and the fourth gate line and the fifth stage, and Supply to the second stage CST2. Then, the fifth stage CST5 is enabled in response to the fourth scan pulse Vout4, and the second stage CST2 supplies a second voltage source VSS to the second gate line. Subsequently, the enabled fifth stage receives the first clock pulse CLK1 from the timing controller and outputs a fifth scan pulse, and the fifth gate line, the sixth stage, and the third stage CST3. ) Together. Then, the sixth stage is enabled in response to the fifth scan pulse, and the third stage CST3 supplies a second voltage source VSS to the third gate line. In this manner, the sixth to nth scan pulses Voutn are sequentially output to the sixth to nth stages CSTn, and they are sequentially supplied to the sixth to nth gate lines, respectively. In this case, the adjacent scan pulses have a pulse width section overlapping by a predetermined time. Here, the first dummy stage CSTn + 1 serves to supply the n + 1 scan pulse Voutn + 1 to the n-1th stage CSTn-1, and the second dummy stage CSTn + 2. 300h serves to supply the n + 2th scan pulse Voutn + 2 to the nth stage CSTn. That is, the n + 1 and n + 2 scan pulses Voutn + 1 and Voutn + 2 output from the first and second dummy stages CSTn + 1 and CSTn + 2 are not supplied to the gate line. Only the dummy outputs serve to output the third voltage source VDD3 by the n-th and n-th stages CSTn-1 and CSTn.

In this manner, each stage CST1 to CSTn + 2 outputs scan pulses Vout1 to Voutn + 2, and supplies them sequentially to the corresponding gate lines, respectively, and at the next stage, as a start pulse SP. to provide. Each of the stages CST1 to CSTn + 2 supplies a second voltage source VSS to a corresponding gate line in response to a scan pulse output from a stage located next to the next stage.

Each stage CST1 to CSTn + 2 has a node control unit that largely controls charging and discharging of the first, second, and third nodes, and a charge / discharge state of the first, second, and third nodes. It is turned on according to the output unit for selectively outputting a scan pulse or a second voltage source (VSS). Here, the first, second, and third nodes are selectively charged and discharged. Specifically, when the first node is in a charged state, both the second node and the third node maintain a discharged state. When the first node is in the discharged state, one of the second node and the third node maintains the charged state. That is, in the odd frame, the second node is charged when the first node is in the discharge state, the third node is discharged, and in the even frame, when the first node is in the discharge state, the second node is discharged. The node is discharged and the third node is charged. As such, when the first node is in a discharged state, the reason for applying (charge and discharge) voltage sources VDD3 and VDD4 having different polarities to each of the frames by the second node and the third node is as follows. This is to prevent deterioration of a switching device having a gate terminal connected to three nodes.

Here, each stage of the shift register according to the second embodiment of the present invention will be described in more detail as follows.

FIG. 10 is a circuit diagram illustrating the third stage of FIG. 8.

The shift register according to the second embodiment of the present invention includes the node control unit 100a and the output unit 100b described above.

The node controller 100a of the third stage CST3 includes first to twelfth NMOS transistors Tr1 to Tr12.

The first NMOS transistor Tr1 charges the first node Q to the first voltage source VDD in response to the scan pulse from the previous stage. That is, the first NMOS transistor Tr1 charges the first node Q to the first voltage source VDD in response to the second scan pulse Vout2 from the second stage CST2. To this end, the gate terminal of the first NMOS transistor Tr1 is connected to the second stage CST2, the source terminal is connected to a power line for transmitting the first voltage source VDD, and the drain terminal is connected to the first node. It is connected to (Q).

The second NMOS transistor Tr2 discharges the second node QB1 to the second voltage source VSS in response to the scan pulse from the previous stage. That is, the second NMOS transistor Tr2 discharges the second node QB1 to the second voltage source VSS in response to the second scan pulse Vout2 from the second stage CST2. To this end, the gate terminal of the second NMOS transistor Tr2 is connected to the second stage CST2, the source terminal is connected to the second node QB1, and the drain terminal transmits the second voltage source VSS. Is connected to the power supply line.

The third NMOS transistor Tr3 discharges the third node QB2 to the second voltage source VSS in response to the scan pulse from the previous stage. That is, the third NMOS transistor Tr3 discharges the third node QB2 to the second voltage source VSS in response to the second scan pulse Vout2 from the second stage CST2. To this end, the gate terminal of the third NMOS transistor Tr3 is connected to the second stage CST2, the source terminal is connected to the second node QB1, and the drain terminal transmits the second voltage source VSS. It is connected to the power line.

The fourth NMOS transistor Tr4 is turned on or turned off in response to the third voltage source VDD3, and charges the second node QB1 to the third voltage source VDD3 at turn-on. For this purpose, the gate terminal of the fourth NMOS transistor Tr4 is connected to a power line for transmitting the third voltage source VDD3, the source terminal is connected to a power line for transmitting the third voltage source VDD3, and the drain The terminal is connected to the second node QB1. The third voltage source VDD3 is an AC voltage having alternating positive and negative polarities every frame. That is, the third voltage source VDD3 has positive polarity in odd frames and negative polarity in even frames.

The fifth NMOS transistor Tr5 discharges the third node QB2 to the second voltage source VSS in response to the third voltage source VDD3. To this end, the gate terminal of the fifth NMOS transistor Tr5 is connected to a power line for transmitting the third voltage source VDD3, the source terminal is connected to a third node QB2, and the drain terminal is connected to the second node. It is connected to a power supply line that transmits a voltage source VSS.

The sixth NMOS transistor Tr6 is turned on or off in response to the fourth voltage source VDD4, and charges the third node QB2 to the fourth voltage source VDD4 when turned on. To this end, the gate terminal of the sixth NMOS transistor Tr6 is connected to a power line for transmitting the fourth voltage source VDD4, and the source terminal is connected to a power line for transmitting the fourth voltage source VDD4. The drain terminal is connected to the third node QB2. Here, the fourth voltage source VDD4 is an AC voltage having alternating positive and negative polarities every frame. In this case, the fourth voltage source VDD4 has an inverted phase with the third voltage source VDD3. That is, the third voltage source VDD3 has negative polarity in odd frames and positive polarity in even frames.

The seventh NMOS transistor Tr7 discharges the second node QB1 to the second voltage source VSS in response to the fourth voltage source VDD4. To this end, a gate terminal of the seventh NMOS transistor Tr7 is connected to a power line for transmitting the fourth voltage source VDD4, a source terminal is connected to the second node QB1, and a drain terminal is connected to the second terminal QB1. 2 is connected to the power supply line for transmitting the voltage source (VSS).

The eighth NMOS transistor Tr8 discharges the second node QB1 to the second voltage source VSS in response to the first voltage source VDD charged in the first node Q. To this end, the gate terminal of the eighth NMOS transistor Tr8 is connected to the first node Q, the source terminal is connected to the second node QB1, and the drain terminal is connected to the second voltage source VSS. It is connected to the power line to transmit.

The ninth NMOS transistor Tr9 discharges the third node QB2 to the second voltage source VSS in response to the first voltage source VDD charged in the first node Q. To this end, the gate terminal of the ninth NMOS transistor Tr9 is connected to the first node Q, the source terminal is connected to the third node QB2, and the drain terminal transmits the second voltage source VSS. Is connected to the power supply line.

The tenth NMOS transistor Tr10 discharges the first node Q to the second voltage source VSS in response to the third voltage source VDD3 charged in the second node QB1. To this end, a gate terminal of the tenth NMOS transistor Tr10 is connected to the second node QB1, a source terminal is connected to the first node Q, and a drain terminal of the second voltage source VSS is connected. It is connected to the transmitting power line.

The eleventh NMOS transistor Tr11 discharges the first node Q to the second voltage source VSS in response to the fourth voltage source VDD4 charged in the third node QB2. To this end, a gate terminal of the eleventh NMOS transistor Tr11 is connected to the third node QB2, a source terminal is connected to the first node Q, and a drain terminal of the second voltage source VSS is connected. It is connected to the transmitting power line.

The twelfth NMOS transistor Tr12 discharges the first node Q to the second voltage source VSS in response to the scan pulse from the next stage. That is, the twelfth NMOS transistor Tr12 discharges the first node Q to the second voltage source VSS in response to the fifth scan pulse Vout5 from the fifth stage. To this end, the gate terminal of the twelfth NMOS transistor Tr12 is connected to the fifth stage, the source terminal is connected to the first node Q, and the drain terminal is connected to a power line for transmitting the second voltage source VSS. Connected.

And. The output unit 100b of the third stage CST3 is composed of the thirteenth to fifteenth NMOS transistors Tr13 to Tr15.

The thirteenth NMOS transistor Tr13 outputs a clock pulse as a scan pulse to the gate line in response to the first voltage source VDD charged in the first node Q. In addition, this scan pulse is supplied to both the front stage and the next stage. For this purpose, the gate terminal of the thirteenth NMOS transistor Tr13 is connected to the first node Q, the source terminal is connected to the clock line for transmitting the third clock pulse CLK3, and the drain terminal is connected to the third gate. A line, a gate terminal of the twelfth NMOS provided in the first stage CST1, and a gate terminal of the first through third NMOS transistors Tr1 through Tr3 provided in the fourth stage CST4.

The fourteenth NMOS transistor Tr14 supplies the second voltage source VSS to the gate line in response to the third voltage source VDD3 charged in the second node QB1. That is, the fourteenth NMOS transistor Tr14 supplies the second voltage source VSS to the third gate line in response to the third voltage source VDD3 charged in the second node QB1. To this end, the gate terminal of the fourteenth NMOS transistor Tr14 is connected to the second node QB1, the drain terminal is connected to a power line for transmitting the second voltage source VSS, and the source terminal is connected to the second gate line. And the gate terminals of the twelfth NMOS transistor Tr12 provided in the first stage CST1 and the gate terminals of the first through third NMOS transistors Tr1 through Tr3 provided in the fourth stage CST4.

The fifteenth NMOS transistor Tr15 supplies the second voltage source VSS to the gate line in response to the fourth voltage source VDD4 charged in the third node QB2. That is, the fifteenth NMOS transistor Tr15 supplies the second voltage source VSS to the third gate line in response to the fourth voltage source VDD4 charged in the third node QB2. To this end, the gate terminal of the fifteenth NMOS transistor Tr15 is connected to the second node QB1, the drain terminal is connected to a power line for transmitting the second voltage source VSS, and the source terminal is connected to the third gate line. The gate terminals of the twelfth NMOS provided in the first stage CST1 and the gate terminals of the first through third NMOS transistors Tr1 through Tr3 provided in the fourth stage CST4.

The first and second stages CST1 and CST2, the fourth to nth stages CST4 to CSTn, and the first and second dummy stages CSTn + 1 and CSTn + 2 are also described in the third stage CST3. Has the same configuration as

However, since there is no stage before the first stage CST1, the first to third NMOS transistors Tr1 to Tr3 included in the first stage CST1 may have the start pulse SP from the timing controller. Is supplied). That is, the first NMOS transistor Tr1 of the first stage CST1 receives the first node Q of the first stage CST1 in response to the start pulse SP from the timing controller. Charge with a voltage source VDD. The second NMOS transistor Tr2 discharges the second node QB1 of the first stage CST1 to the second voltage source VSS in response to the start pulse SP from the timing controller. . The third NMOS transistor Tr3 discharges the third node QB2 of the first stage CST1 to the second voltage source VSS in response to the start pulse SP from the timing controller. .

The stage is not present at the front ends of the first and second stages CST1 and CST2. Therefore, the first stage CST1 outputs the first scan pulse Vout1 and supplies it to the first gate line and the second stage CST2. Similarly, the second stage CST2 outputs the second scan pulse Vout2 and supplies it to the second gate line and the third stage CST3.

There is no stage next to the second dummy stage CSTn + 2. Therefore, the source terminal of the thirteenth NMOS transistor Tr13 of the second dummy stage CSTn + 2, the drain terminal of the fourteenth NMOS transistor Tr14, and the drain terminal of the fifteenth NMOS transistor Tr15 are n-th. It is connected to the gate terminal of the twelfth NMOS transistor Tr12 of the stage CSTn.

The operation of the shift register according to the embodiment of the present invention configured as described above is as follows.

FIG. 11 is a diagram illustrating first to third stages having the circuit configuration of FIG. 10.

Here, it is assumed that the third voltage source VDD3 is maintained at the positive voltage during the first frame, and the fourth voltage source VDD4 is maintained at the negative voltage, and the third voltage source VDD3 is negative during the second frame. It is assumed that the voltage is maintained at the polarity and the fourth voltage source VDD4 is maintained at the voltage of the positive polarity. That is, it is assumed that the third voltage source VDD3 is maintained as the positive polarity during the odd-numbered frame, and the fourth voltage source VDD4 is maintained as the negative polarity, and the third voltage source VDD3 is negative as the negative frame during the even-numbered frame. It is assumed that the fourth voltage source VDD4 remains positive.

First, the start pulse SP is applied to the gate terminal of the first NMOS transistor Tr1, the gate terminal of the second NMOS transistor Tr2, and the gate terminal of the third NMOS transistor Tr3, and thus, the first terminal. , Second, and third NMOS transistors Tr1, Tr2, Tr3 are turned on.

Then, the first voltage source VDD is supplied to the first node Q through the turned-on first NMOS transistor Tr1. In this case, as the first node Q is charged with the first voltage source VDD, the eighth, ninth, and thirteenth NMOS transistors Tr8 and Tr9 having gate terminals connected to the first node Q, respectively. , Tr13) is turned on at the same time. Here, the second voltage source VSS is supplied to the second node QB1 through the turned-on eighth NMOS transistor Tr8 and the second NMOS transistor Tr2. Accordingly, the second node QB1 is maintained in a discharged state, and the tenth and fourteenth NMOS transistors Tr10 and Tr14 having gate terminals connected to the second node QB1 are turned off.

The second voltage source VSS is supplied to the third node QB2 through the turned-on third and ninth NMOS transistors Tr3 and Tr9. In this case, as the third node QB2 is discharged to the second voltage source VSS, the eleventh and fifteen NMOS transistors Tr11 and Tr15 having gate terminals connected to the third node QB2 are turned on. Is off.

In addition, the fourth NMOS transistor Tr4 is turned on as the third voltage source VDD3 is applied to its gate terminal. Since the third voltage source VDD3 is always in a positive state during the first frame, the fourth NMOS transistor Tr4 is always turned on during the first frame. Here, the third voltage source VDD3 is supplied to the second node QB1 through the turned-on fourth NMOS transistor Tr4. As a result, the second voltage source VSS and the third voltage source VDD3 are simultaneously supplied to the second node QB1. However, since the number of transistors supplying the second voltage source VSS is greater than the number of transistors supplying the third voltage source VDD3, the second node QB1 is maintained as the second voltage source VSS. do. As a result, the second node QB1 maintains a discharge state. Accordingly, the tenth and fourteenth NMOS transistors Tr10 and Tr14 having gate terminals connected to the second node QB1 are turned off.

The third voltage source VDD3 is also supplied to the gate terminal of the fifth NMOS transistor Tr5. Accordingly, the fifth NMOS transistor Tr5 is also always turned on during the first frame. The second voltage source VSS is supplied to the third node QB2 through the turned-on fifth NMOS transistor Tr5. As a result, the third node QB2 is maintained in the discharge state by the third, fifth, and ninth NMOS transistors Tr3, Tr5, and Tr9. Accordingly, the eleventh and fifteenth NMOS transistors Tr11 and Tr15 having a gate terminal connected to the third node QB2 are turned off.

The sixth NMOS transistor Tr6 is turned off by the fourth voltage source VDD4 applied to its gate terminal. In this case, since the fourth voltage source VDD4 is negatively maintained during the first frame, the sixth NMOS transistor Tr6 is always turned off during the first frame.

In addition, since the fourth voltage source VDD4 is also applied to the gate terminal of the seventh NMOS transistor Tr7, the seventh NMOS transistor Tr7 is always turned off during the first frame.

As such, the first node Q of the first stage CST1 is charged to the first voltage source VDD by the start pulse SP, and the second and third nodes QB1 and QB2 are secondly charged. By discharging to the voltage source VSS, the first stage CST1 is enabled.

In this state, when the first clock pulse CLK1 is supplied to the thirteenth NMOS transistor Tr13 of the first stage CST1, the thirteenth NMOS transistor Tr13 removes the first clock pulse CLK1. Outputs as one scan pulse (Vout1). In this case, since the first clock pulse CLK1 and the start pulse SP are superimposed and output, the first scan pulse Vout1 is superimposed on the start pulse SP and output.

The first scan pulse Vout1 is supplied to the first gate line and the second stage CST2. That is, the first scan pulse Vout1 from the first stage CST1 is supplied to the first, second, and third NMOS transistors Tr1, Tr2, and Tr3 of the second stage CST2. Accordingly, the first node Q of the second stage CST2 is charged, and the second and third nodes QB1 and QB2 are discharged. That is, the second stage CST2 is enabled by the first scan pulse Vout1. In other words, as the first stage CST1 is enabled by the start pulse SP, the second stage CST2 is enabled by the first scan pulse Vout1. In this state, when the second clock pulse CLK2 is supplied to the thirteenth NMOS transistor Tr13 of the second stage CST2, the thirteenth NMOS transistor Tr13 removes the second clock pulse CLK2. Outputs as 2 scan pulses (Vout2). In this case, since the second clock pulse CLK2 overlaps the first clock pulse CLK1, the second scan pulse Vout2 is output to overlap the first scan pulse Vout1.

The second scan pulse Vout2 is supplied to the second gate line and the third stage CST3. That is, the second scan pulse Vout2 from the second stage CST2 is supplied to the first, second, and third NMOS transistors Tr1, Tr2, and Tr3 of the third stage CST3. Accordingly, the first node Q of the third stage CST3 is charged, and the second and third nodes QB1 and QB2 are discharged. That is, the third stage CST3 is enabled by the second scan pulse Vout2. In other words, as the first stage CST1 is enabled by the start pulse SP, the third stage CST3 is enabled by the second scan pulse Vout2.

In this state, when the third clock pulse CLK3 is supplied to the thirteenth NMOS transistor Tr13 of the third stage CST3, the thirteenth NMOS transistor Tr13 removes the third clock pulse CLK3. Outputs as 3 scan pulses (Vout3). In this case, since the third clock pulse CLK3 overlaps the second clock pulse CLK2, the third scan pulse Vout3 is output to overlap the second scan pulse Vout2.

The third scan pulse Vout3 is supplied to the third gate line and the fourth stage CST4. That is, the third scan pulse Vout3 from the third stage CST3 is supplied to the first, second, and third NMOS transistors Tr1, Tr2, and Tr3 of the fourth stage CST4. Accordingly, the first node Q of the fourth stage CST4 is charged and the second and third nodes QB1 and QB2 are discharged. That is, the fourth stage CST4 is enabled by the third scan pulse Vout3. In other words, as the first stage CST1 is enabled by the start pulse SP, the fourth stage CST4 is enabled by the third scan pulse Vout3.

In this state, when the fourth clock pulse CLK4 is supplied to the thirteenth NMOS transistor Tr13 of the fourth stage CST4, the thirteenth NMOS transistor Tr13 removes the fourth clock pulse CLK4. Outputs as 4 scan pulses (Vout4). In this case, since the fourth clock pulse CLK4 overlaps the third clock pulse CLK3, the fourth scan pulse Vout4 is output to overlap the third scan pulse Vout3.

On the other hand, the third scan pulse Vout3 output from the third stage CST3 is also supplied to the twelfth NMOS transistor Tr12 of the first stage CST1. That is, the third scan pulse Vout3 is supplied to the gate terminal of the twelfth NMOS transistor Tr12 provided in the first stage CST1. Accordingly, the first stage CST1 is disabled.

In detail, the third scan pulse Vout3 turns on the twelfth NMOS transistor Tr12 included in the first stage CST1. Then, the second voltage source VSS is supplied to the first node Q of the first stage CST1 through the turned-on twelfth NMOS transistor Tr12. Accordingly, the first node Q of the first stage CST1 is discharged. Therefore, the eighth, ninth, and thirteenth NMOS transistors Tr8, Tr9, and Tr13 connected to the first node Q of the first stage CST1 are turned off. In addition, when the start pulse SP is changed to low, the first, second, and third NMOS transistors Tr1, Tr2, and the first stage CST1 of the first stage CST1 are supplied with the start pulse SP in the low state. Tr3) is turned off.

Here, since the second and eighth NMOS transistors Tr2 and Tr8 of the first stage CST1 are turned off, the second node QB1 of the first stage CST1 is the fourth NMOS transistor Tr4. Is charged to the first voltage source VDD. Accordingly, both the tenth and fourteenth NMOS transistors Tr10 and Tr14 having gate terminals connected to the second node QB1 of the first stage CST1 are turned on. At this time, the second voltage source VSS is supplied to the first gate line through the turned-on fourteenth NMOS transistor Tr14.

Meanwhile, the second voltage source VSS is supplied to the first node Q through the turned-on tenth NMOS transistor Tr10. As a result, the first node Q of the first stage CST1 is discharged by the tenth and twelfth NMOS transistors Tr10 and Tr12.

In this way, the first node Q and the third node QB2 of the first stage CST1 are discharged by the third scan pulse Vout3 from the third stage CST3, and the second node ( QB1) is charged. That is, the first stage CST1 is disabled in response to the third scan pulse Vout3 from the third stage CST3. The disabled first stage CST1 outputs the second voltage source VSS through the fourteenth NMOS transistor Tr14 provided therein. Then, the second voltage source VSS is supplied to the first gate line.

In this manner, each stage CST1 to CSTn + 2 is enabled by a scan pulse output from the previous stage from itself. Then, each stage CST1 to CSTn + 2 is disabled by the scan pulse from the stage located next to it.

On the other hand, the third voltage source VDD3 is maintained at the negative polarity and the fourth voltage source VDD4 is maintained at the positive polarity in the second frame. As a result, when the stages CST1 to CSTn + 2 are disabled, the second node QB1 of each stage CST1 to CSTn + 2 is discharged and the third node QB2 is charged. Therefore, when each of the stages CST1 to CSTn + 2 is disabled, the second voltage source VSS is output through the fifteenth NMOS transistor Tr15 having a gate terminal connected to the third node QB2. As such, since the second and third nodes QB1 and QB2 are alternately charged / discharged for each frame, deterioration of the 14th and 15th NMOS transistors Tr15 included in the output unit 100 is prevented. can do.

On the other hand, the stage may have a circuit configuration as follows.

FIG. 12 is another circuit diagram of the third stage of FIG. 8.

As illustrated in FIG. 12, the third stage CST3 includes a node controller 120a and an output unit 120b. The node control unit 120a includes first to thirteenth NMOS transistors Tr1 to Tr12 and sixteenth and seventeenth NMOS transistors Tr16 and Tr17. The output unit 120b includes thirteenth to fifteenth NMOS transistors Tr13 to Tr15. Here, the first to twelfth NMOS transistors Tr1 to Tr12 of the node control unit 120a are the same as the first to twelfth NMOS transistors Tr1 to Tr12 included in the node control unit 100a of FIG. 10. The thirteenth to fifteenth NMOS transistors Tr13 to Tr15 of the output unit 120b are the same as the thirteenth to fifteenth NMOS transistors Tr13 to Tr15 included in the output unit 100b of FIG. 10. That is, the third stage CST3 of FIG. 12 is the same as the third stage CST3 of FIG. 10, except that the third stage CST3 of FIG. 12 includes the sixteenth and seventeenth NMOS transistors Tr16 and Tr17. It is further provided.

The sixteenth NMOS transistor Tr16 charges the second node QB to the third voltage source VDD3 in response to the scan pulse from the next stage. To this end, the gate terminal of the sixteenth NMOS transistor Tr16 charges the second node QB to the third voltage source VDD3 in response to the fifth scan pulse from the fifth stage.

The seventeenth NMOS transistor Tr17 charges the third node QB2 to the fourth voltage source VDD4 in response to the scan pulse from the next stage. That is, the gate terminal of the seventeenth NMOS transistor Tr17 charges the third node QB2 to the fourth voltage source VDD4 in response to the fifth scan pulse from the fifth stage. To this end, the gate terminal of the seventeenth NMOS transistor Tr17 is connected to the fifth stage, the source terminal is connected to a power line for transmitting the fourth voltage source VDD4, and the drain terminal is connected to the third node QB2. ) Is connected.

That is, the 16th NMOS transistor Tr16, together with the fourth NMOS transistor Tr4, supplies the third voltage source VDD3 to the second node QB to further charge the second node QB. It's making progress fast. In addition, when the sixteenth NMOS transistor Tr17 and the fourth NMOS transistor Tr4 are used together, the channel width of the fourth NMOS transistor Tr4 may be reduced. As a result, it is possible to prevent deterioration of the fourth NMOS transistor Tr4 having a diode shape.

In addition, the seventeenth NMOS transistor Tr17, together with the sixth NMOS transistor Tr6, supplies the fourth voltage source VDD4 to the third node QB2 to further charge the third node QB2. It's making progress fast. In addition, when the seventeenth NMOS transistor Tr17 and the sixth NMOS transistor Tr6 are used together, the channel width of the sixth NMOS transistor Tr6 may be reduced. As a result, deterioration of the sixth NMOS transistor Tr6 having a diode shape can be prevented.

On the other hand, the stage may have a circuit configuration as follows.

FIG. 13 is another circuit diagram illustrating the third stage of FIG. 8.

The configuration of the third stage CST3 of FIG. 13 is the same as that of the stage CST3 of FIG. 12. However, the fifth NMOS transistor Tr5 of FIG. 13 has a configuration different from that of the fifth NMOS transistor Tr5 of FIG. 12. The seventh NMOS transistor Tr7 of FIG. 13 has a structure different from that of the seventh NMOS transistor Tr7 of FIG. 12.

That is, the fifth NMOS transistor Tr5 of FIG. 13 discharges the third node QB2 to the second voltage source VSS in response to the third voltage source VDD3 charged in the second node QB. To this end, the gate terminal of the fifth NMOS transistor Tr5 is connected to the second node QB, the source terminal is connected to the second node QB, and the drain terminal of the fifth voltage source VSS. It is connected to the power line to transmit.

The seventh NMOS transistor Tr7 of FIG. 13 discharges the second node QB to the second voltage source VSS in response to the fourth voltage source VDD4 charged in the third node QB2. To this end, the gate terminal of the seventh NMOS transistor Tr7 is connected to the third node QB2, the source terminal is connected to the second node QB, and the drain terminal of the seventh NMOS transistor Tr7 is connected to the second voltage source VSS. It is connected to the transmitting power line.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The shift register of the present invention as described above has the following effects.

The shift register of the present invention may have the effect of reducing the total number of stages by dividing the whole stages into at least two groups and supplying start pulses to each group individually. That is, since each group is driven individually by individual start pulses, the shift register of the present invention drives a relatively smaller number of stages than in the prior art. Thus, as the group is further divided and the number of stages belonging to the group is reduced, the shift register of the present invention has a longer time life.

Claims (18)

A shift register having a plurality of stages having different phases and sequentially outputted so as to overlap a predetermined interval, a scan pulse from a previous stage, and a plurality of stages outputting a scan pulse in response to a scan pulse from a next stage. To Each stage is embedded on the liquid crystal panel, A first switching element for charging the first node with a second voltage source in response to a start pulse or a scan pulse from a previous stage; A second switching element for discharging a second node to a first voltage source in response to the start pulse or a scan pulse from a previous stage; A third switching device configured to charge the second node with a second voltage source in response to a first clock pulse or a charging pulse synchronized with a scan pulse output from a next stage; A fourth switching element configured to discharge the first node to a first voltage source in response to a second voltage source charged in the second node; A fifth switching device configured to discharge the second node to the first voltage source in response to the second voltage source charged in the first node; A sixth switching element which discharges the first node to a first voltage source in response to a scan pulse from a next stage; A seventh switching element configured to output, as a scan pulse, a second clock pulse output before the first clock pulse in response to a second voltage source charged in the first node; And And an eighth switching device configured to output the first voltage source in response to the second voltage source charged in the second node. The method of claim 1, And the start pulse is supplied to a first stage which outputs a scan pulse first of the stages. Claim 3 has been abandoned due to the setting registration fee. The method of claim 1, The first to eighth switching element is an amorphous TFT (Thin Film Transistor) characterized in that the shift register. Responding to a plurality of clock pulses sequentially having different phases and overlapping a predetermined section, a plurality of charging pulses sequentially outputting different phases, a scan pulse from the previous stage, and a scan pulse from the next stage In the shift register having a plurality of stages for outputting a scan pulse, Each stage is embedded on the liquid crystal panel, A first switching element for charging the first node with a second voltage source in response to a start pulse or a scan pulse from a previous stage; A second switching element for discharging a second node to a first voltage source in response to the start pulse or a scan pulse from a previous stage; A third switching device configured to charge the second node with a second voltage source in response to a charging pulse; A fourth switching element configured to discharge the first node to a first voltage source in response to a second voltage source charged in the second node; A fifth switching device configured to discharge the second node to the first voltage source in response to the second voltage source charged in the first node; A sixth switching element which discharges the first node to a first voltage source in response to a scan pulse from a next stage; A seventh switching element which outputs a clock pulse output before the charging pulse as a scan pulse in response to a second voltage source charged in the first node; And And an eighth switching device configured to output the first voltage source in response to the second voltage source charged in the second node. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 4, wherein And the start pulse is supplied to a first stage which outputs a scan pulse first of the stages. Claim 6 has been abandoned due to the setting registration fee. The method of claim 4, wherein A shift register having a plurality of stages having different phases and sequentially outputted so as to overlap a predetermined interval, a scan pulse from a previous stage, and a plurality of stages outputting a scan pulse in response to a scan pulse from a next stage. To Each stage is embedded on the liquid crystal panel, A first switching element for charging the first node with a second voltage source in response to a start pulse or a scan pulse from a previous stage; A second switching element for discharging a second node to a first voltage source in response to a start pulse or a scan pulse from a previous stage; A third switching element for discharging the third node to the first voltage source in response to a start pulse or a scan pulse from a previous stage; A fourth switching element which is turned on or turned off in response to a third voltage source having a different polarity for each frame, and charges the second node with a third voltage source at turn-on; A fifth switching element that is turned on or off in response to the third voltage source and discharges the third node to the first voltage source when turned on; A sixth switching element turned on or off in response to a fourth voltage source having a polarity opposite to that of the third voltage source and charging the third node with the fourth voltage source at turn-on; A seventh switching element turned on or off in response to the fourth voltage source and discharging the second node to the first voltage source when turned on; An eighth switching element for discharging the second node to the first voltage source in response to the second voltage source charged to the first node; A ninth switching element configured to discharge the third node to the first voltage source in response to the second voltage source charged to the first node; A tenth switching element configured to discharge the first node to the first voltage source in response to the third voltage source charged in the second node; An eleventh switching element discharging the first node to the first voltage source in response to the fourth voltage source charged to the third node; A twelfth switching element for discharging the first node to the first voltage source in response to the scan pulse from the next stage; A thirteenth switching element configured to output a scan pulse in response to a second voltage source charged in the first node and to supply the scan pulse to the gate line, the next stage, and the previous stage; A fourteenth switching element configured to supply the first voltage source to the gate line in response to the third voltage source charged in the second node; And And a fifteenth switching element for supplying the first voltage source to the gate line in response to the fourth voltage source charged to the third node. The method of claim 7, wherein A sixteenth switching element that charges the second node with the third voltage source in response to a scan pulse from a next stage; And And a seventeenth switching element for charging the third node with the fourth voltage source in response to the scan pulse from the next stage. Claim 9 has been abandoned due to the setting registration fee. 9. The method of claim 8, And the start pulse is supplied to a first stage which outputs a scan pulse first of the stages. Claim 10 has been abandoned due to the setting registration fee. 9. The method of claim 8, And the first to seventeenth switching elements are amorphous thin film transistors (TFTs). A shift register having a plurality of stages having different phases and sequentially outputted so as to overlap a predetermined interval, a scan pulse from a previous stage, and a plurality of stages outputting a scan pulse in response to a scan pulse from a next stage. To Each stage is embedded on the liquid crystal panel, A second switching element for discharging a second node to a first voltage source in response to a start pulse or a scan pulse from a previous stage; A third switching element for discharging the third node to the first voltage source in response to a start pulse or a scan pulse from a previous stage; A fourth switching element which is turned on or turned off in response to a third voltage source having a different polarity for each frame, and charges the second node with a third voltage source at turn-on; A fifth switching device configured to discharge the third node to a first voltage source in response to a third voltage source charged in the second node; A sixth switching element which is turned on or off in response to a fourth voltage source having a polarity opposite to the third voltage source, and charges a third node to the fourth voltage source when turned on; A seventh switching element discharging the second node to a first voltage source in response to a fourth voltage source charged to the third node; An eighth switching element for discharging the second node to the first voltage source in response to the second voltage source charged to the first node; A ninth switching element configured to discharge the third node to the first voltage source in response to the second voltage source charged to the first node; A tenth switching element configured to discharge the first node to the first voltage source in response to the third voltage source charged in the second node; An eleventh switching element discharging the first node to the first voltage source in response to the fourth voltage source charged to the third node; A twelfth switching element for discharging the first node to the first voltage source in response to the scan pulse from the next stage; A thirteenth switching element configured to output a scan pulse in response to a second voltage source charged in the first node and to supply the scan pulse to the gate line, the next stage, and the previous stage; A fourteenth switching element configured to supply the first voltage source to the gate line in response to the third voltage source charged in the second node; And And a fifteenth switching element for supplying the first voltage source to the gate line in response to the fourth voltage source charged to the third node. The method of claim 11, wherein Each stage, A sixteenth switching element that charges the second node with the third voltage source in response to a scan pulse from a next stage; And And a seventeenth switching element for charging the third node with the fourth voltage source in response to the scan pulse from the next stage. Claim 13 was abandoned upon payment of a registration fee. 13. The method of claim 12, And the start pulse is supplied to a first stage which outputs a scan pulse first of the stages. Claim 14 has been abandoned due to the setting registration fee. 13. The method of claim 12, And the second to seventeenth switching elements are amorphous thin film transistors (TFTs). A shift register having a plurality of stages having different phases and sequentially outputted so as to overlap a predetermined interval, a scan pulse from a previous stage, and a plurality of stages outputting a scan pulse in response to a scan pulse from a next stage. To Each stage is embedded on the liquid crystal panel, A first switching element for charging the first node with a second voltage source in response to a start pulse or a scan pulse from a previous stage; A second switching element for discharging a second node to a first voltage source in response to a start pulse or a scan pulse from a previous stage; A third switching element for discharging the third node to the first voltage source in response to a start pulse or a scan pulse from a previous stage; A fourth switching element which is turned on or turned off in response to a third voltage source having a different polarity for each frame, and charges the second node with a third voltage source at turn-on; A fifth switching device configured to discharge the third node to a first voltage source in response to a third voltage source charged in the second node; A sixth switching element which is turned on or off in response to a fourth voltage source having a polarity opposite to the third voltage source, and charges a third node to the fourth voltage source when turned on; A seventh switching element discharging the second node to a first voltage source in response to a fourth voltage source charged to the third node; An eighth switching element for discharging the second node to the first voltage source in response to the second voltage source charged to the first node; A ninth switching element configured to discharge the third node to the first voltage source in response to the second voltage source charged to the first node; A tenth switching element configured to discharge the first node to the first voltage source in response to the third voltage source charged in the second node; An eleventh switching element discharging the first node to the first voltage source in response to the fourth voltage source charged to the third node; A twelfth switching element for discharging the first node to the first voltage source in response to the scan pulse from the next stage; A thirteenth switching element configured to output a scan pulse in response to a second voltage source charged in the first node and to supply the scan pulse to the gate line, the next stage, and the previous stage; A fourteenth switching element configured to supply the first voltage source to the gate line in response to the third voltage source charged in the second node; And And a fifteenth switching element for supplying the first voltage source to the gate line in response to the fourth voltage source charged to the third node. 16. The method of claim 15, Each stage, A sixteenth switching element that charges the second node with the third voltage source in response to a scan pulse from a next stage; And And a seventeenth switching element for charging the third node with the fourth voltage source in response to the scan pulse from the next stage. Claim 17 has been abandoned due to the setting registration fee. 17. The method of claim 16, And the start pulse is supplied to a first stage which outputs a scan pulse first of the stages. Claim 18 has been abandoned due to the setting registration fee. 17. The method of claim 16, And the first to seventeenth switching elements are amorphous thin film transistors (TFTs).

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