WO2023010614A1

WO2023010614A1 - Goa circuit and display panel

Info

Publication number: WO2023010614A1
Application number: PCT/CN2021/113145
Authority: WO
Inventors: 潘优
Original assignee: 武汉华星光电技术有限公司
Priority date: 2021-08-03
Filing date: 2021-08-18
Publication date: 2023-02-09
Also published as: CN113643669A; CN113643669B

Abstract

A GOA circuit and a display panel. The GOA circuit comprises a forward and reverse scanning control module (100), an output module (200), a potential regulation module (300), a node control module (400) and a voltage stabilization module (500). When a second node (P(N)) is at a second potential, a first node (Q(N)) and a third node (Qa(N)) are not turned on; and when the second node (P(N)) is at a third potential, the first node (Q(N)) and the third node (Qa(N)) are turned on and are at the second potential, wherein the second potential is opposite to the third potential. The problem of electricity leakage in an IP middle-stop stage in a GOA circuit can be eliminated.

Description

GOA circuit and display panel

technical field

The present application relates to the field of display technology, in particular to a GOA circuit and a display panel.

Background technique

Gate Driver On Array, referred to as GOA, is a technology that uses the existing thin-film transistor liquid crystal display Array process to fabricate the Gate line scan drive signal circuit on the Array substrate to realize the gate progressive scan drive method. Stopping in TP means that the GOA circuit including the ITP (In Cell Touch Panel, embedded touch screen) function needs to realize the function of pausing scanning during the display period.

In the GOA circuit in the related art, there is a leakage problem during the stop phase in TP.

technical problem

technical solution

The embodiment of the present application provides a GOA circuit and a display panel, which can improve the problem of leakage in the TP stop stage existing in the GOA circuit.

The embodiment of the present application provides a GOA circuit, including cascaded multi-level GOA units, N is a positive integer, except for the first level, second level, penultimate level and last level of GOA units, the Nth level Units include:

A forward and reverse scan control module, the forward and reverse scan control module accesses the forward scan signal and the reverse scan signal, and is electrically connected to the output end of the N-2th level GOA unit and the N+2th level GOA unit The output terminal and the first node are used to adjust the potential of the first node to first potential;

An output module, the output module includes a ninth thin film transistor, the gate of the ninth thin film transistor is electrically connected to the third node, the source is electrically connected to the Nth clock signal, and the drain is electrically connected to the output terminal;

A potential adjustment module, the potential adjustment module is connected to the N+2th clock signal, the N-2th clock signal, the forward scanning signal, the reverse scanning signal, the constant voltage high potential and the constant voltage low potential, and is electrically Connect the first node and the output terminal, used to adjust the potential of the first node to a constant voltage under the control of the N+2th clock signal, the N-2th clock signal, the forward scanning signal, and the reverse scanning signal Potential;

A node control module, the node control module is connected to a constant voltage potential and electrically connected to the first node and the second node;

A voltage stabilizing module, the voltage stabilizing module is connected to the first node, the third node, and the second node, and is used for when the second node is at the second potential, the first node and the third node are not conducted, and when the second node When the node is at the third potential, the first node and the third node are connected and are at the second potential, and the second potential is opposite to the third potential.

The embodiment of the present application also provides a GOA circuit, including cascaded multi-level GOA units, N is a positive integer, except for the first level, second level, penultimate level and last level of GOA units, the Nth level GOA units include:

A ninth thin film transistor, the gate of the ninth thin film transistor is electrically connected to the third node, the source is electrically connected to the Nth clock signal, and the drain is electrically connected to the output terminal;

A seventh thin film transistor, the source of the seventh thin film transistor is electrically connected to the first node, the gate is connected to the first node, and the drain is connected to the third node;

an eleventh thin film transistor, the source of the eleventh thin film transistor is electrically connected to the third node, the gate is connected to the second node, and the drain is connected to the first node;

When the GOA circuit enters the pause period, the seventh thin film transistor and the eleventh thin film transistor are in the off state, the potential of the first node is lowered, and the potential of the third node is maintained at the original high potential.

An embodiment of the present application further provides a display panel, including the GOA circuit described in any one of the above.

Beneficial effect

The GOA circuit of the embodiment of the present application includes cascaded multi-level GOA units. Let N be a positive integer. Except for the first-level, second-level, penultimate and last-level GOA units, the Nth-level GOA units include Forward and reverse scanning control module, output module, potential adjustment module, node control module and voltage stabilizing module. The voltage stabilizing module is connected to the first node, the third node, and the second node, so that when the second node is at the second potential, the first node and the third node are not conducted, and when the second node is at the third potential , the first node and the third node are turned on and are at the second potential, and the second potential and the third potential are opposite potentials. By setting a voltage stabilizing module with a voltage stabilizing effect, the outputs of the first node, the second node and the third node are normal during the stop phase, thereby improving the problem of leakage in the TP mid-stop phase existing in the GOA circuit.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a GOA circuit in the prior art.

FIG. 2 is a schematic diagram of the first structure of the GOA circuit provided by the embodiment of the present application.

FIG. 3 is a time sequence diagram of the GOA circuit shown in FIG. 2 when the function is transmitted in stages.

FIG. 4 is a schematic diagram of a second structure of the GOA circuit provided by the embodiment of the present application.

FIG. 5 is a schematic diagram of a third structure of the GOA circuit provided by the embodiment of the present application.

Embodiments of the present invention

Gate Driver On Array, referred to as GOA, is a technology that uses the existing thin-film transistor liquid crystal display Array process to fabricate the Gate line scan drive signal circuit on the Array substrate to realize the gate progressive scan drive method. Stopping in TP means that the GOA circuit including the ITP function needs to realize the function of pausing scanning during the display period. In the traditional embedded (In-Cell) touch screen technology, after displaying (display) scanning several rows of pixels in the AA (Active Area, active area/working area) area, the display scanning is stopped, and partial touch of the AA area is started. The (touch) electrode is scanned, and then the display scan and touch scan are alternated, and this process is repeated many times (the number of times depends on the specific product), so as to complete the display of a frame and the full-screen touch electrode scan. However, in the GOA circuit in the related art, there is a problem of electric leakage when the TP stops.

For example, please refer to FIG. 1 , which is a schematic structural diagram of a GOA circuit in the prior art. The existing GOA circuit works in the non-stop stage, the scanning signal Gate (N-2) of the N-2th GOA unit is at a high potential, the first thin film transistor T1 is turned on, the first node Q(N), the third The node Qa(N) changes to a high potential, the ninth thin film transistor T9 is turned on, and the Gate(N) is electrically connected to the Nth clock signal CK(N). When CK(N) is at a high potential, the Gate(N) outputs a high potential. The gate of this level is opened. When the N+2 clock signal CK (N+2) is at a high potential, the fourth node A is at a high potential, the eighth thin film transistor T8 is turned on, the second node P(N) is at a high potential, and the fifth thin film transistor T5 is turned on , the first node Q(N) and the third node Qa(N) turn to low potential, the ninth thin-film transistor T9 is turned off, and the tenth thin-film transistor T10 is turned on at the same time, Gate (N) is electrically connected to VGL, and the stage transmission ends . Assume that GOA enters the TP stop stage after the Gate (N-2) level output. As above, Gate (N-2) turns on a CK pulse (clock signal pulse) width. During this time, the first node Q (N) and the third node Qa (N) are connected to the forward scanning signal U2D and turn to a high potential. After Gate (N-2) is closed, the first node Q (N) and the third node Qa (N) maintain high potential until the end of TP stop, the Nth clock signal CK (N) is turned on, and Gate (N) outputs , CK(N+2) is turned on, the second node P(N) is high potential, the fifth thin film transistor T5 is turned on, the first node Q(N) and the third node Qa(N) are connected to VGL, the ninth thin film transistor T9 is turned off, and at the same time, the tenth thin film transistor T10 is turned on, the Gate (N) outputs a low potential, and the transmission of this stage is completed.

Double 85 work refers to working in an environment with a temperature of 85°C and a humidity of 85%, which is a common reliability life test method for panels. When the dual 85 is working, the fifth thin film transistor T5 is in a serious PBTS state (positive Voltage bias and temperature stress, positive bias voltage and temperature stress), Vgs=VGH-VGL, under long-term operation, the fifth thin film transistor T5 Vth negative drift or Ioff increases (referring to the Vgs-Ids curve of the thin film transistor TFT, Vth refers to the threshold voltage, Ioff refers to the off-state current, because long-term operation in the BTS (bias and temperature stress, bias and temperature stress) state, the characteristics of thin-film transistor TFT devices will deteriorate, and the common failure mechanism is Vth negative drift and Ioff increase). During the TP stop period, the potential of the first node Q(N) needs to be maintained at the VGH level, and the potential of the second node P(N) should be maintained at VGL. At this time, T5 Vgs=0. If T5 is under stress and causes Vgs=0V, Ioff is high In 10E-8A, there is a leakage path of the fifth thin film transistor T5 at the first node Q(N), so the VGH level of the first node Q(N) is pulled down, and the third node Qa(N) is connected to the first node Q (N) is connected, the VGH (high potential) of the third node Qa (N) is pulled down, the ninth thin film transistor T9 is not turned on well, the output of Gate (N) is insufficient, and the first thin film transistor T1 of the next stage GOA is turned on Poor, the potential of point Q(N+2) cannot be increased to a high potential, and the ninth thin film transistor T9 of the next stage cannot be turned on normally, resulting in the failure of GOA circuit stage transmission during the stop of the circuit during TP, that is, when the circuit is stopped during TP There is a leakage problem.

In order to solve the above problems, embodiments of the present application provide a GOA circuit and a display panel. The GOA circuit and the display panel will be described below with reference to the accompanying drawings.

The forward and reverse scanning control module, the forward and reverse scanning control module is connected to the forward scanning signal and the reverse scanning signal, and is electrically connected to the output end of the N-2nd level GOA unit and the output end of the N+2th level GOA unit And the first node is used to adjust the potential of the first node to the first node according to the potential of the output terminal of the N-2th GOA unit, the potential of the output terminal of the N+2th GOA unit, the forward scanning signal and the reverse scanning signal. Potential;

An output module, the output module includes a ninth thin film transistor; the gate of the ninth thin film transistor is electrically connected to the third node, the source is electrically connected to the Nth clock signal, and the drain is electrically connected to the output terminal;

The potential adjustment module, the potential adjustment module is connected to the N+2th clock signal, the N-2th clock signal, the forward scanning signal, the reverse scanning signal, the constant voltage high potential and the constant voltage low potential, and is electrically connected to the A node and an output terminal, used to adjust the potential of the first node to a constant voltage potential under the control of the N+2th clock signal, the N-2th clock signal, the forward scanning signal, and the reverse scanning signal;

A node control module, the node control module is connected to a constant voltage potential, and is electrically connected to the first node and the second node;

A voltage stabilizing module, the voltage stabilizing module is connected to the first node, the third node, and the second node, for when the second node is at the second potential, the first node and the third node are not conducted, and when the second node is at the second potential At the third potential, the first node and the third node are turned on and are at the second potential, and the second potential and the third potential are opposite potentials.

By setting a voltage stabilizing module with a voltage stabilizing effect, and when the second node is at the second potential, the first node and the third node are not conducting, and when the second node is at the third potential, the first node and the third node are conducting It is connected to the second potential, so that the outputs of the first node, the second node and the third node are normal during the stoppage stage, thereby improving the problem of TP stoppage leakage in the GOA circuit.

For example, please refer to FIG. 2 , which is a schematic diagram of a first structure of a GOA circuit provided by an embodiment of the present application. The embodiment of the present application provides a GOA circuit. The GOA circuit includes cascaded multi-level GOA units. Let N be a positive integer. Except for the first level, second level, penultimate level and last level of GOA units, The level GOA unit includes a forward and reverse scan control module 100 , an output module 200 , a potential adjustment module 300 , a node control module 400 and a voltage stabilization module 500 .

The forward and reverse scanning control module 100 accesses the forward scanning signal U2D and the reverse scanning signal D2U, and is electrically connected to the output terminal Gate (N-2) of the N-2th level GOA unit and the N+2th level GOA unit. The output terminal Gate(N+2) and the first node Q(N), the forward and reverse scanning control module 100 is used to control the potential of the output terminal Gate(N-2) according to the N-2th level GOA unit, the N+2th The potential of the output terminal Gate(N+2) of the stage GOA unit, the forward scan signal U2D and the reverse scan signal D2U pull up the potential of the first node Q(N).

The output module 200 includes a ninth thin film transistor T9; the gate of the ninth thin film transistor T9 is electrically connected to the third node Qa(N), the source is electrically connected to the Nth clock signal CK(N), and the drain is electrically connected to Output Gate(N).

The potential adjustment module 300 is connected to the N+2th clock signal CK(N+2), the N-2th clock signal CK(N-2), the forward scanning signal U2D, the reverse scanning signal D2U, the constant voltage high potential VGH and the constant voltage low potential VGL are electrically connected to the first node Q(N) and the output terminal Gate(N). The potential adjustment module 300 is used to control the N+2 clock signal CK(N+2), the N-2 clock signal CK(N-2), the forward scanning signal U2D, and the reverse scanning signal D2U, The potential of the first node Q(N) is pulled down to the constant low potential VGL, at this time the potential adjustment module 300 can be understood as a pull-down module.

The node control module 400 is connected to the constant voltage low potential VGL, and is electrically connected to the first node Q(N) and the second node P(N).

The voltage stabilizing module 500 is connected to the first node Q(N), the third node Qa(N), and the second node P(N), for when the second node P(N) is at a low potential, the first node Q( N) and the third node Qa(N) are non-conductive, and when the second node P(N) is high potential, the first node Q(N) and third node Qa(N) are conductive and low potential.

By setting the voltage stabilizing module 500 with a voltage stabilizing function, and when the second node P(N) is at a low potential, the first node Q(N) and the third node Qa(N) are not conducted, and the second node P( When N) is a high potential, the first node Q(N) and the third node Qa(N) are turned on and are low potential, so that the first node Q(N), the second node P(N) and the third node The output of Qa(N) is normal in the mid-stop phase, which improves the leakage problem in the TP mid-stop phase in the GOA circuit.

In order to illustrate the GOA circuit in the embodiment of the present application more clearly, each component module of the GOA circuit will be introduced below.

Exemplarily, please continue to refer to FIG. 2, the forward and reverse scan control module 100 may include a first thin film transistor T1 and a second thin film transistor T2, the gate of the first thin film transistor T1 is electrically connected to the N-2th level GOA unit The source of the output terminal Gate(N-2) is connected to the forward scanning signal U2D, and the drain is electrically connected to the first node Q(N). The gate of the second thin film transistor T2 is electrically connected to the output terminal Gate(N+2) of the N+2th GOA unit, the source is connected to the reverse scanning signal D2U, and the drain is electrically connected to the first node Q(N). .

The potential adjustment module 300 includes a third thin film transistor T3 , a fourth thin film transistor T4 , an eighth thin film transistor T8 , a fifth thin film transistor T5 and a tenth thin film transistor T10 . The gate of the third thin film transistor T3 is connected to the forward scanning signal U2D, the source is connected to the N+2th clock signal CK(N+2), and the drain is electrically connected to the drain of the fourth thin film transistor T4. The gate of the fourth thin film transistor T4 is connected to the reverse scanning signal D2U, and the source is connected to the N−2th clock signal CK(N−2). The gate of the eighth thin film transistor T8 is electrically connected to the drain of the third thin film transistor T3 , the source is connected to the constant voltage high potential VGH, and the drain is electrically connected to the second node P(N). The gate of the fifth thin film transistor T5 is electrically connected to the second node P(N), the source is electrically connected to the first node Q(N), and the drain is connected to the constant voltage low potential VGL. The gate of the tenth thin film transistor T10 is electrically connected to the second node P(N), the source is electrically connected to the output Gate(N), and the drain is connected to the constant voltage low potential VGL.

The node control module 400 includes a sixth thin film transistor T6, the gate of the sixth thin film transistor T6 is electrically connected to the first node Q(N), the source is electrically connected to the second node P(N), and the drain is connected to the constant voltage low Potential VGL.

The voltage stabilizing module 500 includes a seventh thin film transistor T7 and an eleventh thin film transistor T11. The source of the seventh thin film transistor T7 is electrically connected to the first node Q(N), the gate is connected to the first node Q(N), and the drain is connected to the first node Q(N). A third node Qa(N) is connected. The source of the eleventh thin film transistor T11 is electrically connected to the third node Qa(N), the gate is connected to the second node P(N), and the drain is connected to the first node Q(N). When the GOA circuit enters the pause scanning stage during the display period, that is, the TP stop stage, the seventh thin film transistor T7 and the eleventh thin film transistor T11 are in the off state, and when the potential of the first node Q(N) decreases, the third node Qa( N) Keep the original high potential. When the first thin film transistor T1 is turned on and the potential of the first node Q(N) is lowered, the third node Qa(N) is connected to the forward scanning signal U2D and is at a high level.

The GOA circuit further includes a first capacitor C1 and/or a second capacitor C2. One end of the first capacitor C1 is connected to the constant voltage low potential VGL, and the other end is electrically connected to the first node Q(N). One end of the second capacitor C2 is electrically connected to the second node P(N), and the other end is connected to the constant voltage low potential VGL.

It should be noted that, for the first-level GOA unit, the second-level GOA unit, the penultimate second-level GOA unit, and the last-level GOA unit, the circuit structures of the above-mentioned four GOA units are all the same as those of the above-mentioned Nth-level GOA unit. same. The difference between the above four GOA units and the Nth-level GOA units is that the gates of the first thin-film transistor T1 in the first-level GOA unit and the second-level GOA unit are all connected to the circuit start signal STV, and the rest are connected with other level GOA units. The GOA unit is the same. The gates of the second TFT T2 in the penultimate level of GOA units and the last level of GOA units are both connected to the circuit start signal STV, and the rest are the same as those of other levels of GOA units.

It should be noted that, since the conventional GOA circuit does not have the eleventh thin film transistor T11 for voltage stabilization and protection, there is a leakage path in the TP stop stage in the conventional GOA circuit.

In order to solve the above problems, the GOA circuit in the embodiment of the present application can resist double 85 working failure. Exemplarily, please refer to FIG. 3 in conjunction with FIG. 2 . FIG. 3 is a time sequence diagram of the GOA circuit shown in FIG. 2 when transferring functions in stages. When the GOA circuit works at the non-interruption level, the scanning signal Gate (N-2) of the N-2th level GOA unit is at a high potential, the first thin film transistor T1 is turned on, the first node Q(N), the third node Qa( N) changes to a high potential, the ninth thin film transistor T9 is turned on, and the output terminal Gate (N) is electrically connected to the Nth clock signal CK (N). When CK (N) is a high potential, the Gate (N) outputs a high potential. The stage Gate is turned on, when CK (N+2) is at high potential, the fourth node A(N) is at high potential, the eighth thin film transistor T8 is turned on, the second node P(N) is at high potential, and the fifth thin film transistor T5 is turned on , the first node Q(N) turns to a low potential, the eleventh thin film transistor T11 is turned on, the third node Qa(N) is connected to the first node Q(N), and the third node Qa(N) turns to a low potential, The ninth thin film transistor T9 is turned off, and the tenth thin film transistor T10 is turned on at the same time, the Gate (N) is electrically connected to the VGL, and the stage transmission is completed. Assume that GOA enters the TP stop stage after the Gate (N-2) level output. As above, Gate (N-2) turns on a CK pulse width. During this time, the first node Q(N) and the third node Qa(N) are connected to the forward scanning signal U2D and turn to high potential. Gate (N-2 ) is turned off, the first node Q(N) and the third node Qa(N) maintain a high potential until the end of the TP stop, CK(N) is turned on, Gate(N) is output, CK(N+2) is turned on, and the second The second node P(N) is at a high potential, the fifth thin film transistor T5 is turned on, the first node Q(N) and the third node Qa(N) are connected to VGL, the ninth thin film transistor T9 is turned off, and the tenth thin film transistor T10 is turned on , Gate (N) outputs a low potential, and the transmission of this stage is over.

It should be noted that, in the GOA circuit of the embodiment of the present application, the gate of the seventh thin film transistor T7 is reconnected to the first node Q(N), and the eleventh thin film transistor T11 is added and its gate is connected to the second node P ( N), the drain is connected to the third node Qa(N), and the source is connected to the first node Q(N). Under long-term operation, the Vth negative drift or Ioff of the fifth thin film transistor T5 increases, and during the TP stop period, the potential of the first node Q(N) decreases due to the leakage of the fifth thin film transistor T5, and the third node Qa(N) is still high potential, but at this time the seventh thin film transistor T7 is in the off state, the eleventh thin film transistor T11 is also in the off state, and the potential of the third node Qa(N) will not decrease, so it will not affect the opening of the ninth thin film transistor T9, GOA The output is fine. After the output of Gate (N) is completed, CK (N+2) is at high potential, Gate (N+2) is at high potential, the eighth thin film transistor T8 is turned on, the second node P(N) becomes high potential, the first node Q(N) is pulled into a low potential by the fifth thin film transistor T5 and the second thin film transistor T2, at this time the eleventh thin film transistor T11 is turned on, the third node Qa(N) is connected to the first node Q(N), and the ninth The thin film transistor T9 is turned off.

The embodiment of the present application also provides a GOA circuit, which can be referred to FIG. 4 . FIG. 4 is a second structural schematic diagram of the GOA circuit provided in the embodiment of the present application. The GOA circuit includes cascaded multi-level GOA units. Let N be a positive integer. Except for the first-level, second-level, penultimate and last-level GOA units, the Nth-level GOA unit can include a ninth thin film transistor. T9, the seventh thin film transistor T7 and the eleventh thin film transistor T11. The gate of the ninth thin film transistor T9 is electrically connected to the third node Qa(N), the source is electrically connected to the Nth clock signal, and the drain is electrically connected to the output terminal Gate(N). The source of the seventh thin film transistor T7 is electrically connected to the first node Q(N), the gate is connected to the first node Q(N), and the drain is connected to the third node Qa(N). The source of the eleventh thin film transistor T11 is electrically connected to the third node Qa(N), the gate is connected to the second node P(N), and the drain is connected to the first node Q(N). When the GOA circuit enters the pause scanning phase during the display period, that is, during the TP pause period, the seventh thin film transistor T7 and the eleventh thin film transistor T11 are in the off state, the potential of the first node Q(N) decreases, and the third node Qa(N) Keep the original high potential.

The GOA circuit also includes a first thin film transistor T1 and a second thin film transistor T2, the gate of the first thin film transistor T1 is electrically connected to the output terminal Gate (N-2) of the N-2th level GOA unit, and the source is connected to the positive The drain of the scan signal U2D is electrically connected to the first node Q(N). The gate of the second thin film transistor T2 is electrically connected to the output terminal Gate(N+2) of the N+2th GOA unit, the source is connected to the reverse scanning signal D2U, and the drain is electrically connected to the first node Q(N). . In the turn-on phase of the first thin film transistor T1, when the potential of the first node Q(N) drops, the third node Qa(N) is connected to the forward scanning signal U2D and is at a high level.

The GOA circuit further includes a third thin film transistor T3, a fourth thin film transistor T4, an eighth thin film transistor T8, a fifth thin film transistor T5, and a tenth thin film transistor T10. The gate of the third thin film transistor T3 is connected to the forward scanning signal U2D, and the source is connected to the N+2th clock signal CK(N+2). The gate of the fourth thin film transistor T4 is connected to the reverse scanning signal D2U, the source is connected to the N-2th clock signal CK(N-2), and the drain is electrically connected to the drain of the third thin film transistor T3. The gate of the eighth thin film transistor T8 is electrically connected to the drain of the third thin film transistor T3 , the source is connected to the constant voltage high potential VGH, and the drain is electrically connected to the second node P(N). The gate of the fifth thin film transistor T5 is electrically connected to the second node P(N), the source is electrically connected to the first node Q(N), and the drain is connected to the constant voltage low potential VGL. The gate of the tenth thin film transistor T10 is electrically connected to the second node P(N), the source is electrically connected to the output Gate(N), and the drain is connected to the constant voltage low potential VGL.

The GOA circuit also includes a sixth thin film transistor T6, the gate of the sixth thin film transistor T6 is electrically connected to the first node Q(N), the source is electrically connected to the second node P(N), and the drain is connected to a constant voltage low potential VGL.

It should be noted that for other structures of the GOA circuit provided in the embodiment of the present application, reference may be made to FIG. 2 and FIG. 3 and the above description, and details are not repeated here.

It should be noted that in the above-mentioned GOA circuit, the thin film transistors can all use NMOS (N-Metal-Oxide-Semiconductor, N-type metal-oxide-semiconductor/NMOS transistors), and the thin film transistors (or MOS transistors) are divided into N There are two types of channel and P channel, so MOS transistors are divided into P-type MOS transistors and N-type MOS transistors. Of course, PMOS (P-Metal-Oxide-Semiconductor, P-type Metal-Oxide-Semiconductor/PMOS transistor) may also be used.

For example, please refer to FIG. 5 , which is a third schematic structural diagram of the GOA circuit provided by the embodiment of the present application. The embodiment of the present application also provides a GOA circuit, including cascaded multi-level GOA units, N is a positive integer, except for the first level, second level, penultimate level and last level of GOA units, the Nth level GOA units include:

The forward and reverse scan control module 100, the forward and reverse scan control module 100 is connected to the forward scan signal U2D and the reverse scan signal D2U, and is electrically connected to the output terminal Gate (N-2) of the N-2th level GOA unit, The output terminal Gate(N+2) of the N+2th GOA unit and the first node Q(N) are used for the potential of the output terminal Gate(N-2) of the N-2th GOA unit, the N+th The potential of the output terminal Gate(N+2) of the 2-level GOA unit, the forward scanning signal U2D and the reverse scanning signal D2U pull down the potential of the first node Q(N).

The output module 200, the output module 200 includes a ninth thin film transistor T9; the gate of the ninth thin film transistor T9 is electrically connected to the third node Qa(N), the source is electrically connected to the Nth clock signal CK(N), and the drain The pole is electrically connected to the output terminal Gate (N).

The potential adjustment module 300 is connected to the N+2th clock signal CK(N+2), the N-2th clock signal CK(N-2), the forward scanning signal U2D, the reverse scanning signal D2U, the constant voltage high potential VGH and constant voltage low potential VGL are electrically connected to the first node Q(N) and the output terminal Gate(N) for the N+2 clock signal CK(N+2) and the N-2 clock Under the control of the signal CK(N−2), the forward scan signal U2D and the reverse scan signal D2U, the potential of the first node Q(N) is pulled up to the constant high potential VGH. At this time, the potential adjustment module 300 can be understood as a pull-up module.

The node control module 400, the node control module 400 is connected to the constant voltage high potential VGH, and is electrically connected to the first node Q(N) and the second node P(N).

The voltage stabilizing module 500, the voltage stabilizing module 500 is connected to the first node Q(N), the third node Qa(N), and the second node P(N), for when the second node P(N) is at a high potential, The first node Q(N) and the third node Qa(N) are not conducting, and when the second node P(N) is at a low potential, the first node Q(N) and the third node Qa(N) are conducting And for high potential.

Among them, the description of each module can be combined with Fig. 2 and Fig. 3 and refer to the above description, the difference is that the gate Gate of the NMOS transistor is turned on when the potential is high, and the gate Gate of the PMOS transistor is turned on when the potential is low, so here No longer.

By setting the voltage stabilizing module 500 with a voltage stabilizing function, and when the second node P(N) is at a high potential, the first node Q(N) and the third node Qa(N) are not conducted, and the second node P( When N) is a low potential, the first node Q(N) and the third node Qa(N) are turned on and are high potential, so that the first node Q(N), the second node P(N) and the third node The output of Qa(N) is normal in the mid-stop phase, which improves the leakage problem in the TP mid-stop phase in the GOA circuit.

The embodiment of the present application also provides a display panel, the display panel includes a GOA circuit, and the GOA circuit is used to drive the display panel to work. Regarding the GOA circuit, reference may be made to FIG. 2 to FIG. 5 and the above description, and details are not repeated here. By setting the voltage stabilizing module 500 with a voltage stabilizing function, and when the second node P(N) is at the second potential, the first node Q(N) and the third node Qa(N) are not conducted, and the second node P When (N) is the third potential, the first node Q(N) and the third node Qa(N) are turned on and are at the second potential, and the second potential and the third potential are opposite potentials, so that the first node Q The outputs of (N), the second node P(N) and the third node Qa(N) are normal during the stop phase, thereby improving the leakage problem in the TP mid-stop phase existing in the GOA circuit.

The GOA circuit and the display panel provided by the embodiments of the present application have been introduced in detail above. In this paper, specific examples are used to illustrate the principles and implementation methods of the present application, and the descriptions of the above embodiments are only used to help understand the present application. At the same time, for those skilled in the art, based on the idea of this application, there will be changes in the specific implementation and application scope. In summary, the content of this specification should not be construed as limiting the application.

Claims

A kind of GOA circuit, wherein, comprise the multistage GOA unit of cascading, set N to be positive integer, except the GOA unit of the first level, the second level, the penultimate level and the last level, the Nth level GOA unit includes :

A forward and reverse scan control module, the forward and reverse scan control module accesses the forward scan signal and the reverse scan signal, and is electrically connected to the output end of the N-2th level GOA unit and the N+2th level GOA unit The output terminal and the first node are used to adjust the potential of the first node to first potential;

An output module, the output module includes a ninth thin film transistor, the gate of the ninth thin film transistor is electrically connected to the third node, the source is electrically connected to the Nth clock signal, and the drain is electrically connected to the output terminal;

A potential adjustment module, the potential adjustment module is connected to the N+2th clock signal, the N-2th clock signal, the forward scanning signal, the reverse scanning signal, the constant voltage high potential and the constant voltage low potential, and is electrically Connect the first node and the output terminal, used to adjust the potential of the first node to a constant voltage under the control of the N+2th clock signal, the N-2th clock signal, the forward scanning signal, and the reverse scanning signal Potential;

A node control module, the node control module is connected to a constant voltage potential and electrically connected to the first node and the second node;

A voltage stabilizing module, the voltage stabilizing module is connected to the first node, the third node, and the second node, and is used for when the second node is at the second potential, the first node and the third node are not conducted, and when the second node When the node is at the third potential, the first node and the third node are connected and are at the second potential, and the second potential is opposite to the third potential.
The GOA circuit according to claim 1, wherein the forward and reverse scanning control module is used for forward scanning according to the potential of the output terminal of the N-2th GOA unit and the potential of the output terminal of the N+2th GOA unit The signal and the reverse scanning signal pull up the potential of the first node to the first potential;

The potential adjustment module is used to pull down the potential of the first node to a constant low potential under the control of the N+2th clock signal, the N-2th clock signal, the forward scanning signal, and the reverse scanning signal;

The node control module is connected to a constant voltage low potential;

The voltage stabilizing module is used for when the second node is at a low potential, the first node and the third node are not conducted, and when the second node is at a high potential, the first node and the third node are conducted and are at a low potential .
The GOA circuit according to claim 2, wherein the voltage stabilizing module includes a seventh thin film transistor and an eleventh thin film transistor, the source of the seventh thin film transistor is electrically connected to the first node, and the gate is connected to the The first node, the drain is connected to the third node; the source of the eleventh thin film transistor is electrically connected to the third node, the gate is connected to the second node, and the drain is connected to the first node.
The GOA circuit according to claim 3, wherein, when the GOA circuit enters the pause scanning phase during the display period, the seventh thin film transistor and the eleventh thin film transistor are in the off state, and when the potential of the first node is lowered, the third node remains the same high potential.
The GOA circuit according to claim 2, wherein the forward and reverse scanning control module includes a first thin film transistor and a second thin film transistor, and the gate of the first thin film transistor is electrically connected to the N-2th level GOA unit The output terminal of the TFT, the source is connected to the forward scanning signal, and the drain is electrically connected to the first node; the gate of the second thin film transistor is electrically connected to the output terminal of the N+2th level GOA unit, and the source is connected to the reverse To the scan signal, the drain is electrically connected to the first node.
The GOA circuit according to claim 5, wherein when the first thin film transistor is turned on, when the potential of the first node is lowered, the third node is connected to the forward scanning signal and is at a high level.
The GOA circuit according to claim 6, wherein the potential adjustment module includes a third thin film transistor, a fourth thin film transistor, an eighth thin film transistor, a fifth thin film transistor, and a tenth thin film transistor; the third thin film transistor The gate is connected to the forward scanning signal, the source is connected to the N+2th clock signal, and the drain is electrically connected to the drain of the fourth thin film transistor; the gate of the fourth thin film transistor is connected to the reverse scanning signal, The source is connected to the N-2th clock signal; the gate of the eighth thin film transistor is electrically connected to the drain of the third thin film transistor, the source is connected to a constant voltage high potential, and the drain is electrically connected to the second node; The gate of the fifth thin film transistor is electrically connected to the second node, the source is electrically connected to the first node, and the drain is connected to a constant voltage low potential; the gate of the tenth thin film transistor is electrically connected to the second node, The source is electrically connected to the output terminal, and the drain is connected to a constant voltage low potential.
The GOA circuit according to claim 7, wherein the node control module includes a sixth thin film transistor, the gate of the sixth thin film transistor is electrically connected to the first node, the source is electrically connected to the second node, and the drain is electrically connected to the second node. Access to constant voltage low potential.
The GOA circuit according to claim 1, wherein the GOA circuit further comprises:

A first capacitor, one end of the first capacitor is connected to a constant voltage low potential, and the other end is electrically connected to the first node; and/or

A second capacitor, one end of the second capacitor is electrically connected to the second node, and the other end is connected to a constant voltage low potential.
The GOA circuit according to claim 8, wherein, when the GOA circuit is working in the display period scanning phase, the GOA circuit is used for:

When the potential of the output terminal of the N-2th level GOA unit is a high potential, the first thin film transistor is turned on, the first node and the third node are changed to a high potential, the ninth thin film transistor is turned on, and the output terminal is connected to the Nth The clock signals are electrically connected, and if the Nth clock signal is at a high potential, the output terminal outputs a high potential;

If the N+2th clock signal is at a high potential, the fourth node is at a high potential, the eighth thin film transistor is turned on, the second node is at a high potential, the fifth thin film transistor is turned on, and the first node turns to a low potential , the eleventh thin film transistor is turned on, the first node is connected to the third node, the third node turns to a low potential, the ninth thin film transistor is turned off, and the tenth thin film transistor is turned on at the same time, and the output terminal is connected to the constant voltage low Potential electrical connection.
The GOA circuit according to claim 1, wherein the forward and reverse scanning control module is used for forward scanning according to the potential of the output terminal of the N-2th GOA unit and the potential of the output terminal of the N+2th GOA unit The signal and the reverse scanning signal pull down the potential of the first node to the first potential;

The potential adjustment module is used to pull up the potential of the first node to a constant voltage high potential under the control of the N+2th clock signal, the N-2th clock signal, the forward scanning signal, and the reverse scanning signal ;

The node control module is connected to a constant voltage high potential;

The voltage stabilizing module is used for when the second node is at a high potential, the first node and the third node are not conducting, and when the second node is at a low potential, the first node and the third node are conducting and are at a high potential .
A kind of GOA circuit, wherein, comprise the multistage GOA unit of cascading, set N to be positive integer, except the GOA unit of the first level, the second level, the penultimate level and the last level, the Nth level GOA unit includes :

A ninth thin film transistor, the gate of the ninth thin film transistor is electrically connected to the third node, the source is electrically connected to the Nth clock signal, and the drain is electrically connected to the output terminal;

A seventh thin film transistor, the source of the seventh thin film transistor is electrically connected to the first node, the gate is connected to the first node, and the drain is connected to the third node;

an eleventh thin film transistor, the source of the eleventh thin film transistor is electrically connected to the third node, the gate is connected to the second node, and the drain is connected to the first node;

When the GOA circuit enters the pause period, the seventh thin film transistor and the eleventh thin film transistor are in the off state, the potential of the first node is lowered, and the potential of the third node is maintained at the original high potential.
The GOA circuit according to claim 12, wherein the GOA circuit further comprises:

A first thin film transistor, the gate of the first thin film transistor is electrically connected to the output terminal of the N-2th level GOA unit, the source is connected to the forward scanning signal, and the drain is electrically connected to the first node;

The second thin film transistor, the gate of the second thin film transistor is electrically connected to the output end of the N+2th level GOA unit, the source is connected to the reverse scanning signal, and the drain is electrically connected to the first node.
The GOA circuit according to claim 13, wherein, in the turn-on phase of the first thin film transistor, when the potential of the first node is lowered, the third node is connected to the forward scanning signal and is at a high level.
The GOA circuit according to claim 14, wherein the GOA circuit further comprises:

The third thin film transistor, the gate of the third thin film transistor is connected to the forward scanning signal, and the source is connected to the N+2th clock signal;

A fourth thin film transistor, the gate of the fourth thin film transistor is connected to the reverse scanning signal, the source is connected to the N-2th clock signal, and the drain is electrically connected to the drain of the third thin film transistor;

An eighth thin film transistor, the gate of the eighth thin film transistor is electrically connected to the drain of the third thin film transistor, the source is connected to a constant voltage high potential, and the drain is electrically connected to the second node;

The fifth thin film transistor, the gate of the fifth thin film transistor is electrically connected to the second node, the source is electrically connected to the first node, and the drain is connected to a constant voltage low potential; and

The tenth thin film transistor, the gate of the tenth thin film transistor is electrically connected to the second node, the source is electrically connected to the output terminal, and the drain is connected to a constant voltage low potential.
The GOA circuit according to claim 15, wherein the GOA circuit further comprises a sixth thin film transistor, the gate of the sixth thin film transistor is electrically connected to the first node, the source is electrically connected to the second node, and the drain is electrically connected to the second node. Access to constant voltage low potential.
The GOA circuit according to claim 12, wherein the GOA circuit further comprises:

A first capacitor, one end of the first capacitor is connected to a constant voltage low potential, and the other end is electrically connected to the first node; and/or

A second capacitor, one end of the second capacitor is electrically connected to the second node, and the other end is connected to a constant voltage low potential.
The GOA circuit according to claim 16, wherein, when the GOA circuit is working in the scanning phase during display, the GOA circuit is used for:

When the potential of the output terminal of the N-2th level GOA unit is a high potential, the first thin film transistor is turned on, the first node and the third node are changed to a high potential, the ninth thin film transistor is turned on, and the output terminal is connected to the Nth The clock signals are electrically connected, and if the Nth clock signal is at a high potential, the output terminal outputs a high potential;

If the N+2th clock signal is at a high potential, the fourth node is at a high potential, the eighth thin film transistor is turned on, the second node is at a high potential, the fifth thin film transistor is turned on, and the first node turns to a low potential , the eleventh thin film transistor is turned on, the first node is connected to the third node, the third node turns to a low potential, the ninth thin film transistor is turned off, and the tenth thin film transistor is turned on at the same time, and the output terminal is connected to the constant voltage low Potential electrical connection.
A display panel, which includes a GOA circuit, the GOA circuit includes cascaded multi-level GOA units, N is a positive integer, except for the first level, second level, penultimate level and last level of GOA units , the Nth-level GOA unit includes:

A forward and reverse scan control module, the forward and reverse scan control module accesses the forward scan signal and the reverse scan signal, and is electrically connected to the output end of the N-2th level GOA unit and the N+2th level GOA unit The output terminal and the first node are used to adjust the potential of the first node to first potential;

An output module, the output module includes a ninth thin film transistor, the gate of the ninth thin film transistor is electrically connected to the third node, the source is electrically connected to the Nth clock signal, and the drain is electrically connected to the output terminal;

A potential adjustment module, the potential adjustment module is connected to the N+2th clock signal, the N-2th clock signal, the forward scanning signal, the reverse scanning signal, the constant voltage high potential and the constant voltage low potential, and the electrical Connecting the first node and the output terminal, it is used to adjust the potential of the first node to a constant voltage under the control of the N+2th clock signal, the N-2th clock signal, the forward scanning signal, and the reverse scanning signal Potential;

A node control module, the node control module is connected to a constant voltage potential and electrically connected to the first node and the second node;

A voltage stabilizing module, the voltage stabilizing module is connected to the first node, the third node, and the second node, and is used to make the first node and the third node non-conductive when the second node is at the second potential, and when the second node When the node is at the third potential, the first node and the third node are connected and are at the second potential, and the second potential is opposite to the third potential.
The display panel according to claim 19, wherein the forward and reverse scan control module is used for forward scan The signal and the reverse scanning signal pull up the potential of the first node to the first potential;

The potential adjustment module is used to pull down the potential of the first node to a constant low potential under the control of the N+2th clock signal, the N-2th clock signal, the forward scanning signal, and the reverse scanning signal;

The node control module is connected to a constant voltage low potential;

The voltage stabilizing module is used for when the second node is at a low potential, the first node and the third node are not conducted, and when the second node is at a high potential, the first node and the third node are conducted and are at a low potential .