WO2021012313A1 - Gate driving circuit - Google Patents

Gate driving circuit Download PDF

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Publication number
WO2021012313A1
WO2021012313A1 PCT/CN2019/099332 CN2019099332W WO2021012313A1 WO 2021012313 A1 WO2021012313 A1 WO 2021012313A1 CN 2019099332 W CN2019099332 W CN 2019099332W WO 2021012313 A1 WO2021012313 A1 WO 2021012313A1
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WO
WIPO (PCT)
Prior art keywords
output terminal
signal output
node
transistor
gate
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PCT/CN2019/099332
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French (fr)
Chinese (zh)
Inventor
薛炎
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2021012313A1 publication Critical patent/WO2021012313A1/en

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays

Definitions

  • the present invention relates to the field of display technology, and in particular to a gate driving circuit for a display panel.
  • the gate driver on array (GOA) technology on the array substrate is the row drive technology of the array substrate.
  • the gate scan drive circuit is fabricated on the thin film transistor array substrate to realize the progressive scan driving mode.
  • the node QB is the gate point of the transistor that maintains the output signal at a low level. During the display of one frame, the node QB almost maintains a high potential, so that the transistor controlled by the node QB is always in the on state.
  • IGZO Indium Gallium Zinc Oxide
  • the transistor When the transistor is operated for a long time, especially for the indium gallium zinc oxide transistor, its threshold voltage is prone to drift, causing the gate drive circuit to fail.
  • the object of the present invention is to provide a gate drive circuit, which can avoid the threshold voltage drift of the transistor and ensure the normal operation of the gate drive circuit.
  • the present invention provides a gate driving circuit including a plurality of cascaded gate driving units, wherein the gate driving unit includes: a pull-up control unit, the pull-up control unit is connected to a first node , The second node, the first clock signal, the scan signal output terminal, the transmission signal output terminal of the current stage and the previous stage transmission signal output terminal; a pull-down maintaining unit, the pull-down maintaining unit is connected to the first node and the first node Two nodes, the feedback signal output terminal of the current stage, the feedback signal output terminal of the next stage, the scan signal output terminal, the signal output terminal of the current stage, the first DC high voltage, the first DC low voltage and the second Two DC low voltage; a pull-up unit, the pull-up unit is connected to the first node, the second clock signal and the scan signal output terminal; a downstream unit, the downstream unit is connected to the first node, the The second clock signal, the second DC high voltage, the feedback signal output terminal of the current stage, and the transmission signal output terminal;
  • the first clock signal and the second clock signal are AC signals with opposite waveforms.
  • the pull-up control unit includes: a first transistor, the gate of which is connected to the first clock signal, the source of which is connected to the output terminal of the previous stage transmission signal, and the drain of which is connected to the first Two nodes; a second transistor whose gate is connected to the first clock signal, its source is connected to the second node, and its drain is connected to the first node; and a third transistor whose gate is connected to the present
  • the step-by-step transmission signal output terminal has its source connected to the scan signal output terminal and its drain connected to the second node.
  • the source of the first transistor receives the trigger signal through the signal output terminal of the previous stage.
  • the pull-up unit includes a fourth transistor whose gate is connected to the first node, its source is connected to the second clock signal, and its drain is connected to the scan signal output terminal.
  • the downstream unit includes: a fifth transistor whose gate is connected to the first node, its source is connected to the second DC high voltage, and its drain is connected to the feedback signal output of the current stage And a sixth transistor, the gate of which is connected to the first node, the source of which is connected to the second clock signal, and the drain of which is connected to the signal output terminal of the current stage.
  • the pull-down unit includes: a seventh transistor, the gate of which is connected to the next-stage signal output terminal, the source of which is connected to the scan signal output terminal, and the drain of which is connected to the second
  • the eighth transistor the gate of which is connected to the output terminal of the next-stage signal transmission, the source of which is connected to the first node, and the drain of which is connected to the second node
  • the ninth transistor the gate of which The pole is connected to the output terminal of the next-stage transmission signal, the source is connected to the second node, and the drain is connected to the first DC low voltage.
  • the pull-down sustain unit includes: a tenth transistor, the gate of which is connected to the third node, the source of which is connected to the scan signal output terminal, and the drain of which is connected to the second DC low voltage; A transistor whose gate is connected to the third node, its source is connected to the signal output terminal of the current stage, and its drain is connected to the first DC low voltage; a twelfth transistor, whose gate is connected to all The third node has its source connected to the feedback signal output terminal of the current stage, and its drain connected to the first DC low voltage; a thirteenth transistor has its gate connected to the third node and its source connected to The first node has its drain connected to the second node; the fourteenth transistor has its gate connected to the third node, its source connected to the second node, and its drain connected to the first node.
  • a fifteenth transistor, its gate and source are connected to the first DC high voltage, and its drain is connected to the third node; a sixteenth transistor, its gate and source are connected to the lower The first-level feedback signal output terminal, the drain of which is connected to the third node; and the seventeenth transistor, the gate of which is connected to the first node, the source of which is connected to the third node, and the drain of which is connected to the third node.
  • the second DC low voltage is greater than the first DC low voltage.
  • the second DC high voltage is greater than the first DC high voltage and greater than the high potential of the second clock signal.
  • the present invention also provides a gate driving circuit including a plurality of cascaded gate driving units, wherein the gate driving unit includes:
  • a pull-up control unit, the pull-up control unit is connected to the first node, the second node, the first clock signal, the scan signal output terminal, the current stage transmission signal output terminal and the previous stage transmission signal output terminal;
  • a pull-down maintaining unit which is connected to the first node, the second node, the feedback signal output terminal of the current stage, the feedback signal output terminal of the next stage, the scan signal output terminal, and the current stage transmission Signal output terminal, first direct current high voltage, first direct current low voltage and second direct current low voltage;
  • a pull-up unit, the pull-up unit is connected to the first node, the second clock signal, and the scan signal output terminal;
  • a downstream unit which is connected to the first node, the second clock signal, the second DC high voltage, the feedback signal output terminal of the current stage, and the transmission signal output terminal of the current stage;
  • the pull-down unit is connected to the first node, the second node, the scan signal output terminal, the next-stage transmission signal output terminal, the first direct current low voltage, and the second direct current Low voltage;
  • a bootstrap capacitor one end of which is connected to the first node, and the other end of which is connected to the scan signal output terminal;
  • first clock signal and the second clock signal are AC signals with opposite waveforms; the second DC low voltage is greater than the first DC low voltage; the second DC high voltage is greater than the The first DC high voltage is greater than the high potential of the second clock signal.
  • the invention can avoid the threshold voltage drift of the transistor and ensure the normal operation of the gate drive circuit.
  • FIG. 1 is a schematic diagram of the circuit structure of a gate driving circuit according to an embodiment of the present invention
  • FIG. 2 is a working timing diagram of the gate driving circuit shown in FIG. 1.
  • FIG. 1 shows a schematic diagram of a circuit structure of a gate driving circuit according to an embodiment of the present invention.
  • the gate driving circuit includes a plurality of cascaded gate driving units 1.
  • the gate driving unit 1 includes a pull-up unit 100, a pull-up control unit 200, a downstream unit 300, a pull-down unit 400, a pull-down sustain unit 500, and a bootstrap capacitor Cbt.
  • the first clock signal CK1 and the second clock signal CK2 are AC signals with opposite waveforms.
  • the second DC low voltage VGL2 is greater than the first DC low voltage VGL1;
  • the second DC high voltage VGH2 is greater than the first DC high voltage VGH1 and is greater than the high potential of the second clock signal CK2.
  • the pull-up unit 100 is connected to the first node Q, the second clock signal CK2, and the scan signal output terminal G(n).
  • the pull-up unit 100 includes a fourth transistor T21, the gate of the fourth transistor T21 is connected to the first node Q, the source of the fourth transistor T21 is connected to the second clock signal CK2, and the drain of the fourth transistor T21 is connected to the scan signal output terminal G (n).
  • the pull-up control unit 200 is connected to the first node Q, the second node N, the first clock signal CK1, the scan signal output terminal G(n), the transmission signal output terminal Cout(n) of the current stage and the front
  • the signal output terminal Cout(n-1) is transmitted in stages.
  • the pull-up control unit 200 includes a first transistor T11, a second transistor T12, and a third transistor T6.
  • the gate of the first transistor T11 is connected to the first clock signal CK1
  • the source of the first transistor T11 is connected to the previous stage transmission signal output terminal Cout(n-1)
  • the drain of the first transistor T11 is connected to the second node N.
  • the gate of the second transistor T12 is connected to the first clock signal CK1, the source of the second transistor T12 is connected to the second node N, and the drain of the second transistor T12 is connected to the first node Q.
  • the gate of the third transistor T6 is connected to the signal output terminal Cout(n) of the current stage, the source of the third transistor T6 is connected to the scan signal output terminal G(n), and the drain of the third transistor T6 is connected to the second node N.
  • the download unit 300 is connected to the first node Q, the second clock signal CK2, the second DC high voltage VGH2, the feedback signal output terminal Out(n) of the current stage, and the transmission signal output terminal Cout(n ).
  • the downstream unit 300 includes a fifth transistor T23 and a sixth transistor T22.
  • the gate of the fifth transistor T23 is connected to the first node Q, the source of the fifth transistor T23 is connected to the second DC high voltage VGH2, and the drain of the fifth transistor T23 is connected to the feedback signal output terminal Out(n) of this stage.
  • the gate of the sixth transistor T22 is connected to the first node Q, the source of the sixth transistor T22 is connected to the second clock signal CK2, and the drain of the sixth transistor T22 is connected to the signal output terminal Cout(n) of the current stage.
  • the pull-down unit 400 is connected to the first node Q, the second node N, the scan signal output terminal G(n), the next stage transmission signal output terminal Cout(n+1), and the first DC low voltage VGL1 and the second DC low voltage VGL2.
  • the pull-down unit 400 includes a seventh transistor T31, an eighth transistor T32, and a ninth transistor T33.
  • the gate of the seventh transistor T31 is connected to the next stage signal output terminal Cout(n+1), the source of the seventh transistor T31 is connected to the scanning signal output terminal G(n), and the drain of the seventh transistor T31 is connected to the second DC low voltage VGL2.
  • the gate of the eighth transistor T32 is connected to the next stage signal output terminal Cout(n+1), the source of the eighth transistor T32 is connected to the first node Q, and the drain of the eighth transistor T32 is connected to the second node N.
  • the gate of the ninth transistor T33 is connected to the next-stage signal output terminal Cout(n+1), the source of the ninth transistor T33 is connected to the second node N, and the drain of the ninth transistor T33 is connected to the first DC low voltage VGL1.
  • the pull-down maintenance unit 500 is connected to the first node Q, the second node N, the feedback signal output terminal Out(n) of the current stage, the feedback signal output terminal Out(n+1) of the next stage, and the scan signal output terminal.
  • G(n) the signal output terminal Cout(n) of the current stage, the first DC high voltage VGH1, the first DC low voltage VGL1, and the second DC low voltage VGL2.
  • the pull-down sustain unit 500 includes a tenth transistor T41, an eleventh transistor T42, a twelfth transistor T43, a thirteenth transistor T44, a fourteenth transistor T45, a fifteenth transistor T51, a sixteenth transistor T52, and a seventeenth transistor T53.
  • the gate of the tenth transistor T41 is connected to the third node QB, the source of the tenth transistor T41 is connected to the scan signal output terminal G(n), and the drain of the tenth transistor T41 is connected to the second DC low voltage VGL2.
  • the gate of the eleventh transistor T42 is connected to the third node QB, the source of the eleventh transistor T42 is connected to the signal output terminal Cout(n) of the current stage, and the drain of the eleventh transistor T42 is connected to the first DC low voltage VGL1.
  • the gate of the twelfth transistor T43 is connected to the third node QB, the source of the twelfth transistor T43 is connected to the feedback signal output terminal Out(n) of the current stage, and the drain of the twelfth transistor T43 is connected to the first DC low voltage VGL1 .
  • the gate of the thirteenth transistor T44 is connected to the third node QB, the source of the thirteenth transistor T44 is connected to the first node Q, and the drain of the thirteenth transistor T44 is connected to the second node N.
  • the gate of the fourteenth transistor T45 is connected to the third node QB, the source of the fourteenth transistor T45 is connected to the second node N, and the drain of the fourteenth transistor T45 is connected to the first DC low voltage VGL1.
  • the gate and source of the fifteenth transistor T51 are connected to the first DC high voltage VGH1, and the drain of the fifteenth transistor T51 is connected to the third node QB.
  • the gate and source of the sixteenth transistor T52 are connected to the next-stage feedback signal output terminal Out(n+1), and the drain of the sixteenth transistor T52 is connected to the third node QB.
  • the gate of the seventeenth transistor T53 is connected to the first node Q, the source of the seventeenth transistor T53 is connected to the third node QB, and the drain of the seventeenth transistor T53 is connected to the first DC low voltage VGL1.
  • one end of the bootstrap capacitor Cbt is connected to the first node Q, and the other end of the bootstrap capacitor Cbt is connected to the scan signal output terminal G(n).
  • FIG. 2 is a working timing diagram of the gate driving circuit shown in FIG. 1.
  • the source of the first transistor T11 receives the trigger signal STV through the signal output terminal Cout(n-1) of the previous stage.
  • the previous stage transmission signal output terminal Cout(n-1) and the first clock signal CK1 are at high potential, the first transistor T11 and the second transistor T12 are turned on, and the potential of the first node Q is raised to a high potential.
  • the fourth transistor T21, the sixth transistor T22, the fifth transistor T23, and the seventeenth transistor T53 are turned on, the third node QB is pulled down to a low potential, the tenth transistor T41, the eleventh transistor T42, and the twelfth transistor T43, The thirteenth transistor T44 and the fourteenth transistor T45 are turned off, and the feedback signal output terminal Out(n) of this stage is high. Since the second clock signal CK2 is at a low level, the signal output terminal Cout(n) of the current stage and the scan signal output terminal G(n) are at a low level.
  • the first clock signal CK1 and the previous stage transmission signal output terminal Cout(n-1) fall to a low level, the first transistor T11 and the second transistor T12 are turned off, and the second clock signal CK2 rises to a high level. Due to the existence of the storage capacitor, the potential of the first node Q is coupled to a higher potential, which facilitates turning on the fourth transistor T21, the sixth transistor T22, and the fifth transistor T23. At this time, the feedback signal output terminal Out(n) of the current stage, the transmission signal output terminal Cout(n) of the current stage, and the scanning signal output terminal G(n) output high potential.
  • the potential of the feedback signal output terminal Out(n) of this stage is higher than that of the signal output terminal Cout(n) and scanning of this stage.
  • the first clock signal CK1 rises to a high potential
  • the first transistor T11 and the second transistor T12 are turned on
  • the next-stage transmission signal output terminal Cout(n+1) rises to a high potential
  • the seventh transistor T31, The eighth transistor T32 and the ninth transistor T33 are turned on, the first node Q and the scan signal output terminal G(n) fall to a low level
  • the fourth transistor T21, the sixth transistor T22, the fifth transistor T23 and the seventeenth transistor T53 are turned off .
  • the third node QB is also raised to a higher potential, and the tenth transistor T41, the eleventh transistor T42, and the twelfth transistor T43 , The thirteenth transistor T44 and the fourteenth transistor T45 are turned on. Due to the higher potential of the third node QB, the potential of the scan signal output terminal G(n) decreases rapidly, thereby reducing the fall time of the scan signal.
  • the first node Q maintains a low potential, and the seventeenth transistor T53 is turned off.
  • the next-stage feedback signal output terminal Out(n+1) drops to a low level, and the sixteenth transistor T52 is turned off.
  • the potential of the third node QB is controlled by the first DC high voltage VGH1, so the potential of the third node QB drops. Due to the drop in the potential of the third node QB, the 10th transistor T41, the eleventh transistor T42, the twelfth transistor T43, the thirteenth transistor T44, and the fourteenth transistor T45 receive a lower DC stress, and the threshold value of the transistor Voltage (threshold voltage) will not easily drift.
  • the gate drive circuit uses the next-stage feedback signal output terminal Out(n+1) and the first DC high voltage VGH1 to control the potential of the third node QB, so as to reduce the transistor's exposure
  • the direct current pressure can avoid the threshold voltage drift of the transistor.
  • the invention reduces the direct current pressure on the transistor and can avoid the threshold voltage drift of the transistor.

Abstract

Provided is a gate driving circuit comprising: a plurality of gate driving units 1, comprising: a pull-up control unit 200, which is connected to a first and a second nodes Q and N, a first clock signal CK1, a scan signal output terminal G(n), a current stage transmission signal output terminal Cout(n) and a previous stage transmission signal output terminal Cout(n-1); a pull-down maintenance unit 500, which is connected to the first and second nodes Q and N, a current stage feedback signal output terminal Out(n), a next stage feedback signal output terminal Out(n+1), the scan signal output terminal G(n), the current stage transmission signal output terminal Cout(n), a first DC high voltage VGH1, a first and second DC low voltages VGL1 and VGL2; a pull-up unit 100, which is connected to the first node Q, the second clock signal and the scan signal output terminal; a downstream unit 400, which is connected to the first node Q, the second clock signal CK2, a second DC high voltage VGH2, the current stage feedback signal output terminal Out(n), and the current stage transmission signal output terminal Cout(n); a pull-down unit 300, which is connected to the first and second nodes Q and N, the scan signal output terminal G(n), the next stage transmission signal output terminal Out(n+1), and the first and second DC low voltages VGL1 and VGL2; a bootstrap capacitor Cbt, one end of the bootstrap capacitor Cbt is connected to the first node Q, and the other end is connected to the scan signal output terminal G(n).

Description

栅极驱动电路Gate drive circuit 技术领域Technical field
本发明涉及显示技术领域，尤其涉及一种用于显示面板的栅极驱动电路。The present invention relates to the field of display technology, and in particular to a gate driving circuit for a display panel.
背景技术Background technique
阵列基板上栅极驱动(gate driver on array，GOA)技术即阵列基板行驱动技术，系将栅极扫描驱动电路制作在薄膜晶体管阵列基板上，以实现逐行扫描的驱动方式。The gate driver on array (GOA) technology on the array substrate is the row drive technology of the array substrate. The gate scan drive circuit is fabricated on the thin film transistor array substrate to realize the progressive scan driving mode.
在传统的栅极驱动电路中，节点QB乃使输出信号维持低电平的晶体管的栅极点。在一帧画面显示期间，节点QB几乎保持高电位，如此使得节点QB控制的晶体管一直处于开态。当晶体管在长时间工作后，尤其对于氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)晶体管，其阈值电压(threshold voltage)容易发生漂移，导致栅极驱动电路失效。In a conventional gate driving circuit, the node QB is the gate point of the transistor that maintains the output signal at a low level. During the display of one frame, the node QB almost maintains a high potential, so that the transistor controlled by the node QB is always in the on state. When the transistor is working for a long time, especially for indium gallium zinc oxide (Indium Gallium Zinc Oxide (IGZO) transistors are prone to drift in their threshold voltages, leading to failure of the gate drive circuit.
因此，有必要提供一种栅极驱动电路，以解决上述问题。Therefore, it is necessary to provide a gate driving circuit to solve the above-mentioned problems.
技术问题technical problem
当晶体管在长时间工作后，尤其对于氧化铟镓锌晶体管，其阈值电压容易发生漂移，导致栅极驱动电路失效。When the transistor is operated for a long time, especially for the indium gallium zinc oxide transistor, its threshold voltage is prone to drift, causing the gate drive circuit to fail.
技术解决方案Technical solutions
本发明的目的在于提供一种栅极驱动电路，可以避免晶体管的阈值电压漂移,确保栅极驱动电路正常运作。The object of the present invention is to provide a gate drive circuit, which can avoid the threshold voltage drift of the transistor and ensure the normal operation of the gate drive circuit.
为实现上述目的，本发明提供一种栅极驱动电路，包括多个级联的栅极驱动单元，其中所述栅极驱动单元包括:上拉控制单元，所述上拉控制单元连接第一节点、第二节点、第一时钟信号、扫描信号输出端、本级级传信号输出端及前级级传信号输出端；下拉维持单元，所述下拉维持单元连接所述第一节点、所述第二节点、本级反馈信号输出端、下一级反馈信号输出端、所述扫描信号输出端、所述本级级传信号输出端、第一直流高电压、第一直流低电压及第二直流低电压；上拉单元，所述上拉单元连接所述第一节点、第二时钟信号及所述扫描信号输出端；下传单元，所述下传单元连接所述第一节点、所述第二时钟信号、第二直流高电压、所述本级反馈信号输出端及所述本级级传信号输出端；下拉单元，所述下拉单元连接所述第一节点、所述第二节点、所述扫描信号输出端、下一级级传信号输出端、所述第一直流低电压及所述第二直流低电压；以及自举电容，其一端连接所述第一节点，且其另一端连接所述扫描信号输出端。In order to achieve the above object, the present invention provides a gate driving circuit including a plurality of cascaded gate driving units, wherein the gate driving unit includes: a pull-up control unit, the pull-up control unit is connected to a first node , The second node, the first clock signal, the scan signal output terminal, the transmission signal output terminal of the current stage and the previous stage transmission signal output terminal; a pull-down maintaining unit, the pull-down maintaining unit is connected to the first node and the first node Two nodes, the feedback signal output terminal of the current stage, the feedback signal output terminal of the next stage, the scan signal output terminal, the signal output terminal of the current stage, the first DC high voltage, the first DC low voltage and the second Two DC low voltage; a pull-up unit, the pull-up unit is connected to the first node, the second clock signal and the scan signal output terminal; a downstream unit, the downstream unit is connected to the first node, the The second clock signal, the second DC high voltage, the feedback signal output terminal of the current stage, and the transmission signal output terminal of the current stage; a pull-down unit, the pull-down unit is connected to the first node and the second node , The scanning signal output terminal, the next stage transmission signal output terminal, the first direct current low voltage and the second direct current low voltage; and a bootstrap capacitor, one end of which is connected to the first node, and The other end is connected to the scanning signal output end.
在一些实施例中，所述第一时钟信号和所述第二时钟信号为具有相反波形的交流信号。In some embodiments, the first clock signal and the second clock signal are AC signals with opposite waveforms.
在一些实施例中，所述上拉控制单元包括：第一晶体管，其栅极连接所述第一时钟信号，其源极连接所述前级级传信号输出端，其漏极连接所述第二节点；第二晶体管，其栅极连接所述第一时钟信号，其源极连接所述第二节点，其漏极连接所述第一节点；以及第三晶体管，其栅极连接所述本级级传信号输出端，其源极连接所述扫描信号输出端，其漏极连接所述第二节点。In some embodiments, the pull-up control unit includes: a first transistor, the gate of which is connected to the first clock signal, the source of which is connected to the output terminal of the previous stage transmission signal, and the drain of which is connected to the first Two nodes; a second transistor whose gate is connected to the first clock signal, its source is connected to the second node, and its drain is connected to the first node; and a third transistor whose gate is connected to the present The step-by-step transmission signal output terminal has its source connected to the scan signal output terminal and its drain connected to the second node.
在一些实施例中，对于第一级的栅极驱动单元，所述第一晶体管的源极通过所述前级级传信号输出端接收触发信号。In some embodiments, for the gate driving unit of the first stage, the source of the first transistor receives the trigger signal through the signal output terminal of the previous stage.
在一些实施例中，所述上拉单元包括第四晶体管，其栅极连接所述第一节点，其源极连接所述第二时钟信号，其漏极连接所述扫描信号输出端。In some embodiments, the pull-up unit includes a fourth transistor whose gate is connected to the first node, its source is connected to the second clock signal, and its drain is connected to the scan signal output terminal.
在一些实施例中，所述下传单元包括：第五晶体管，其栅极连接所述第一节点，其源极连接所述第二直流高电压，其漏极连接所述本级反馈信号输出端；以及第六晶体管，其栅极连接所述第一节点，其源极连接所述第二时钟信号，其漏极连接所述本级级传信号输出端。In some embodiments, the downstream unit includes: a fifth transistor whose gate is connected to the first node, its source is connected to the second DC high voltage, and its drain is connected to the feedback signal output of the current stage And a sixth transistor, the gate of which is connected to the first node, the source of which is connected to the second clock signal, and the drain of which is connected to the signal output terminal of the current stage.
在一些实施例中，所述下拉单元包括：第七晶体管，其栅极连接所述下一级级传信号输出端，其源极连接所述扫描信号输出端，其漏极连接所述第二直流低电压；第八晶体管，其栅极连接所述下一级级传信号输出端，其源极连接所述第一节点，其漏极连接所述第二节点；以及第九晶体管，其栅极连接所述下一级级传信号输出端，其源极连接所述第二节点，其漏极连接所述第一直流低电压。In some embodiments, the pull-down unit includes: a seventh transistor, the gate of which is connected to the next-stage signal output terminal, the source of which is connected to the scan signal output terminal, and the drain of which is connected to the second The eighth transistor, the gate of which is connected to the output terminal of the next-stage signal transmission, the source of which is connected to the first node, and the drain of which is connected to the second node; and the ninth transistor, the gate of which The pole is connected to the output terminal of the next-stage transmission signal, the source is connected to the second node, and the drain is connected to the first DC low voltage.
在一些实施例中，所述下拉维持单元包括：第十晶体管，其栅极连接第三节点，其源极连接所述扫描信号输出端，其漏极连接所述第二直流低电压；第十一晶体管，其栅极连接所述第三节点，其源极连接所述本级级传信号输出端，其漏极连接所述第一直流低电压；第十二晶体管，其栅极连接所述第三节点，其源极连接所述本级反馈信号输出端，其漏极连接所述第一直流低电压；第十三晶体管，其栅极连接所述第三节点，其源极连接所述第一节点，其漏极连接所述第二节点；第十四晶体管，其栅极连接所述第三节点，其源极连接所述第二节点，其漏极连接所述第一直流低电压；第十五晶体管，其栅极和源极连接所述第一直流高电压，其漏极连接所述第三节点；第十六晶体管，其栅极和源极连接所述下一级反馈信号输出端，其漏极连接所述第三节点；以及第十七晶体管，其栅极连接所述第一节点，其源极连接所述第三节点，其漏极连接所述第一直流低电压。In some embodiments, the pull-down sustain unit includes: a tenth transistor, the gate of which is connected to the third node, the source of which is connected to the scan signal output terminal, and the drain of which is connected to the second DC low voltage; A transistor whose gate is connected to the third node, its source is connected to the signal output terminal of the current stage, and its drain is connected to the first DC low voltage; a twelfth transistor, whose gate is connected to all The third node has its source connected to the feedback signal output terminal of the current stage, and its drain connected to the first DC low voltage; a thirteenth transistor has its gate connected to the third node and its source connected to The first node has its drain connected to the second node; the fourteenth transistor has its gate connected to the third node, its source connected to the second node, and its drain connected to the first node. Flow low voltage; a fifteenth transistor, its gate and source are connected to the first DC high voltage, and its drain is connected to the third node; a sixteenth transistor, its gate and source are connected to the lower The first-level feedback signal output terminal, the drain of which is connected to the third node; and the seventeenth transistor, the gate of which is connected to the first node, the source of which is connected to the third node, and the drain of which is connected to the third node. A DC low voltage.
在一些实施例中，所述第二直流低电压大于所述第一直流低电压。In some embodiments, the second DC low voltage is greater than the first DC low voltage.
在一些实施例中，所述第二直流高电压大于所述第一直流高电压且大于所述第二时钟信号的高电位。In some embodiments, the second DC high voltage is greater than the first DC high voltage and greater than the high potential of the second clock signal.
为实现上述目的，本发明还提供一种栅极驱动电路，包括多个级联的栅极驱动单元，其中所述栅极驱动单元包括:In order to achieve the above objective, the present invention also provides a gate driving circuit including a plurality of cascaded gate driving units, wherein the gate driving unit includes:
上拉控制单元，所述上拉控制单元连接第一节点、第二节点、第一时钟信号、扫描信号输出端、本级级传信号输出端及前级级传信号输出端；A pull-up control unit, the pull-up control unit is connected to the first node, the second node, the first clock signal, the scan signal output terminal, the current stage transmission signal output terminal and the previous stage transmission signal output terminal;
下拉维持单元，所述下拉维持单元连接所述第一节点、所述第二节点、本级反馈信号输出端、下一级反馈信号输出端、所述扫描信号输出端、所述本级级传信号输出端、第一直流高电压、第一直流低电压及第二直流低电压；A pull-down maintaining unit, which is connected to the first node, the second node, the feedback signal output terminal of the current stage, the feedback signal output terminal of the next stage, the scan signal output terminal, and the current stage transmission Signal output terminal, first direct current high voltage, first direct current low voltage and second direct current low voltage;
上拉单元，所述上拉单元连接所述第一节点、第二时钟信号及所述扫描信号输出端；A pull-up unit, the pull-up unit is connected to the first node, the second clock signal, and the scan signal output terminal;
下传单元，所述下传单元连接所述第一节点、所述第二时钟信号、第二直流高电压、所述本级反馈信号输出端及所述本级级传信号输出端；A downstream unit, which is connected to the first node, the second clock signal, the second DC high voltage, the feedback signal output terminal of the current stage, and the transmission signal output terminal of the current stage;
下拉单元，所述下拉单元连接所述第一节点、所述第二节点、所述扫描信号输出端、下一级级传信号输出端、所述第一直流低电压及所述第二直流低电压；以及The pull-down unit is connected to the first node, the second node, the scan signal output terminal, the next-stage transmission signal output terminal, the first direct current low voltage, and the second direct current Low voltage; and
自举电容，其一端连接所述第一节点，且其另一端连接所述扫描信号输出端；A bootstrap capacitor, one end of which is connected to the first node, and the other end of which is connected to the scan signal output terminal;
其中，所述第一时钟信号和所述第二时钟信号为具有相反波形的交流信号；所述第二直流低电压大于所述第一直流低电压；所述第二直流高电压大于所述第一直流高电压且大于所述第二时钟信号的高电位。Wherein, the first clock signal and the second clock signal are AC signals with opposite waveforms; the second DC low voltage is greater than the first DC low voltage; the second DC high voltage is greater than the The first DC high voltage is greater than the high potential of the second clock signal.
有益效果Beneficial effect
本发明可以避免晶体管的阈值电压漂移,确保栅极驱动电路正常运作。The invention can avoid the threshold voltage drift of the transistor and ensure the normal operation of the gate drive circuit.
附图说明Description of the drawings
为让本发明的特征以及技术内容能更明显易懂，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考用，并非用来对本发明加以限制。In order to make the features and technical content of the present invention more comprehensible, please refer to the following detailed description of the present invention and the accompanying drawings. However, the accompanying drawings are only for reference and are not used to limit the present invention.
图1为根据本发明实施例的栅极驱动电路的电路结构示意图；FIG. 1 is a schematic diagram of the circuit structure of a gate driving circuit according to an embodiment of the present invention;
图2为图1所示的栅极驱动电路的工作时序图。FIG. 2 is a working timing diagram of the gate driving circuit shown in FIG. 1.
本发明的实施方式Embodiments of the invention
为了使本发明的目的、技术手段及其效果更加清楚明确，以下将结合附图对本发明作进一步地阐述。应当理解，此处所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例，并不用于限定本发明。In order to make the purpose, technical means and effects of the present invention clearer and clearer, the present invention will be further described below in conjunction with the accompanying drawings. It should be understood that the embodiments described here are only a part of the embodiments of the present invention, rather than all the embodiments, and are not intended to limit the present invention.
请参考图1，其示出根据本发明实施例的栅极驱动电路的电路结构示意图。栅极驱动电路包括多个级联的栅极驱动单元1，栅极驱动单元1包括上拉单元100、上拉控制单元200、下传单元300、下拉单元400、下拉维持单元500及自举电容Cbt。在本实施例中，第一时钟信号CK1和第二时钟信号CK2为具有相反波形的交流信号。具体地，第二直流低电压VGL2大于第一直流低电压VGL1；第二直流高电压VGH2大于第一直流高电压VGH1且大于第二时钟信号CK2的高电位。Please refer to FIG. 1, which shows a schematic diagram of a circuit structure of a gate driving circuit according to an embodiment of the present invention. The gate driving circuit includes a plurality of cascaded gate driving units 1. The gate driving unit 1 includes a pull-up unit 100, a pull-up control unit 200, a downstream unit 300, a pull-down unit 400, a pull-down sustain unit 500, and a bootstrap capacitor Cbt. In this embodiment, the first clock signal CK1 and the second clock signal CK2 are AC signals with opposite waveforms. Specifically, the second DC low voltage VGL2 is greater than the first DC low voltage VGL1; the second DC high voltage VGH2 is greater than the first DC high voltage VGH1 and is greater than the high potential of the second clock signal CK2.
如图1所示，上拉单元100连接第一节点Q、第二时钟信号CK2及扫描信号输出端G(n)。上拉单元100包括第四晶体管T21，第四晶体管T21的栅极连接第一节点Q，第四晶体管T21的源极连接第二时钟信号CK2，第四晶体管T21的漏极连接扫描信号输出端G(n)。As shown in FIG. 1, the pull-up unit 100 is connected to the first node Q, the second clock signal CK2, and the scan signal output terminal G(n). The pull-up unit 100 includes a fourth transistor T21, the gate of the fourth transistor T21 is connected to the first node Q, the source of the fourth transistor T21 is connected to the second clock signal CK2, and the drain of the fourth transistor T21 is connected to the scan signal output terminal G (n).
如图1所示，上拉控制单元200连接第一节点Q、第二节点N、第一时钟信号CK1、扫描信号输出端G(n)、本级级传信号输出端Cout(n)及前级级传信号输出端Cout(n－1)。上拉控制单元200包括第一晶体管T11、第二晶体管T12及第三晶体管T6。第一晶体管T11的栅极连接第一时钟信号CK1，第一晶体管T11的源极连接前级级传信号输出端Cout(n－1)，第一晶体管T11的漏极连接第二节点N。第二晶体管T12的栅极连接第一时钟信号CK1，第二晶体管T12的源极连接第二节点N，第二晶体管T12的漏极连接第一节点Q。第三晶体管T6的栅极连接本级级传信号输出端Cout(n)，第三晶体管T6的源极连接扫描信号输出端G(n)，第三晶体管T6的漏极连接第二节点N。As shown in FIG. 1, the pull-up control unit 200 is connected to the first node Q, the second node N, the first clock signal CK1, the scan signal output terminal G(n), the transmission signal output terminal Cout(n) of the current stage and the front The signal output terminal Cout(n-1) is transmitted in stages. The pull-up control unit 200 includes a first transistor T11, a second transistor T12, and a third transistor T6. The gate of the first transistor T11 is connected to the first clock signal CK1, the source of the first transistor T11 is connected to the previous stage transmission signal output terminal Cout(n-1), and the drain of the first transistor T11 is connected to the second node N. The gate of the second transistor T12 is connected to the first clock signal CK1, the source of the second transistor T12 is connected to the second node N, and the drain of the second transistor T12 is connected to the first node Q. The gate of the third transistor T6 is connected to the signal output terminal Cout(n) of the current stage, the source of the third transistor T6 is connected to the scan signal output terminal G(n), and the drain of the third transistor T6 is connected to the second node N.
如图1所示，下传单元300连接第一节点Q、第二时钟信号CK2、第二直流高电压VGH2、本级反馈信号输出端Out(n)及本级级传信号输出端Cout(n)。下传单元300包括第五晶体管T23和第六晶体管T22。第五晶体管T23的栅极连接第一节点Q，第五晶体管T23的源极连接第二直流高电压VGH2，第五晶体管T23的漏极连接本级反馈信号输出端Out(n)。第六晶体管T22的栅极连接第一节点Q，第六晶体管T22的源极连接第二时钟信号CK2，第六晶体管T22的漏极连接本级级传信号输出端Cout(n)。As shown in Figure 1, the download unit 300 is connected to the first node Q, the second clock signal CK2, the second DC high voltage VGH2, the feedback signal output terminal Out(n) of the current stage, and the transmission signal output terminal Cout(n ). The downstream unit 300 includes a fifth transistor T23 and a sixth transistor T22. The gate of the fifth transistor T23 is connected to the first node Q, the source of the fifth transistor T23 is connected to the second DC high voltage VGH2, and the drain of the fifth transistor T23 is connected to the feedback signal output terminal Out(n) of this stage. The gate of the sixth transistor T22 is connected to the first node Q, the source of the sixth transistor T22 is connected to the second clock signal CK2, and the drain of the sixth transistor T22 is connected to the signal output terminal Cout(n) of the current stage.
如图1所示，下拉单元400连接第一节点Q、第二节点N、扫描信号输出端G(n)、下一级级传信号输出端Cout(n+1)、第一直流低电压VGL1及第二直流低电压VGL2。下拉单元400包括第七晶体管T31、第八晶体管T32及第九晶体管T33。第七晶体管T31的栅极连接下一级级传信号输出端Cout(n+1)，第七晶体管T31的源极连接扫描信号输出端G(n)，第七晶体管T31的漏极连接第二直流低电压VGL2。第八晶体管T32的栅极连接下一级级传信号输出端Cout(n+1)，第八晶体管T32的源极连接第一节点Q，第八晶体管T32的漏极连接第二节点N。第九晶体管T33的栅极连接下一级级传信号输出端Cout(n+1)，第九晶体管T33的源极连接第二节点N，第九晶体管T33的漏极连接第一直流低电压VGL1。As shown in FIG. 1, the pull-down unit 400 is connected to the first node Q, the second node N, the scan signal output terminal G(n), the next stage transmission signal output terminal Cout(n+1), and the first DC low voltage VGL1 and the second DC low voltage VGL2. The pull-down unit 400 includes a seventh transistor T31, an eighth transistor T32, and a ninth transistor T33. The gate of the seventh transistor T31 is connected to the next stage signal output terminal Cout(n+1), the source of the seventh transistor T31 is connected to the scanning signal output terminal G(n), and the drain of the seventh transistor T31 is connected to the second DC low voltage VGL2. The gate of the eighth transistor T32 is connected to the next stage signal output terminal Cout(n+1), the source of the eighth transistor T32 is connected to the first node Q, and the drain of the eighth transistor T32 is connected to the second node N. The gate of the ninth transistor T33 is connected to the next-stage signal output terminal Cout(n+1), the source of the ninth transistor T33 is connected to the second node N, and the drain of the ninth transistor T33 is connected to the first DC low voltage VGL1.
如图1所示，下拉维持单元500连接第一节点Q、第二节点N、本级反馈信号输出端Out(n)、下一级反馈信号输出端Out(n+1)、扫描信号输出端G(n)、本级级传信号输出端Cout(n)、第一直流高电压VGH1、第一直流低电压VGL1及第二直流低电压VGL2。下拉维持单元500包括第十晶体管T41、第十一晶体管T42、第十二晶体管T43、第十三晶体管T44、第十四晶体管T45、第十五晶体管T51、第十六晶体管T52和第十七晶体管T53。第十晶体管T41的栅极连接第三节点QB，第十晶体管T41的源极连接扫描信号输出端G(n)，第十晶体管T41的漏极连接第二直流低电压VGL2。第十一晶体管T42的栅极连接第三节点QB，第十一晶体管T42的源极连接本级级传信号输出端Cout(n)，第十一晶体管T42的漏极连接第一直流低电压VGL1。第十二晶体管T43的栅极连接第三节点QB ，第十二晶体管T43的源极连接本级反馈信号输出端Out(n)，第十二晶体管T43的漏极连接第一直流低电压VGL1。第十三晶体管T44的栅极连接所述第三节点QB ，第十三晶体管T44的源极连接第一节点Q，第十三晶体管T44的漏极连接第二节点N。第十四晶体管T45的栅极连接第三节点QB，第十四晶体管T45的源极连接第二节点N，第十四晶体管T45的漏极连接第一直流低电压VGL1。第十五晶体管T51的栅极和源极连接第一直流高电压VGH1，第十五晶体管T51的漏极连接第三节点QB。第十六晶体管T52的栅极和源极连接下一级反馈信号输出端Out(n+1)，第十六晶体管T52的漏极连接第三节点QB。第十七晶体管T53的栅极连接第一节点Q，第十七晶体管T53的源极连接第三节点QB，第十七晶体管T53的漏极连接第一直流低电压VGL1。As shown in FIG. 1, the pull-down maintenance unit 500 is connected to the first node Q, the second node N, the feedback signal output terminal Out(n) of the current stage, the feedback signal output terminal Out(n+1) of the next stage, and the scan signal output terminal. G(n), the signal output terminal Cout(n) of the current stage, the first DC high voltage VGH1, the first DC low voltage VGL1, and the second DC low voltage VGL2. The pull-down sustain unit 500 includes a tenth transistor T41, an eleventh transistor T42, a twelfth transistor T43, a thirteenth transistor T44, a fourteenth transistor T45, a fifteenth transistor T51, a sixteenth transistor T52, and a seventeenth transistor T53. The gate of the tenth transistor T41 is connected to the third node QB, the source of the tenth transistor T41 is connected to the scan signal output terminal G(n), and the drain of the tenth transistor T41 is connected to the second DC low voltage VGL2. The gate of the eleventh transistor T42 is connected to the third node QB, the source of the eleventh transistor T42 is connected to the signal output terminal Cout(n) of the current stage, and the drain of the eleventh transistor T42 is connected to the first DC low voltage VGL1. The gate of the twelfth transistor T43 is connected to the third node QB, the source of the twelfth transistor T43 is connected to the feedback signal output terminal Out(n) of the current stage, and the drain of the twelfth transistor T43 is connected to the first DC low voltage VGL1 . The gate of the thirteenth transistor T44 is connected to the third node QB, the source of the thirteenth transistor T44 is connected to the first node Q, and the drain of the thirteenth transistor T44 is connected to the second node N. The gate of the fourteenth transistor T45 is connected to the third node QB, the source of the fourteenth transistor T45 is connected to the second node N, and the drain of the fourteenth transistor T45 is connected to the first DC low voltage VGL1. The gate and source of the fifteenth transistor T51 are connected to the first DC high voltage VGH1, and the drain of the fifteenth transistor T51 is connected to the third node QB. The gate and source of the sixteenth transistor T52 are connected to the next-stage feedback signal output terminal Out(n+1), and the drain of the sixteenth transistor T52 is connected to the third node QB. The gate of the seventeenth transistor T53 is connected to the first node Q, the source of the seventeenth transistor T53 is connected to the third node QB, and the drain of the seventeenth transistor T53 is connected to the first DC low voltage VGL1.
如图1所示，自举电容Cbt的一端连接第一节点Q，且自举电容Cbt的另一端连接扫描信号输出端G(n)。As shown in FIG. 1, one end of the bootstrap capacitor Cbt is connected to the first node Q, and the other end of the bootstrap capacitor Cbt is connected to the scan signal output terminal G(n).
图2为图1所示的栅极驱动电路的工作时序图。以第一级的栅极驱动单元为例，第一晶体管T11的源极通过前级级传信号输出端Cout(n－1)接收触发信号STV。在T1阶段中，前级级传信号输出端Cout(n-1)及第一时钟信号CK1为高电位，第一晶体管T11和第二晶体管T12打开，第一节点Q的电位被抬升至高电位，第四晶体管T21、第六晶体管T22、第五晶体管T23及第十七晶体管T53打开，第三节点QB被拉低至低电位，第十晶体管T41、第十一晶体管T42、第十二晶体管T43、第十三晶体管T44及第十四晶体管T45关闭，本级反馈信号输出端Out(n)为高电位。由于第二时钟信号CK2为低电位，本级级传信号输出端Cout(n)和扫描信号输出端G(n)为低电位。FIG. 2 is a working timing diagram of the gate driving circuit shown in FIG. 1. Taking the gate driving unit of the first stage as an example, the source of the first transistor T11 receives the trigger signal STV through the signal output terminal Cout(n-1) of the previous stage. In the T1 stage, the previous stage transmission signal output terminal Cout(n-1) and the first clock signal CK1 are at high potential, the first transistor T11 and the second transistor T12 are turned on, and the potential of the first node Q is raised to a high potential. The fourth transistor T21, the sixth transistor T22, the fifth transistor T23, and the seventeenth transistor T53 are turned on, the third node QB is pulled down to a low potential, the tenth transistor T41, the eleventh transistor T42, and the twelfth transistor T43, The thirteenth transistor T44 and the fourteenth transistor T45 are turned off, and the feedback signal output terminal Out(n) of this stage is high. Since the second clock signal CK2 is at a low level, the signal output terminal Cout(n) of the current stage and the scan signal output terminal G(n) are at a low level.
在T2阶段中，第一时钟信号CK1和前级级传信号输出端Cout(n-1)降为低电位，第一晶体管T11和第二晶体管T12关闭，第二时钟信号CK2升为高电位。由于存储电容的存在，第一节点Q的电位被耦合至更高的电位，使得有利于打开第四晶体管T21、第六晶体管T22及第五晶体管T23。此时，本级反馈信号输出端Out(n)、本级级传信号输出端Cout(n)及扫描信号输出端G(n)输出高电位。在本实施例中，由于第二直流高电压VGH2大于第二时钟信号CK2的高电位，本级反馈信号输出端Out(n)的电位高于本级级传信号输出端Cout(n)和扫描信号输出端G(n)的电位。In the T2 phase, the first clock signal CK1 and the previous stage transmission signal output terminal Cout(n-1) fall to a low level, the first transistor T11 and the second transistor T12 are turned off, and the second clock signal CK2 rises to a high level. Due to the existence of the storage capacitor, the potential of the first node Q is coupled to a higher potential, which facilitates turning on the fourth transistor T21, the sixth transistor T22, and the fifth transistor T23. At this time, the feedback signal output terminal Out(n) of the current stage, the transmission signal output terminal Cout(n) of the current stage, and the scanning signal output terminal G(n) output high potential. In this embodiment, since the second DC high voltage VGH2 is greater than the high potential of the second clock signal CK2, the potential of the feedback signal output terminal Out(n) of this stage is higher than that of the signal output terminal Cout(n) and scanning of this stage. The potential of the signal output terminal G(n).
在T3阶段中，第一时钟信号CK1升为高电位，第一晶体管T11和第二晶体管T12打开，下一级级传信号输出端Cout(n+1)升为高电位，第七晶体管T31、第八晶体管T32及第九晶体管T33打开，第一节点Q和扫描信号输出端G(n)降至低电位，第四晶体管T21、第六晶体管T22、第五晶体管T23及第十七晶体管T53关闭。由于下一级反馈信号输出端Out(n+1)输出更高的电位，第三节点QB也被抬升至更高的电位，且第十晶体管T41、第十一晶体管T42、第十二晶体管T43、第十三晶体管T44及第十四晶体管T45打开。由于第三节点QB的更高电位，使得扫描信号输出端G(n)的电位快速降低，因而减少扫描信号的下降时间。In the T3 phase, the first clock signal CK1 rises to a high potential, the first transistor T11 and the second transistor T12 are turned on, the next-stage transmission signal output terminal Cout(n+1) rises to a high potential, and the seventh transistor T31, The eighth transistor T32 and the ninth transistor T33 are turned on, the first node Q and the scan signal output terminal G(n) fall to a low level, and the fourth transistor T21, the sixth transistor T22, the fifth transistor T23 and the seventeenth transistor T53 are turned off . Since the next-stage feedback signal output terminal Out(n+1) outputs a higher potential, the third node QB is also raised to a higher potential, and the tenth transistor T41, the eleventh transistor T42, and the twelfth transistor T43 , The thirteenth transistor T44 and the fourteenth transistor T45 are turned on. Due to the higher potential of the third node QB, the potential of the scan signal output terminal G(n) decreases rapidly, thereby reducing the fall time of the scan signal.
在T4阶段中，第一节点Q维持低电位，第十七晶体管T53关闭。同时，下一级反馈信号输出端Out(n+1)降为低电位，第十六晶体管T52关闭。第三节点QB的电位由第一直流高电压VGH1控制，因此第三节点QB的电位下降。由于第三节点QB的电位下降，第十晶体管T41、第十一晶体管T42、第十二晶体管T43、第十三晶体管T44及第十四晶体管T45受到的直流压力(DC stress)降低，晶体管的阈值电压(threshold voltage)便不易发生漂移。In the T4 phase, the first node Q maintains a low potential, and the seventeenth transistor T53 is turned off. At the same time, the next-stage feedback signal output terminal Out(n+1) drops to a low level, and the sixteenth transistor T52 is turned off. The potential of the third node QB is controlled by the first DC high voltage VGH1, so the potential of the third node QB drops. Due to the drop in the potential of the third node QB, the 10th transistor T41, the eleventh transistor T42, the twelfth transistor T43, the thirteenth transistor T44, and the fourteenth transistor T45 receive a lower DC stress, and the threshold value of the transistor Voltage (threshold voltage) will not easily drift.
综上所述，本发明提供的栅极驱动电路，利用下一级反馈信号输出端Out(n+1)和第一直流高电压VGH1来控制第三节点QB的电位，以减少晶体管所受到的直流压力，如此可以避免晶体管的阈值电压漂移。In summary, the gate drive circuit provided by the present invention uses the next-stage feedback signal output terminal Out(n+1) and the first DC high voltage VGH1 to control the potential of the third node QB, so as to reduce the transistor's exposure The direct current pressure can avoid the threshold voltage drift of the transistor.
应当理解的是，本发明的应用不限于上述的举例，对本领域普通技术人员来说，可以根据上述说明加以改进或变换，所有这些改进和变换都应属于本发明所附权利要求的保护范围。It should be understood that the application of the present invention is not limited to the above examples. For those of ordinary skill in the art, improvements or changes can be made based on the above description, and all these improvements and changes should fall within the protection scope of the appended claims of the present invention.
工业实用性Industrial applicability
本发明减少晶体管所受到的直流压力，可以避免晶体管的阈值电压漂移。The invention reduces the direct current pressure on the transistor and can avoid the threshold voltage drift of the transistor.

Claims (11)

  1. 一种栅极驱动电路，包括多个级联的栅极驱动单元，其中所述栅极驱动单元包括：A gate driving circuit includes a plurality of cascaded gate driving units, wherein the gate driving unit includes:
    上拉控制单元，所述上拉控制单元连接第一节点、第二节点、第一时钟信号、扫描信号输出端、本级级传信号输出端及前级级传信号输出端；A pull-up control unit, the pull-up control unit is connected to the first node, the second node, the first clock signal, the scan signal output terminal, the current stage transmission signal output terminal and the previous stage transmission signal output terminal;
    下拉维持单元，所述下拉维持单元连接所述第一节点、所述第二节点、本级反馈信号输出端、下一级反馈信号输出端、所述扫描信号输出端、所述本级级传信号输出端、第一直流高电压、第一直流低电压及第二直流低电压；A pull-down maintaining unit, which is connected to the first node, the second node, the feedback signal output terminal of the current stage, the feedback signal output terminal of the next stage, the scan signal output terminal, and the current stage transmission Signal output terminal, first direct current high voltage, first direct current low voltage and second direct current low voltage;
    上拉单元，所述上拉单元连接所述第一节点、第二时钟信号及所述扫描信号输出端；A pull-up unit, the pull-up unit is connected to the first node, the second clock signal, and the scan signal output terminal;
    下传单元，所述下传单元连接所述第一节点、所述第二时钟信号、第二直流高电压、所述本级反馈信号输出端及所述本级级传信号输出端；A downstream unit, which is connected to the first node, the second clock signal, the second DC high voltage, the feedback signal output terminal of the current stage, and the transmission signal output terminal of the current stage;
    下拉单元，所述下拉单元连接所述第一节点、所述第二节点、所述扫描信号输出端、下一级级传信号输出端、所述第一直流低电压及所述第二直流低电压；以及The pull-down unit is connected to the first node, the second node, the scan signal output terminal, the next-stage transmission signal output terminal, the first direct current low voltage, and the second direct current Low voltage; and
    自举电容，其一端连接所述第一节点，且其另一端连接所述扫描信号输出端。One end of the bootstrap capacitor is connected to the first node, and the other end is connected to the scan signal output terminal.
  2. 如权利要求1所述的栅极驱动电路，其中，所述第一时钟信号和所述第二时钟信号为具有相反波形的交流信号。5. The gate driving circuit of claim 1, wherein the first clock signal and the second clock signal are AC signals having opposite waveforms.
  3. 如权利要求1所述的栅极驱动电路，其中，所述上拉控制单元包括：8. The gate driving circuit of claim 1, wherein the pull-up control unit comprises:
    第一晶体管，其栅极连接所述第一时钟信号，其源极连接所述前级级传信号输出端，其漏极连接所述第二节点；A first transistor, the gate of which is connected to the first clock signal, the source of which is connected to the output terminal of the previous stage transmission signal, and the drain of which is connected to the second node;
    第二晶体管，其栅极连接所述第一时钟信号，其源极连接所述第二节点，其漏极连接所述第一节点；以及A second transistor whose gate is connected to the first clock signal, its source is connected to the second node, and its drain is connected to the first node; and
    第三晶体管，其栅极连接所述本级级传信号输出端，其源极连接所述扫描信号输出端，其漏极连接所述第二节点。The third transistor has its gate connected to the signal output terminal of the current stage, its source connected to the scanning signal output terminal, and its drain connected to the second node.
  4. 如权利要求3所述的栅极驱动电路，其中，对于第一级的栅极驱动单元，所述第一晶体管的源极通过所述前级级传信号输出端接收触发信号。3. The gate driving circuit according to claim 3, wherein for the gate driving unit of the first stage, the source of the first transistor receives a trigger signal through the signal output terminal of the previous stage.
  5. 如权利要求1所述的栅极驱动电路，其中，所述上拉单元包括第四晶体管，其栅极连接所述第一节点，其源极连接所述第二时钟信号，其漏极连接所述扫描信号输出端。The gate drive circuit of claim 1, wherein the pull-up unit comprises a fourth transistor, the gate of which is connected to the first node, the source of which is connected to the second clock signal, and the drain of which is connected to the The scanning signal output terminal.
  6. 如权利要求1所述的栅极驱动电路，其中，所述下传单元包括：5. The gate driving circuit of claim 1, wherein the download unit comprises:
    第五晶体管，其栅极连接所述第一节点，其源极连接所述第二直流高电压，其漏极连接所述本级反馈信号输出端；以及A fifth transistor, the gate of which is connected to the first node, the source of which is connected to the second DC high voltage, and the drain of which is connected to the feedback signal output terminal of the current stage; and
    第六晶体管，其栅极连接所述第一节点，其源极连接所述第二时钟信号，其漏极连接所述本级级传信号输出端。The sixth transistor has a gate connected to the first node, a source connected to the second clock signal, and a drain connected to the signal output terminal of the current stage.
  7. 如权利要求1所述的栅极驱动电路，其中，所述下拉单元包括：8. The gate driving circuit of claim 1, wherein the pull-down unit comprises:
    第七晶体管，其栅极连接所述下一级级传信号输出端，其源极连接所述扫描信号输出端，其漏极连接所述第二直流低电压；A seventh transistor, the gate of which is connected to the next stage signal output terminal, the source of which is connected to the scanning signal output terminal, and the drain of which is connected to the second DC low voltage;
    第八晶体管，其栅极连接所述下一级级传信号输出端，其源极连接所述第一节点，其漏极连接所述第二节点；以及An eighth transistor, the gate of which is connected to the next-stage signal output terminal, the source of which is connected to the first node, and the drain of which is connected to the second node; and
    第九晶体管，其栅极连接所述下一级级传信号输出端，其源极连接所述第二节点，其漏极连接所述第一直流低电压。The ninth transistor has its gate connected to the next stage signal output terminal, its source connected to the second node, and its drain connected to the first direct current low voltage.
  8. 如权利要求1所述的栅极驱动电路，其中，所述下拉维持单元包括：5. The gate driving circuit of claim 1, wherein the pull-down sustain unit comprises:
    第十晶体管，其栅极连接第三节点，其源极连接所述扫描信号输出端，其漏极连接所述第二直流低电压；A tenth transistor, the gate of which is connected to the third node, the source of which is connected to the scan signal output terminal, and the drain of which is connected to the second DC low voltage;
    第十一晶体管，其栅极连接所述第三节点，其源极连接所述本级级传信号输出端，其漏极连接所述第一直流低电压；An eleventh transistor, the gate of which is connected to the third node, the source of which is connected to the signal output terminal of the current stage, and the drain of which is connected to the first DC low voltage;
    第十二晶体管，其栅极连接所述第三节点，其源极连接所述本级反馈信号输出端，其漏极连接所述第一直流低电压；A twelfth transistor, the gate of which is connected to the third node, the source of which is connected to the feedback signal output terminal of this stage, and the drain of which is connected to the first DC low voltage;
    第十三晶体管，其栅极连接所述第三节点，其源极连接所述第一节点，其漏极连接所述第二节点；A thirteenth transistor, with a gate connected to the third node, a source connected to the first node, and a drain connected to the second node;
    第十四晶体管，其栅极连接所述第三节点，其源极连接所述第二节点，其漏极连接所述第一直流低电压；A fourteenth transistor, with a gate connected to the third node, a source connected to the second node, and a drain connected to the first direct current low voltage;
    第十五晶体管，其栅极和源极连接所述第一直流高电压，其漏极连接所述第三节点；A fifteenth transistor, its gate and source are connected to the first DC high voltage, and its drain is connected to the third node;
    第十六晶体管，其栅极和源极连接所述下一级反馈信号输出端，其漏极连接所述第三节点；以及A sixteenth transistor, the gate and source of which are connected to the output terminal of the next stage feedback signal, and the drain of which is connected to the third node; and
    第十七晶体管，其栅极连接所述第一节点，其源极连接所述第三节点，其漏极连接所述第一直流低电压。The seventeenth transistor has its gate connected to the first node, its source connected to the third node, and its drain connected to the first direct current low voltage.
  9. 如权利要求1所述的栅极驱动电路，其中，所述第二直流低电压大于所述第一直流低电压。3. The gate driving circuit of claim 1, wherein the second DC low voltage is greater than the first DC low voltage.
  10. 如权利要求1所述的栅极驱动电路，其中，所述第二直流高电压大于所述第一直流高电压且大于所述第二时钟信号的高电位。3. The gate driving circuit of claim 1, wherein the second DC high voltage is greater than the first DC high voltage and greater than the high potential of the second clock signal.
  11. 一种栅极驱动电路，包括多个级联的栅极驱动单元，其中所述栅极驱动单元包括:A gate driving circuit includes a plurality of cascaded gate driving units, wherein the gate driving unit includes:
    上拉控制单元，所述上拉控制单元连接第一节点、第二节点、第一时钟信号、扫描信号输出端、本级级传信号输出端及前级级传信号输出端；A pull-up control unit, the pull-up control unit is connected to the first node, the second node, the first clock signal, the scan signal output terminal, the current stage transmission signal output terminal and the previous stage transmission signal output terminal;
    下拉维持单元，所述下拉维持单元连接所述第一节点、所述第二节点、本级反馈信号输出端、下一级反馈信号输出端、所述扫描信号输出端、所述本级级传信号输出端、第一直流高电压、第一直流低电压及第二直流低电压；A pull-down maintaining unit, which is connected to the first node, the second node, the feedback signal output terminal of the current stage, the feedback signal output terminal of the next stage, the scan signal output terminal, and the current stage transmission Signal output terminal, first direct current high voltage, first direct current low voltage and second direct current low voltage;
    上拉单元，所述上拉单元连接所述第一节点、第二时钟信号及所述扫描信号输出端；A pull-up unit, the pull-up unit is connected to the first node, the second clock signal, and the scan signal output terminal;
    下传单元，所述下传单元连接所述第一节点、所述第二时钟信号、第二直流高电压、所述本级反馈信号输出端及所述本级级传信号输出端；A downstream unit, which is connected to the first node, the second clock signal, the second DC high voltage, the feedback signal output terminal of the current stage, and the transmission signal output terminal of the current stage;
    下拉单元，所述下拉单元连接所述第一节点、所述第二节点、所述扫描信号输出端、下一级级传信号输出端、所述第一直流低电压及所述第二直流低电压；以及A pull-down unit connected to the first node, the second node, the scan signal output terminal, the next-stage transmission signal output terminal, the first direct current low voltage, and the second direct current Low voltage; and
    自举电容，其一端连接所述第一节点，且其另一端连接所述扫描信号输出端；A bootstrap capacitor, one end of which is connected to the first node, and the other end of which is connected to the scan signal output terminal;
    其中，所述第一时钟信号和所述第二时钟信号为具有相反波形的交流信号；所述第二直流低电压大于所述第一直流低电压；所述第二直流高电压大于所述第一直流高电压且大于所述第二时钟信号的高电位。Wherein, the first clock signal and the second clock signal are AC signals with opposite waveforms; the second DC low voltage is greater than the first DC low voltage; the second DC high voltage is greater than the The first DC high voltage is greater than the high potential of the second clock signal.
PCT/CN2019/099332 2019-07-22 2019-08-06 Gate driving circuit WO2021012313A1 (en)

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