CN106935168B - Shift register and display device - Google Patents

Shift register and display device Download PDF

Info

Publication number
CN106935168B
CN106935168B CN201511027073.0A CN201511027073A CN106935168B CN 106935168 B CN106935168 B CN 106935168B CN 201511027073 A CN201511027073 A CN 201511027073A CN 106935168 B CN106935168 B CN 106935168B
Authority
CN
China
Prior art keywords
signal
pull
unit
coupled
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201511027073.0A
Other languages
Chinese (zh)
Other versions
CN106935168A (en
Inventor
詹建廷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hannstar Display Corp
Original Assignee
Hannstar Display Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hannstar Display Corp filed Critical Hannstar Display Corp
Priority to CN201511027073.0A priority Critical patent/CN106935168B/en
Publication of CN106935168A publication Critical patent/CN106935168A/en
Application granted granted Critical
Publication of CN106935168B publication Critical patent/CN106935168B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Shift Register Type Memory (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention discloses a shift register and a display device. The shift register comprises a pre-charging unit, a pull-up unit, a first pull-down unit and a second pull-down unit. The pre-charging unit receives a first input signal and a second input signal, and outputs a pre-charging signal from a first node. The pull-up unit receives the precharge signal, the first clock signal and the second clock signal, and outputs a scan signal from the second node. The first pull-down unit receives the precharge signal, the first pull-down control signal and the second pull-down control signal, and controls whether to pull down the scan signal to the reference potential. The second pull-down unit receives the precharge signal, the first pull-down control signal and the second pull-down control signal, and controls whether to pull down the scan signal to the reference potential. Therefore, the shift register has high reliability and high stability, and the display device with the shift register can improve the display quality of the display device.

Description

Shift register and display device
Technical Field
The present invention relates to a shift register, and more particularly, to a shift register with improved reliability and a display device having the same.
Background
With the continuous progress of Thin Film Transistor (TFT) liquid crystal display technology, technology for integrating driving circuits on display panels, such as System On Glass (SOG), has been increasingly used in display device products nowadays. On the other hand, in the high-resolution display device, the driving time of each pixel is limited, and if the driving circuit cannot drive the corresponding pixel within the driving time, the driving circuit may cause image display error data or other problems due to poor driving stability. Therefore, how to design a driving circuit suitable for a high-resolution display device has been one of the goals addressed in the industry.
Disclosure of Invention
The present invention is directed to a shift register and a display device, which have stable performance and are not easily interfered by other noise, so as to improve the display quality of an image.
In accordance with the above object of the present invention, a shift register is provided. The shift register comprises a pre-charge unit, a pull-up unit, a first pull-down unit and a second pull-down unit. The precharge unit receives a first input signal and a second input signal, and outputs a precharge signal from the first node according to the first input signal and the second input signal. The precharge unit includes a first transistor and a second transistor. The gate and the first source/drain of the first transistor receive the first input signal, and the second source/drain of the first transistor is coupled to the first node and outputs the pre-charge signal. The gate and the first source/drain of the second transistor receive the second input signal, and the second source/drain of the second transistor is coupled to the second source/drain of the first transistor. The pull-up unit is coupled to the pre-charge unit and outputs the scan signal from the second node according to the pre-charge signal, the first clock signal and the second clock signal. The pull-up unit includes a third transistor, a capacitor and a fourth transistor. The gate of the third transistor receives the pre-charge signal, the first source/drain of the third transistor receives the first clock signal, and the second source/drain of the third transistor is coupled to the second node and outputs the scan signal. The first terminal of the capacitor is coupled to the gate of the third transistor, and the second terminal of the capacitor is coupled to the second source/drain of the third transistor. The gate of the fourth transistor receives the second clock signal, the first source/drain of the fourth transistor is coupled to the reference potential, and the second source/drain of the fourth transistor is coupled to the gate of the third transistor. The first pull-down unit is coupled to the pre-charge unit and the pull-up unit, receives the pre-charge signal, the first pull-down control signal and the second pull-down control signal, and controls whether to pull down the scan signal to the reference potential according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal. The second pull-down unit is coupled to the pre-charge unit and the pull-up unit, receives the pre-charge signal, the first pull-down control signal and the second pull-down control signal, and controls whether to pull down the scan signal to the reference potential according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal.
According to an embodiment of the present invention, the first input signal is a start signal, and the second input signal is a scan signal output by a next stage of the corresponding shift register.
According to another embodiment of the present invention, the first input signal is a scan signal outputted from a previous stage of the shift register corresponding to the shift register, and the second input signal is a scan signal outputted from a next stage of the shift register corresponding to the shift register.
According to another embodiment of the present invention, the first input signal is a scan signal outputted from a shift register of a previous stage of the corresponding shift register, and the second input signal is an end signal.
According to another embodiment of the present invention, the first clock signal is switched from the high level to the low level at a first time point, the second clock signal is switched from the low level to the high level at a second time point after the first time point, and the difference between the second time point and the first time point is two data writing times.
According to another embodiment of the present invention, the first pull-down unit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor. The gate and the first source/drain of the fifth transistor are inputted with the first pull-down control signal. The gate of the sixth transistor is inputted with the second pull-down control signal, the first source/drain of the sixth transistor is coupled to the reference potential, and the second source/drain of the sixth transistor is coupled to the second source/drain of the fifth transistor. The gate of the seventh transistor is coupled to the first node, the first source/drain of the seventh transistor is coupled to the reference potential, and the second source/drain of the seventh transistor is coupled to the second source/drain of the fifth transistor. The gate of the eighth transistor is coupled to the second source/drain of the seventh transistor, the first source/drain of the eighth transistor is coupled to the reference potential, and the second source/drain of the eighth transistor is coupled to the first node. The gate of the ninth transistor is coupled to the second source/drain of the seventh transistor, the first source/drain of the ninth transistor is coupled to the reference potential, and the second source/drain of the ninth transistor is coupled to the second node.
According to another embodiment of the present invention, the second pull-down unit includes a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor and a fourteenth transistor. The gate and the first source/drain of the tenth transistor are inputted with the second pull-down control signal. The gate of the eleventh transistor is inputted with the first pull-down control signal, the first source/drain of the eleventh transistor is coupled to the reference potential, and the second source/drain of the eleventh transistor is coupled to the second source/drain of the tenth transistor. The gate of the twelfth transistor is coupled to the first node, the first source/drain of the twelfth transistor is coupled to the reference potential, and the second source/drain of the twelfth transistor is coupled to the second source/drain of the tenth transistor. The gate of the thirteenth transistor is coupled to the second source/drain of the twelfth transistor, the first source/drain of the thirteenth transistor is coupled to the reference potential, and the second source/drain of the thirteenth transistor is coupled to the first node. The gate of the fourteenth transistor is coupled to the second source/drain of the twelfth transistor, the first source/drain of the fourteenth transistor is coupled to the reference potential, and the second source/drain of the fourteenth transistor is coupled to the second node.
According to the above object of the present invention, a display device is further provided. The display device comprises a display panel, a plurality of clock signal lines and a shift register device. The clock signal lines are used for providing a plurality of clock signals. The shift register device is used for driving the display panel and comprises a plurality of shift registers. Each shift register is coupled with the shift register of the previous stage or the shift register of the next stage, and each shift register comprises a pre-charge unit, a pull-up unit, a first pull-down unit and a second pull-down unit. The precharge unit receives a first input signal and a second input signal, and outputs a precharge signal from the first node according to the first input signal and the second input signal. The precharge unit includes a first transistor and a second transistor. The gate and the first source/drain of the first transistor receive the first input signal, and the second source/drain of the first transistor is coupled to the first node and outputs the pre-charge signal. The gate and the first source/drain of the second transistor receive the second input signal, and the second source/drain of the second transistor is coupled to the second source/drain of the first transistor. The pull-up unit is coupled to the pre-charge unit and outputs the scan signal from the second node according to the pre-charge signal, the first clock signal and the second clock signal. The pull-up unit includes a third transistor, a capacitor and a fourth transistor. The gate of the third transistor receives the pre-charge signal, the first source drain of the third transistor is coupled to the first clock signal line for providing the first clock signal, and the second source drain of the third transistor is coupled to the second node and outputs the scan signal. The first terminal of the capacitor is coupled to the gate of the third transistor, and the second terminal of the capacitor is coupled to the second source/drain of the third transistor. The gate of the fourth transistor is coupled to the second clock signal line for providing the second clock signal, the first source/drain of the fourth transistor is coupled to the reference potential, and the second source/drain of the fourth transistor is coupled to the gate of the third transistor. The first pull-down unit is coupled to the pre-charge unit and the pull-up unit, receives the pre-charge signal, the first pull-down control signal and the second pull-down control signal, and controls whether to pull down the scan signal to the reference potential according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal. The second pull-down unit is coupled to the pre-charge unit and the pull-up unit, receives the pre-charge signal, the first pull-down control signal and the second pull-down control signal, and controls whether to pull down the scan signal to the reference potential according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal.
According to an embodiment of the present invention, the shift registers are N-stage shift registers, wherein the first input signal and the second input signal in the 1 st stage shift register are respectively a start signal and a scan signal output by the 2 nd stage shift register, the first input signal and the second input signal in the N-th stage shift register are respectively a scan signal and an end signal output by the (N-1) th stage shift register, and the first input signal and the second input signal in the i-th stage shift register are respectively a scan signal output by the (i-1) th stage shift register and a scan signal output by the (i +1) th stage shift register, wherein i is a positive integer greater than 1 and less than N.
According to another embodiment of the present invention, the first clock signal is switched from the high level to the low level at a first time point, the second clock signal is switched from the low level to the high level at a second time point after the first time point, and the difference between the second time point and the first time point is two data writing times.
According to the above object of the present invention, a shift register is provided. The shift register comprises a pre-charge unit, a pull-up unit, a first pull-down unit and a second pull-down unit. The precharge unit receives a first input signal and a second input signal, and outputs a precharge signal from the first node according to the first input signal and the second input signal. The pull-up unit is coupled to the pre-charge unit and outputs the scan signal from the second node according to the pre-charge signal, the first clock signal and the second clock signal. The second pull-down unit is coupled to the pre-charge unit and the pull-up unit, receives the pre-charge signal, the first pull-down control signal and the second pull-down control signal, and controls whether to pull down the scan signal to the reference potential according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal. The first input signal is a start signal, and the second input signal is a scan signal output by a next stage of the shift register corresponding to the shift register.
According to the above object of the present invention, a shift register is provided. The shift register comprises a pre-charge unit, a pull-up unit, a first pull-down unit and a second pull-down unit. The precharge unit receives a first input signal and a second input signal, and outputs a precharge signal from the first node according to the first input signal and the second input signal. The pull-up unit is coupled to the pre-charge unit and outputs the scan signal from the second node according to the pre-charge signal, the first clock signal and the second clock signal. The second pull-down unit is coupled to the pre-charge unit and the pull-up unit, receives the pre-charge signal, the first pull-down control signal and the second pull-down control signal, and controls whether to pull down the scan signal to the reference potential according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal. The first input signal is a scanning signal outputted from a previous stage of the corresponding shift register, and the second input signal is a scanning signal outputted from a next stage of the corresponding shift register.
According to the above object of the present invention, a shift register is provided. The shift register comprises a pre-charge unit, a pull-up unit, a first pull-down unit and a second pull-down unit. The precharge unit receives a first input signal and a second input signal, and outputs a precharge signal from the first node according to the first input signal and the second input signal. The pull-up unit is coupled to the pre-charge unit and outputs the scan signal from the second node according to the pre-charge signal, the first clock signal and the second clock signal. The second pull-down unit is coupled to the pre-charge unit and the pull-up unit, receives the pre-charge signal, the first pull-down control signal and the second pull-down control signal, and controls whether to pull down the scan signal to the reference potential according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal. The first input signal is a scanning signal output by a previous stage of the corresponding shift register, and the second input signal is an end signal.
The invention has the advantages that the shift register has stable driving efficiency and is not easy to be interfered by other noises, and the display device using the shift register can improve the display quality, avoid the problems of water ripples or transverse ripples and the like in the displayed image and ensure high reliability and high stability.
Drawings
For a more complete understanding of the embodiments and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a schematic diagram of a display device according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a gate driving circuit according to an embodiment of the invention;
FIG. 3 is a schematic diagram of an equivalent circuit of a shift register according to an embodiment of the invention; and
FIG. 4 is a timing diagram of the gate driving circuit of FIG. 2.
Detailed Description
Embodiments of the invention are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The embodiments discussed and disclosed are merely illustrative and are not intended to limit the scope of the invention.
Referring to fig. 1, a schematic diagram of a display device 100 according to an embodiment of the invention is shown, the display device 100 includes a display panel 110, a source driver 120, and gate drivers 130A, 130B. the display panel 110 has a plurality of pixels arranged in an array, which are commonly used to display an image, the display panel 110 may be a liquid crystal display panel of various types, such as a Twisted Nematic (TN) type, an in-plane switching (IPS) type, an edge-field switching (FFS) type, or a Vertical Alignment (VA) type, or an organic light-emitting diode (organic light-emitting diode) display panel, but not limited thereto, the source driver 120 is electrically connected to the display panel 110 for converting image data into source driving signals and transmitting the source driving signals to the display panel 110, and the gate drivers 130A, 130B are respectively disposed on left and right sides of the display panel 110, and the gate drivers 130A, 130B are disposed on left and right sides of the display panel for transmitting image data to the display panel 110, and the display panel 130B may be designed to be different display panel positions according to other display driving signals.
Referring to fig. 2, fig. 2 is a schematic diagram illustrating a gate driving circuit 200 according to an embodiment of the invention. The gate driving circuit 200 is suitable for the display device 100 of fig. 1 or other similar display devices. The following description will be given taking the display device 100 used in fig. 1 as an example. The gate driving circuit 200 is divided into a first gate driving circuit 200A and a second gate driving circuit 200B, wherein the first gate driving circuit 200A is a part of the gate driver 130A, and the second gate driving circuit 200B is a part of the gate driver 130B.
The first gate driving circuit 200A includes clock signal lines L-L, a start signal line S, an end signal line R, and N stages of first shift registers 210A (1) -210A (N), and the second gate driving circuit 200B includes clock signal lines L ' L ', a start signal line S ', an end signal line R ', and N stages of second shift registers 210B (1) -210B (N), where N is a positive integer greater than or equal to 8. in some embodiments, N is a multiple of 8. the clock signal lines L-L8 are used to provide clock signals C1-C8 to the corresponding first shift registers 210A (1) -210A (N), and the clock signal lines L ' L ' are used to provide clock signals C1 ' C8 ' to the corresponding second shift registers 210B (1) -210B (N), where each clock signal C1-C1 ' takes the same number of start signal lines, the same number of clock signals C8 ' as the start signal lines providing the start signal, the end signal line R ' and the start signal line R ' writing signal to the N stage of the first shift registers 210A, the second shift register 210B (1-210B), and the end signal line V # 8 are used to provide the start signal writing time signals H ', and the second shift register 210H ', and the end signal lines V # 8 ' for writing the second shift registers 210H + V +.
The first shift registers 210A (1) to 210A (n) respectively generate scan signals OUT (1) to OUT (n) for driving odd-numbered pixel rows (row) of the display panel 110 at a specific data writing time. The second shift registers 210B (1) to 210B (N) respectively generate scan signals OUT '(1) to OUT' (N) for driving even pixel rows of the display panel 110 at a specific data writing time. The scanning signals OUT (1) to OUT (N) and the scanning signals OUT '(1) to OUT' (N) of the same stage differ by one data writing time H. For example, the 1 st stage scan signal OUT (1) lags the 1 st stage scan signal OUT' (1) by one data write time H.
In the gate driving circuit 200 of fig. 2, each of the first shift registers 210A (1) -210A (n) and each of the second shift registers 210B (1) -210B (n) are coupled to the previous shift register or the next shift register, and the scan signal outputted from the previous shift register or the next shift register is used to control the scan signal level outputted from the previous shift register or the next shift register, so that the gate driving circuit 200 can reduce the use of additional control signals and the cross-over of signal lines in the circuit layout.
FIG. 3 is a schematic diagram of an equivalent circuit of a shift register 300 according to an embodiment of the invention. The shift register 300 may be any one of the first shift registers 210A (1) to 210A (n) and the second shift registers 210B (1) to 210B (n) of fig. 2. The shift register 300 includes a precharge unit 310, a pull-up unit 320, a first pull-down unit 330, and a second pull-down unit 340.
The precharge unit 310 receives the input signals IN1, IN2, and outputs a precharge signal from the node X according to the input signals IN1, IN 2. The pre-charge unit 310 includes transistors M1, M2, wherein the gate and the first source drain of the transistor M1 receive the input signal IN1, the second source drain of the transistor M1 is coupled to the node X to output the pre-charge signal, the gate and the first source drain of the transistor M2 receive the input signal IN2, and the second source drain of the transistor M2 is coupled to the second source drain of the transistor M1.
If the shift register 300 is the 1 st stage first shift register 210A (1) or the 1 st stage second shift register 210B (1) IN fig. 2, the input signal IN1 is the start signal STV or STV ', and the input signal IN2 is the scan signal OUT (2) output by the 2 nd stage first shift register 210A (2) or the scan signal OUT' (2) output by the 2 nd stage second shift register 210B (2).
If the shift register 300 is any one of the 2 nd to (N-1) th stage first shift registers 210A (2) -210A (N-1) and the 2 nd to (N-1) th stage second shift registers 210B (2) -210B (N-1) IN fig. 2, the input signal IN1 and the input signal IN2 are respectively a scan signal output by a first shift register of the previous stage and a scan signal output by a first shift register of the next stage, or respectively a scan signal output by a second shift register of the previous stage and a scan signal output by a second shift register of the next stage. Taking the ith stage of the first shift register 210A (i) as an example (i is a positive integer greater than 1 and less than N), the input signal IN1 is the scan signal OUT (i-1) output by the (i-1) th stage of the shift register 210A (i-1), and the input signal IN2 is the scan signal OUT (i +1) output by the (i +1) th stage of the shift register 210A (i + 1).
If the shift register 300 is the Nth stage of the first shift register 210A (N) or the Nth stage of the second shift register 210B (N) IN FIG. 2, the input signal IN1 is the scan signal OUT (N-1) outputted from the (N-1) th stage of the first shift register 210A (N-1) or the scan signal OUT '(N-1) outputted from the (N-1) th stage of the second shift register 210B (N-1), and the input signal IN2 is the end signal RSTV or RSTV'.
The pull-up unit 320 is coupled to the pre-charge unit 310, which receives the pre-charge signal and the clock signals CN1, CN2, and outputs the scan signal out from the node Y according to the pre-charge signal and the clock signals CN1, CN 2. the pull-up unit 320 includes transistors M3, M4 and a capacitor Cx., the gate of the transistor M3 receives the pre-charge signal, the first source and drain of the transistor M3 receives the clock signal CN1, the second source and drain of the transistor M3 is coupled to the node Y and outputs the scan signal out, the first terminal of the capacitor Cx is coupled to the gate of the transistor M3, and the second terminal of the capacitor Cx is coupled to the second source and drain of the transistor M3, the gate of the transistor M4 receives the clock signal CN2, the first source and drain of the transistor M4 is coupled to the reference potential drain VG L, and the second source and drain of the transistor M4 is coupled to the gate of the transistor M3.
The clock signals CN1 and CN2 are two different clock signals C1 to C8 or two different clock signals C1 'to C8', respectively, and the clock signals CN1 and CN2 have a difference of 10 data writing times H. In other words, the time point when the clock signal CN1 transits from high to low differs from the time point when the clock signal CN2 transits from low to high by two data writing times H. For example, when the clock signal CN1 is the clock signal C1, the clock signal CN2 may be the clock signal C6. Referring to fig. 4, the clock signal C1 changes from low to high at time t2, and the clock signal C6 changes from low to high at time t12, wherein the difference between time t12 and time t2 is 10 data writing times H. In other words, the clock signal C1 has already transitioned from high to low at time t10, and the clock signal C6 transitions from low to high at time t12, wherein the difference between time t12 and time t10 is two data writing times H.
The first pull-down unit 330 is coupled to the pre-charge unit 310 and the pull-up unit 320, receives the pre-charge signal and the pull-down control signals GPW 1, GPW 2, and controls whether to pull down the scan signal OUT to the reference potential VG 2 according to the pre-charge signal and the pull-down control signals GPW 01, GPW 12, after the first pull-down unit 330 pulls down the scan signal OUT to the reference potential VG, the first pull-down unit 330 maintains the scan signal OUT at the reference potential VG, the first pull-down unit 330 includes transistors M-M, such as amorphous silicon thin film transistors or low temperature polysilicon thin film transistors, but not limited thereto, the gate of the transistor M and the first source/drain input pull-down control signal GPW 1, the gate of the transistor M inputs the pull-down control signal GPW 2, the first source/drain of the transistor M is coupled to the reference potential VG, the second source/drain of the transistor M is coupled to the second source/drain of the transistor M, the gate of the transistor M is coupled to the gate node X, the first source/drain of the transistor M is coupled to the reference potential VG, the drain of the transistor M is coupled to the second source/drain of the transistor M, the gate of the reference potential VG, the second source/drain of the transistor M is coupled to the gate of the reference potential of the transistor M, and the gate of the transistor M is coupled to the reference potential of the gate of the transistor M, the reference potential of the transistor M, the drain of the transistor M is coupled to the second source/drain of.
The second pull-down unit 340 is coupled to the pre-charge unit 310 and the pull-up unit 320, receives the pre-charge signal and the pull-down control signals GPW L, GPW L2, and controls whether to pull down the scan signal OUT to the reference potential VG L2 according to the pre-charge signal and the pull-down control signals GPW 3601, GPW L, after the second pull-down unit 340 pulls down the scan signal OUT to the reference potential VG L, the second pull-down unit 340 maintains the scan signal OUT at the reference potential VG L, the second pull-down unit 340 includes transistors M L-M14, the transistors M L-M L can be amorphous silicon thin film transistors or low temperature thin film transistors, but not limited thereto, the gate of the transistor M L and the first source drain of the pull-down control signal GPW L, the gate of the transistor M L is coupled to the pull-down control signal GPW L, the first source drain of the transistor M L is coupled to the reference potential VG 72, the gate of the second drain of the transistor M L is coupled to the gate of the second drain of the transistor M L, the second drain is coupled to the reference potential M L, the gate of the drain of the transistor M L, the drain of the transistor M L is coupled to the gate of the drain of the second drain of the transistor M L, the drain is coupled to the gate of the drain of the transistor M L, the drain is coupled to the drain of the transistor M L, the drain of the second drain is coupled to the drain of the transistor M L, the drain of the transistor M L is coupled to the drain of the transistor M L, the transistor M L.
Referring to fig. 4, fig. 4 shows a timing diagram of the gate driving circuit 200A of fig. 2, as shown in fig. 4, the start signal STV rises from the low level to the high level (i.e., the reference potential VGH) at time t0, and then the clock signals C1 to C8 rise to the high level at time t2, t4, … and t16 in sequence, so that the scan signals OUT (1) to OUT (n) rise to the high level in sequence (fig. 4 only shows the scan signals OUT (1) to OUT (3)), the clock signals C1 to C8 fall to the low level (i.e., the reference potential VG L), so that the scan signals OUT (1) to OUT (8) fall to the low level, the clock signal C2 lags two data writing times H behind the clock signal C1, the clock signal C3 lags two data writing times H behind the clock signal C2, and so on the scan signals OUT (4) to OUT (OUT n) (not shown in the figure) are also shown as the rising and falling times of the rising and falling to the pixel driving the row 110.
For each of the shift registers 210A (1) -210A (N), 210B (1) -210B (N) of fig. 2, the transistor M1 is turned on by the input signal IN1 before the two data writing times H when the scan signals OUT (1) -OUT (N), OUT '(1) -OUT' (N) are raised from the reference potential VG L to the reference potential VGH, so that the potential of the node X is raised to the reference potential VGH minus the threshold voltage Vt (i.e., VGH-Vt) of the transistor M1.
Then, after two data writing time periods H, the transistor M3 is turned on by the clock signal CN1, so that the potential of the node X is raised to VGH-Vt + Vc by the coupling effect of the capacitor Cx, and the scan signals OUT (1) -OUT (N), OUT '(1) -OUT' (N) are raised to the reference potential VGH from the reference potential VG L. in the present embodiment, the voltage difference Vc is (VGH-VG L) × [ Cgs/(Cpl+Cgs)]In which C isgsIs the parasitic capacitance of transistor M3, and CplThe equivalent capacitance seen for node X.
Then, after 8 data writing time periods H, the transistor M3 is turned off by the clock signal CN1, so that the potential of the node X is lowered to VGH-Vt, and the scan signals OUT (1) -OUT (N), OUT '(1) -OUT' (N) are lowered from the reference potential VGH to the reference potential VG L.
Finally, after two data writing times H, the transistor M2 is turned off by the input signal IN2, and the transistor M4 is turned on by the clock signal CN2, so that the potential at the node X is reduced to the reference potential VG L.
Taking the shift register 210A (1) as an example, at a time point t0, the start signal STV is raised to the reference potential VGH, the transistor M1 is turned on, the potential of the node X is raised to VGH-Vt., at a time point t2, the clock signal C1 is raised to the reference potential VGH, the transistor M3 is turned on, the potential of the node X is raised to VGH-Vt + Vc by the coupling action of the capacitor Cx, and the scan signal OUT (1) is raised from the reference potential VG L to the reference potential VGH.
In the timing diagram shown in fig. 4, when the scan signals OUT (1) -OUT (N), OUT ' (1) -OUT ' (N) are raised from the reference potential VG L to the reference potential VGH, the potential of the node X is raised to VGH-Vt, but not directly raised to VGH-Vt + Vc. until the two data writing times H pass, the potential of the node X is raised from VGH-Vt to VGH-Vt + Vc., and when the scan signals OUT (1) -OUT (N), OUT ' (1) -OUT ' (N) are lowered from VGH-to the reference potential VG L, the potential of the node X is lowered to VGH-Vt, but not directly lowered to the reference potential VG L until the two data writing times H pass, the circuit diagram shown in fig. 3 and the timing diagram shown in fig. 4 are advantageous in that the scan signals OUT (OUT 1) (OUT N), OUT 1 ' (N) are completely lowered from VGH-Vt to the reference potential VG 29, and that the display quality of the device is not easily disturbed by the transistors M, the horizontal display, and the display quality of the device is more stable.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (13)

1. A shift register, comprising:
a pre-charge unit for receiving a first input signal and a second input signal and for outputting a pre-charge signal from a first node according to the first input signal and the second input signal, wherein the pre-charge unit comprises:
a first transistor, having a gate and a first source/drain receiving the first input signal, and a second source/drain coupled to the first node and outputting the precharge signal; and
a second transistor, the gate and the first source/drain of which receive the second input signal, and the second source/drain of which is coupled to the second source/drain of the first transistor;
a pull-up unit coupled to the pre-charge unit, the pull-up unit being configured to output a scan signal from a second node according to the pre-charge signal, a first clock signal and a second clock signal, wherein the pull-up unit comprises:
a third transistor, having a gate receiving the pre-charge signal, a first source/drain receiving the first clock signal, and a second source/drain coupled to the second node and outputting the scan signal;
a capacitor having a first end coupled to the gate of the third transistor and a second end coupled to the second source/drain of the third transistor; and
a fourth transistor, the gate of which receives the second clock signal, the first source/drain of which is coupled to the reference potential, and the second source/drain of which is coupled to the gate of the third transistor;
a first pull-down unit coupled to the pre-charge unit and the pull-up unit, the first pull-down unit configured to receive the pre-charge signal, a first pull-down control signal and a second pull-down control signal and configured to control whether to pull down the scan signal to the reference potential according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal; and
a second pull-down unit coupled to the pre-charge unit and the pull-up unit, the second pull-down unit configured to receive the pre-charge signal, the first pull-down control signal and the second pull-down control signal, and configured to control whether to pull down the scan signal to the reference potential according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal.
2. The shift register of claim 1, wherein the first input signal is a start signal, and the second input signal is a scan signal output by a shift register corresponding to a next stage of the shift register.
3. The shift register of claim 1, wherein the first input signal is a scan signal output from a shift register corresponding to a previous stage of the shift register, and the second input signal is a scan signal output from a shift register corresponding to a next stage of the shift register.
4. The shift register of claim 1, wherein the first input signal is a scan signal output from a shift register corresponding to a previous stage of the shift register, and the second input signal is an end signal.
5. The shift register as claimed in claim 1, wherein the first clock signal is switched from high to low at a first time point, the second clock signal is switched from low to high at a second time point after the first time point, and the second time point is different from the first time point by two data writing times.
6. The shift register of claim 1, wherein the first pull-down unit comprises:
a fifth transistor, the gate and the first source/drain of which are inputted with the first pull-down control signal;
a sixth transistor, having a gate to which the second pull-down control signal is inputted, a first source/drain coupled to the reference potential, and a second source/drain coupled to the second source/drain of the fifth transistor;
a seventh transistor, having a gate coupled to the first node, a first source/drain coupled to the reference potential, and a second source/drain coupled to the second source/drain of the fifth transistor;
an eighth transistor, having a gate coupled to the second source/drain of the seventh transistor, a first source/drain coupled to the reference potential, and a second source/drain coupled to the first node; and
a ninth transistor, having a gate coupled to the second source/drain of the seventh transistor, a first source/drain coupled to the reference potential, and a second source/drain coupled to the second node.
7. The shift register of claim 1, wherein the second pull-down unit comprises:
a tenth transistor having a gate and a first source/drain to which the second pull-down control signal is inputted;
an eleventh transistor, having a gate to which the first pull-down control signal is inputted, a first source/drain coupled to the reference potential, and a second source/drain coupled to the second source/drain of the tenth transistor;
a twelfth transistor having a gate coupled to the first node, a first source/drain coupled to the reference potential, and a second source/drain coupled to the second source/drain of the tenth transistor;
a thirteenth transistor, having a gate coupled to the second source/drain of the twelfth transistor, a first source/drain coupled to the reference potential, and a second source/drain coupled to the first node; and
a fourteenth transistor, whose gate is coupled to the second source/drain of the twelfth transistor, whose first source/drain is coupled to the reference potential, and whose second source/drain is coupled to the second node.
8. A display device, comprising:
a display panel;
a plurality of clock signal lines to provide a plurality of clock signals; and
a shift register device for driving the display panel, the shift register device comprising a plurality of shift registers, each of the shift registers being coupled to a previous shift register or a next shift register, wherein each of the shift registers comprises:
a pre-charge unit for receiving a first input signal and a second input signal and for outputting a pre-charge signal from a first node according to the first input signal and the second input signal, wherein the pre-charge unit comprises:
a first transistor, the gate and the first source/drain of which receive the first input signal, and the second source/drain of which outputs the pre-charge signal; and
a second transistor, the gate and the first source/drain of which receive the second input signal, and the second source/drain of which is coupled to the second source/drain of the first transistor;
a pull-up unit coupled to the pre-charge unit, the pull-up unit configured to output a scan signal from a second node according to the pre-charge signal, a first clock signal of the clock signals, and a second clock signal, wherein the pull-up unit comprises:
a third transistor, having a gate receiving the pre-charge signal, a first source/drain coupled to a first clock signal line of the clock signal for providing the first clock signal, and a second source/drain outputting the scan signal;
a capacitor having a first end coupled to the gate of the third transistor and a second end coupled to the second source/drain of the third transistor; and
a fourth transistor, having a gate coupled to a second clock signal line for providing the second clock signal among the clock signals, a first source/drain coupled to a reference potential, and a second source/drain coupled to a gate of the third transistor;
a first pull-down unit coupled to the pre-charge unit and the pull-up unit, the first pull-down unit configured to receive the pre-charge signal, a first pull-down control signal and a second pull-down control signal and configured to control whether to pull down the scan signal to the reference potential according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal; and
a second pull-down unit coupled to the pre-charge unit and the pull-up unit, the second pull-down unit configured to receive the pre-charge signal, the first pull-down control signal and the second pull-down control signal, and configured to control whether to pull down the scan signal to the reference potential according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal.
9. The display device according to claim 8, wherein the shift register is an N-stage shift register, wherein the first input signal and the second input signal in the 1 st stage shift register are a start signal and a scan signal output by the 2 nd stage shift register, respectively, the first input signal and the second input signal in the N-stage shift register are a scan signal and an end signal output by the (N-1) th stage shift register, respectively, and the first input signal and the second input signal in the i-th stage shift register are a scan signal output by the (i-1) th stage shift register and a scan signal output by the (i +1) th stage shift register, respectively, wherein i is a positive integer greater than 1 and less than N.
10. The display device as claimed in claim 8, wherein the first clock signal is switched from a high level to a low level at a first time point, the second clock signal is switched from the low level to the high level at a second time point after the first time point, and the second time point is different from the first time point by two data writing times.
11. A shift register, comprising:
a precharge unit to receive a first input signal and a second input signal and to output a precharge signal from a first node according to the first input signal and the second input signal;
a pull-up unit coupled to the pre-charge unit, the pull-up unit being configured to output a scan signal from a second node according to the pre-charge signal, a first clock signal and a second clock signal, wherein after the first clock signal is lowered from a high level to a low level, the second clock signal is raised from the low level to the high level to pull down the level of the pre-charge signal;
a first pull-down unit coupled to the pre-charge unit and the pull-up unit, the first pull-down unit configured to receive the pre-charge signal, a first pull-down control signal and a second pull-down control signal and configured to control whether to pull down the scan signal to a reference potential according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal; and
a second pull-down unit coupled to the pre-charge unit and the pull-up unit, the second pull-down unit configured to receive the pre-charge signal, the first pull-down control signal and the second pull-down control signal and configured to control whether to pull down the scan signal to the reference potential according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal;
the first input signal is a start signal, and the second input signal is a scan signal output by a next stage of the shift register.
12. A shift register, comprising:
a precharge unit to receive a first input signal and a second input signal and to output a precharge signal from a first node according to the first input signal and the second input signal;
a pull-up unit coupled to the pre-charge unit, the pull-up unit being configured to output a scan signal from a second node according to the pre-charge signal, a first clock signal and a second clock signal, wherein after the first clock signal is lowered from a high level to a low level, the second clock signal is raised from the low level to the high level to pull down the level of the pre-charge signal;
a first pull-down unit coupled to the pre-charge unit and the pull-up unit, the first pull-down unit configured to receive the pre-charge signal, a first pull-down control signal and a second pull-down control signal and configured to control whether to pull down the scan signal to a reference potential according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal; and
a second pull-down unit coupled to the pre-charge unit and the pull-up unit, the second pull-down unit configured to receive the pre-charge signal, the first pull-down control signal and the second pull-down control signal and configured to control whether to pull down the scan signal to the reference potential according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal;
the first input signal is a scan signal output by a previous stage of the shift register corresponding to the shift register, and the second input signal is a scan signal output by a next stage of the shift register corresponding to the shift register.
13. A shift register, comprising:
a precharge unit to receive a first input signal and a second input signal and to output a precharge signal from a first node according to the first input signal and the second input signal;
a pull-up unit coupled to the pre-charge unit, the pull-up unit being configured to output a scan signal from a second node according to the pre-charge signal, a first clock signal and a second clock signal, wherein after the first clock signal is lowered from a high level to a low level, the second clock signal is raised from the low level to the high level to pull down the level of the pre-charge signal;
a first pull-down unit coupled to the pre-charge unit and the pull-up unit, the first pull-down unit configured to receive the pre-charge signal, a first pull-down control signal and a second pull-down control signal and configured to control whether to pull down the scan signal to a reference potential according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal; and
a second pull-down unit coupled to the pre-charge unit and the pull-up unit, the second pull-down unit configured to receive the pre-charge signal, the first pull-down control signal and the second pull-down control signal and configured to control whether to pull down the scan signal to the reference potential according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal;
the first input signal is a scan signal output by a shift register of a previous stage corresponding to the shift register, and the second input signal is an end signal.
CN201511027073.0A 2015-12-31 2015-12-31 Shift register and display device Active CN106935168B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201511027073.0A CN106935168B (en) 2015-12-31 2015-12-31 Shift register and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201511027073.0A CN106935168B (en) 2015-12-31 2015-12-31 Shift register and display device

Publications (2)

Publication Number Publication Date
CN106935168A CN106935168A (en) 2017-07-07
CN106935168B true CN106935168B (en) 2020-08-07

Family

ID=59441237

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201511027073.0A Active CN106935168B (en) 2015-12-31 2015-12-31 Shift register and display device

Country Status (1)

Country Link
CN (1) CN106935168B (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106024065B (en) * 2016-05-18 2019-12-17 上海天马微电子有限公司 Shifting register, grid driving circuit, array substrate and display device
CN109461411B (en) * 2017-09-06 2020-08-07 瀚宇彩晶股份有限公司 Grid driving circuit and display panel
CN109473069B (en) * 2017-09-07 2021-03-23 瀚宇彩晶股份有限公司 Gate drive circuit and display panel
CN108231032B (en) * 2018-02-26 2021-01-26 京东方科技集团股份有限公司 Shift register, grid drive circuit and display device
CN110556069A (en) * 2018-05-31 2019-12-10 瀚宇彩晶股份有限公司 Shift register with surge noise suppression function and driving method thereof
CN110379349B (en) * 2019-07-22 2020-10-16 深圳市华星光电半导体显示技术有限公司 Gate drive circuit
CN112349251B (en) * 2019-08-08 2022-03-29 瀚宇彩晶股份有限公司 Gate drive circuit and drive method of display panel
CN112820227B (en) * 2019-11-18 2024-05-07 瀚宇彩晶股份有限公司 Gate driving circuit
TWI726564B (en) 2019-12-31 2021-05-01 財團法人工業技術研究院 Pixel array with gate driver and matrix sensor array
CN113160732B (en) * 2020-01-22 2024-04-30 瀚宇彩晶股份有限公司 Gate driving circuit
CN113643638B (en) * 2020-04-27 2024-04-30 瀚宇彩晶股份有限公司 Gate driving circuit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104050935B (en) * 2013-03-11 2016-12-28 瀚宇彩晶股份有限公司 Shift register, bi-directional shift apparatus for temporary storage and apply its display panels
CN104575409B (en) * 2013-10-16 2017-08-18 瀚宇彩晶股份有限公司 Liquid crystal display and its bi-directional shift apparatus for temporary storage

Also Published As

Publication number Publication date
CN106935168A (en) 2017-07-07

Similar Documents

Publication Publication Date Title
CN106935168B (en) Shift register and display device
US10803823B2 (en) Shift register unit, gate driving circuit, and driving method
US10127875B2 (en) Shift register unit, related gate driver and display apparatus, and method for driving the same
KR101580422B1 (en) Shift register, display apparatus, gate driving circuit, and driving method
US10438676B2 (en) Bidirectional shift register units, bidirectional shift registers, and display panels
CN109461411B (en) Grid driving circuit and display panel
CN106297624B (en) Shift register and display device
US8269713B2 (en) Shift register
KR102607402B1 (en) Gate driving circuit and display device using the same
US9786241B2 (en) Liquid crystal display and gate driver on array circuit
CN107689217B (en) Gate drive circuit and display device
KR20100048103A (en) Method for driving gate line, gate driving circuit performing for the method and display apparatus having the gate driving circuit
CN107689213B (en) Gate drive circuit and display device
US20140372494A1 (en) Gate driver circuit
US10249233B2 (en) Gate driving circuit and display device
US9325311B1 (en) Gate driver and display device using the same
US10403382B2 (en) Gate driving circuit and display apparatus
US20200168285A1 (en) Shift register and gate driver circuit
US10692415B2 (en) Gate driving circuit of irregular screen panel and driving method
CN111105753B (en) Gate drive circuit and display device
TWI588832B (en) Shift register and display apparatus
US8665408B2 (en) Liquid crystal display device
CN111899697A (en) Grid driving circuit and driving method of touch display panel
KR101377463B1 (en) Circuit for removing noise, gate driving circuit having the same and display device having the gate driving circuit
CN112349251B (en) Gate drive circuit and drive method of display panel

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant