KR101377463B1 - Circuit for removing noise, gate driving circuit having the same and display device having the gate driving circuit - Google Patents

Abstract

In the noise removing circuit, the gate driving circuit and the display device including the same, the noise removing circuit includes a first switching unit, a second switching unit, and a third switching unit. The first switching unit outputs a high level output signal through the output terminal. The second switching unit includes an input terminal to which a low level input signal is input, an output terminal connected to an output terminal of the first switching unit, and control terminals to sequentially receive a plurality of control signals. The third switching unit switches the first terminal and the second terminal based on a signal input to the control terminal connected to the output terminals of the first and second switching units. Accordingly, the noise of the first and second terminals can be canceled by electrically shorting the first and second terminals.

Shift register, gate drive circuit, pull up section, noise cancellation

Description

TECHNICAL FIELD [0001] The present invention relates to a noise canceling circuit, a gate driving circuit and a display device having the same,

1 is a plan view of a display device according to an exemplary embodiment of the present invention.

FIG. 2 is a detailed block diagram of the gate driving circuit shown in FIG. 1.

3 is a detailed circuit diagram of the stage shown in FIG.

FIG. 4 is a detailed circuit diagram of the noise removing circuit shown in FIG. 2.

5 is a timing diagram of an input / output signal of the gate driving circuit shown in FIG. 2.

6A is a signal waveform diagram of the first node of the stage shown in FIG. 3.

FIG. 6B is an enlarged view of portion “A” shown in FIG. 6A.

Description of the Related Art

100: display panel 200: gate driving circuit

SRCm: mth stage NRCk: kth noise canceling circuit

210: pull-up part 220: pull-down part

242: first holding part 244: second holding part

246: third holding part 248: fourth holding part

310: first switching unit 330: second switching unit

350: third switching unit 400: source driving circuit

500: printed circuit board

The present invention relates to a noise removing circuit, a gate driving circuit and a display device having the same, and more particularly, to a noise removing circuit for removing a noise phenomenon occurring at a high temperature, and a gate driving circuit and a display device having the same. .

Recently, the so-called ASG (Amorphous Silicon Gate), which simultaneously forms a gate driving circuit in the peripheral area of the panel during the process of forming a switching element located in the display area of the panel, in order to reduce the manufacturing cost and reduce the overall size of the panel module for a display device. Technology is being applied.

However, in the case of the display device using the ASG technology, when the gate driving circuit rises to a high temperature higher than room temperature (for example, 60 ° C. or more) due to the driving for a long time, noise occurs in the gate signal. Since the noise of such gate signal results in poor display quality, improvement of the gate signal is required.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a noise removing circuit for removing high temperature noise.

Another object of the present invention is to provide a gate driving circuit for minimizing the occurrence of noise in the gate signal at a high temperature.

Another object of the present invention is to provide a display device including the gate driving circuit.

The noise removing circuit according to the embodiment for realizing the object of the present invention includes a first switching unit, a second switching unit, and a third switching unit. The first switching unit outputs a high level output signal through an output terminal. The second switching unit includes an input terminal to which a low level input signal is input, an output terminal connected to an output terminal of the first switching unit, and control terminals to sequentially receive a plurality of control signals. The third switching unit switches the first terminal and the second terminal based on a signal input to a control terminal connected to an output terminal of the first and second switching units.

According to another aspect of the present invention, a gate driving circuit includes an m (m is a natural number) stage, an m + 1 stage, and a noise removing circuit. The m-th stage includes a pull-up unit which pulls up the first clock signal to a high level of the m-th gate signal and outputs the first clock signal. The m + 1th stage is connected to the mth stage, and includes a pullup unit configured to pull up a second clock signal to a high level of the m + 1th gate signal and output the same. The noise removing circuit electrically shorts the control terminal of the pull-up unit of the m-th stage and the control terminal of the pull-up unit of the m + 1th stage in response to the first and second clock signals to control the pull-up unit of the m-th stage. The noise of the stage and the noise of the control stage of the pull-up section of the m + 1th stage are canceled out.

According to another exemplary embodiment of the present invention, a display device includes a display panel, a source driving circuit, and a gate driving circuit. The display panel includes a display area in which gate wires and source wires that cross each other are formed to display an image, and a peripheral area surrounding the display area. The source driving circuit outputs data signals to the source wirings. The gate driving circuit includes a plurality of stages integrated in the peripheral area and outputting gate signals to the gate lines. The gate driving circuit includes a m-th stage including a pull-up unit configured to pull up a first clock signal to a high level of an m (m is a natural number) gate signal and output a second clock signal to a high level of the m + 1 th gate signal. An m + 1 th stage including a pull-up part for outputting to a level and outputting the level; and electrically controlling a control end of the pull-up part of the m-th stage and a control end of the pull-up part of the m + 1th stage in response to the first and second clock signals. The short circuit cancels the noise of the control stage of the pull-up unit of the m-th stage and the noise of the control stage of the pull-up unit of the m + 1th stage.

According to such a noise removing circuit, a gate driving circuit and a display device including the same, the display quality can be improved by removing noise generated during high temperature driving.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a schematic plan view of a display device according to an embodiment of the present invention.

Referring to FIG. 1, a display device includes a display panel 100, a gate driving circuit 200, a source driving circuit 400, and a printed circuit board 500.

The display panel 100 includes a display area DA and a peripheral area PA surrounding the display area DA. The display area DA includes gate lines, source lines, and a plurality of pixel units that cross each other. Each pixel portion P includes a switching element TFT electrically connected to a gate line GL and a source line DL, a liquid crystal capacitor CLC electrically connected to the switching element TFT, and the liquid crystal capacitor CLC. ) And a storage capacitor (CST) in parallel.

The gate driving circuit 200 includes a shift register for sequentially outputting gate signals to the gate lines and a plurality of noise removing circuits NRCk (k is a natural number) for removing noise generated in the gate signals. . The shift register includes a plurality of stages SCRm and SCRm + 1 (m is a natural number), and the kth noise eliminating circuit NRCk includes the mth stage SCRm and the (m + 1) th stage SCRm + Noise of the m th gate signal and the m + 1 th gate signal, which are output signals of 1), is removed. The gate driving circuit 200 is preferably integrated in the peripheral area PA corresponding to one end of the gate lines.

The source driving circuit 400 includes a source driving chip 410 for outputting data signals to the source wirings, and the source driving chip 410 is mounted to the printed circuit board 500 and the display panel 100. It includes a flexible circuit board 430 for electrically connecting the. Here, although the source driving chip 410 is mounted on the flexible circuit board 430 as an example, the source driving chip 410 may be directly mounted on the display panel 100, and the source driving chip ( The 410 may be directly integrated in the peripheral area PA of the display panel 100.

FIG. 2 is a detailed block diagram of the gate driving circuit shown in FIG. 1. 3 is a detailed circuit diagram of the stage of FIG. 2, FIG. 4 is a detailed circuit diagram of the noise removing circuit of FIG. 2, and FIG. 5 is a timing diagram of an input / output signal of the gate driving circuit shown in FIG. 2.

Referring to FIG. 2, the gate driving circuit includes a shift register SRC including first to n + 1 stages SRC1 to SRCn + 1 connected to each other and first to nth connected to adjacent stages. / 2 noise cancellation circuits (NRC1 ~ NRCn / 2).

The first to nth + 1 stages SRC1 to SRCn + 1 are the first to nth stages SRC1 to SRCn that output n gate signals and the first to nth + 1 stages SRC1 to SRCn + 1. ), The n + 1th stage SRCn + 1 outputs a reset signal. In order to minimize noise that may be included in the output of the n th stage SCRn during the porch period, the n th +2 th stage SRCn + 2 may be further included.

Each of the first to n + 1th stages SRC1 to SRCn + 1 includes a first clock terminal CK1, a second clock terminal CK2, a first input terminal IN1, a second input terminal IN2, The voltage terminal VSS, the reset terminal RE, the carry terminal CR, the output terminal OUT, and the node terminal ND are included.

The first clock signal CK and the second clock signal CKB having opposite phases are provided to the first clock terminal CK1 and the second clock terminal CK2. Specifically, the first clock signal CK is provided to the first clock terminal CK1 of the odd-numbered stages SRC1, SRC3,..., SRCn + 1, and the second clock terminal CK2 is provided to the first clock signal CK1. The second clock signal CKB is provided. The second clock signal CKB is provided to the first clock terminal CK1 of the even-numbered stages SRC2, SRC4, SRCn and the first clock signal CK2 is supplied to the second clock terminal CK2. (CK) is provided.

The first input terminal IN1 is provided with a vertical start signal STV or a carry signal of a previous stage. That is, the vertical start signal STV is provided to the first input terminal IN1 of the first stage SRC1 as the first stage, and the vertical start signal STV of the second to the (n + 1) One input terminal IN1 is provided with carry signals of the previous stages SRC1 to SRCn, respectively.

The second input terminal IN2 is provided with a gate signal or a vertical start signal STV of a next stage. Gate signals of the next stages SRC2 to SRCn + 1 are respectively provided to the second input terminals IN2 of the first to nth stages SRC1 to SRCn, and the n + 1th stage SRCn + 1 is provided. The vertical start signal STV is provided to the second input terminal IN2.

An off voltage VOFF is provided to the voltage terminal VSS, and a carry signal of the n + 1th stage SRCn + 1 is provided as a reset signal to the reset terminal RE.

The output terminal (OUT) outputs a gate signal to an electrically connected gate wiring. The odd-numbered gate signal output from the output terminal OUT of the odd-numbered stages SRC1, SRC3,..., SRCn + 1 is output in a high section of the first clock signal CK. The even-numbered gate signal output from the output terminal OUT of the even-numbered stages SRC2, SRC4,..., SRCn is output in the high period of the second clock signal CKB. Therefore, the first to n + 1th stages SRC1 to SRCn + 1 sequentially output gate signals G1,..., Gn.

The node terminal ND is electrically connected to the first node N1 of each of the first to nth stages SRC1 to SRCn to output a signal of the first node N1. The signal of the first node N1 output from the node terminal ND is input to each of the first to n / 2th noise removing circuits NRC1 to NRCn / 2.

The first to the n / 2 noise removing circuits NRC1 to NRCn / 2 are connected to the odd-numbered stages SRC1, SRC3, ..., SRCn + 1 and the even-numbered stages SRC2, SRC4,. , SRCn). For example, the first noise canceling circuit NRC1 is formed between the first stage SRC1 and the second stage SRC2, and in the same manner, the n / 2th noise canceling circuit NRCn / 2 is configured as the n− It is formed between one stage SRCn-1 and the nth stage SRCn.

Each of the first to n / 2th noise removing circuits NRC1 to NRCn / 2 may include a first clock terminal CK1, a second clock terminal CK2, a first input terminal IN1, and a second input terminal ( IN2), a third input terminal IN3, a fourth input terminal IN4, and a voltage terminal VSS.

The first clock signal CK is provided to the first clock terminal CK1, and the second clock signal CKB is provided to the second clock terminal CK2. The first input terminal IN1 is electrically connected to an output terminal OUT of the odd stages SRC1, SRC3,..., SRCn + 1 to provide the odd gate signal. The second input terminal IN2 is electrically connected to an output terminal OUT of the even-numbered stages SRC2, SRC4, ..., SRCn to provide the even-numbered gate signal.

The third input terminal IN3 is electrically connected to the node terminal ND of the odd stages SRC1, SRC3,..., SRCn + 1, and thus the odd stages SRC1, SRC3,. The signal applied to the control terminal of the pull-up unit 220 of SRCn + 1 is provided. The fourth input terminal IN4 is electrically connected to the node terminals ND of the even-numbered stages SRC2, SRC4, ..., SRCn to form the even-numbered stages SRC2, SRC4, ..., SRCn, The signal applied to the control unit of the pull-up unit 220 is provided.

The off voltage VOFF is provided to the voltage terminal VSS.

3 is a detailed circuit diagram of the stage of FIG. 2, FIG. 4 is a detailed circuit diagram of the noise removing circuit of FIG. 2, and FIG. 5 is a timing diagram of an input / output signal of the gate driving circuit shown in FIG. 2.

3 and 5, the m-th stage SRCm pulls the m-th gate signal Gm into the first clock signal CK in response to the carry signal of the (m-1) th stage SRCm- The off voltage VOFF is applied to the pull-up unit 210 that pulls up the gate signal Gm + 1 in response to the gate signal Gm + 1 of the m + 1th stage SRCm + 1. It includes a pull-down unit 220 to pull down.

The pull-up unit 210 includes a fifth transistor T5 having a gate electrode connected to the first node N1, a drain electrode connected to the first clock terminal CK1, and a source electrode connected to the output terminal OUT. It includes. Therefore, the drain electrode of the fifth transistor T5 is supplied with the first clock signal CK through the first clock terminal CK1.

The pull-down unit 220 has a gate electrode connected to a second input terminal IN2, a drain electrode connected to an output terminal OUT, a source electrode connected to a voltage terminal VSS, and the off voltage VOFF. This includes the sixth transistor T6 provided.

The m-th stage SRCm turns on the pull-up unit 210 in response to a carry signal of the m-th stage SRCm-1, and the gate signal of the m + 1th stage SRCm + 1. And a pull-up driving unit which turns off the pull-up unit 210 in response to Gm + 1). The pull-up driving unit includes a buffer unit 280, a charging unit 270, and a discharging unit 230.

The buffer unit 280 includes a thirteenth transistor in which a gate electrode and a drain electrode are commonly connected to the first input terminal IN1, and a source electrode is connected to the first node N1. The charging unit 270 includes a third capacitor C3 having a first electrode connected to the first node N1 and a second electrode connected to the output terminal OUT. The discharge unit 230 has a gate electrode connected to the second input terminal IN2, a drain electrode connected to the first node N1, and a source electrode connected to the voltage terminal VSS, so that the off voltage VOFF is applied. ) Is provided with a seventh transistor T7.

When the thirteenth transistor T13 is turned on in response to a carry signal of the m-th stage SRCm-1, the pull-up driving unit carries the carry signal of the m-th stage SRCm-1. The first node N1 is switched to a high level by being applied to the first node N1 and at the same time the third capacitor C3 is charged. Thereafter, when the third capacitor (C3) is charged with a charge equal to or higher than the threshold voltage of the fifth transistor (T5) and the first clock signal (CK) becomes a high period, the fifth transistor (T5) The first high-level clock signal CK is output to the output terminal OUT.

That is, the fifth transistor T5 is bootstraped to output the mth gate signal Gm, which is an output signal of the mth stage SRCm. Thereafter, when the seventh transistor T7 is turned on in response to the (m + 1) th gate signal Gm + 1, the charge charged in the third capacitor C3 is converted to the off voltage of the voltage terminal VSS (VOFF) and the fifth transistor T5 is turned off.

The m-th stage SRCm may include a first holding unit for holding a signal of the first node N1, that is, a signal applied to the control terminal of the pull-up unit 210 at a level of the off voltage VOFF 242, and a second holding portion 244.

The first holding part 242 has a gate electrode connected to the first clock terminal CK1, a drain electrode connected to the first node N1, a source electrode connected to the output terminal OUT, 8 transistor T8. The second holding part 244 has a gate electrode connected to the second clock terminal CK2, a drain electrode connected to the first input terminal IN1, and a source electrode connected to the first node N1 And a ninth transistor T9 connected thereto.

The first node 242 and the second holding part 244 have the first node after the m-th gate signal Gm is shifted to the level of the off voltage VOFF by the pull-down part 220. The signal of N1 is maintained at the level of the off voltage VOFF.

That is, when the eighth transistor T8 is turned on in response to the first clock signal CK, the m-th gate signal Gm is discharged to the level of the off voltage VOFF, and the off voltage ( VOFF is applied to the first node N1 to maintain the first node N1 at the level of the off voltage VOFF. In addition, when the ninth transistor T9 is turned on in response to the second clock signal CKB, the off voltage VOFF is applied to the first node N1 so that the first node N1 is turned on. Is maintained at the level of the off voltage VOFF.

In this manner, the first holding part 242 and the second holding part 244 are alternately turned on in response to the first clock signal CK and the second clock signal CKB, respectively, (N1) to the level of the off-voltage (VOFF).

After the gate signal is output, the m-th stage SRCm outputs a first clock signal CK and a second clock signal CKB after the third node N3 is switched to the off voltage VOFF level by the pull- A third holding portion 246 and a fourth holding portion 248 for keeping the third node N3 stably at the off-voltage (VOFF) level before the gate signal of the next frame is outputted irrespective of the external noise, And a switching unit 250 for controlling the on / off operation of the fourth holding unit 248.

The third holding part 246 has a gate electrode connected to the second clock terminal CK2, a drain electrode connected to the output terminal OUT, a source electrode connected to the voltage terminal VSS, and the off voltage ( And a tenth transistor T10 provided with VOFF). The fourth holding part 248 has a gate electrode connected to the second node N2 of the switching part 250, a drain electrode connected to an output terminal OUT, and a source electrode connected to the voltage terminal VSS. And an eleventh transistor T11 connected to receive an off voltage VOFF.

The switching unit 250 includes first to fourth transistors T1, T2, T3, and T4, and first and second capacitors C1 and C2.

The gate electrode and the drain electrode of the first transistor T1 are commonly connected to the first clock terminal CK1 to receive the first clock signal CK, and the source electrode of the drain of the second transistor T2. Connected with the electrode. The gate electrode of the second transistor T2 is connected to the output terminal OUT, and the source electrode is connected to the voltage terminal V to receive the off voltage VOFF. The drain electrode of the third transistor T3 is connected to the first clock terminal CK1, the gate electrode is connected to the first clock terminal CK1 through the first capacitor C1, and the source electrode is It is connected to the second node N2.

Accordingly, the drain electrode and the gate electrode of the third transistor T3 receive the first clock signal CK, and the second capacitor C2 is disposed between the gate electrode and the source electrode of the third transistor T3. Connected. The fourth transistor T4 has a gate electrode connected to an output terminal OUT, a drain electrode connected to a second node N2, a source electrode connected to a voltage terminal VSS, and the off voltage VOFF. To be provided.

When the m-th stage SRCm outputs the first clock signal CK as the gate signal Gm having a high level, the second and fourth transistors T2 as the output terminal OUT is switched to the high level. , T4 is turned on, and accordingly, the off voltage VOFF is applied to the second node N2. In this case, since the first clock signal CK is in a high state, the first and third transistors T1 and T3 also maintain a turn-on state, and thus the first clock signal CK having a high level at the second node N2. ) Is also applied to the gate electrode of the eleventh transistor T11 strictly in proportion to the resistance ratio of the third transistor T3 and the fourth transistor T4 and the voltage level of the first clock signal CK and the off. The divided voltage between the voltage VOFF voltage levels is applied. At this time, if the distributed voltage is designed to be less than the threshold voltage of the eleventh transistor, the eleventh transistor maintains the turn-off state and the third node N3 can maintain the high level state.

When 1H elapses and the high level m + 1 gate signal Gm + 1 is input to the second input terminal IN2, the sixth transistor is turned on so that the third node N3 may turn off the voltage. VOFF), and the second and fourth transistors T2 and T4 are turned off. At the same time, since the second clock signal CK2 becomes high, the tenth transistor T10 is turned on so that the third node N3 reaches the off voltage VOFF more quickly.

The second clock signal CKB and the first clock signal CK are alternately responded to a period other than a period of outputting the m-th gate signal and the m-th gate signal during one frame period. The third node N3 maintains the off voltage VOFF stably without noise by the third holding part 246 and the fourth holding part 248.

The m-th stage of the gate driving circuit 200 further includes a reset unit 260 and a carry unit 290. In the reset unit 260, a gate electrode is connected to the reset terminal RE, a drain electrode is connected to the first node N1, and a source electrode is connected to the voltage terminal VSS. The twelfth transistor T12 provides the off voltage VOFF to N1. The reset unit 160 receives the carry signal of the (n + 1) th stage SRCn + 1 as the last stage and resets the first node N1 of all the stages to the off voltage VOFF after completion of one frame Let's do it. Since the third node N3 of the N + 1th stage SRCn + 1 is not reset until the vertical start signal STV of the next frame is input, the third node N3 turns off the first node N1 during the blank period. It can be kept stable with (VOFF).

The carry unit 290 has a gate electrode connected to the first node N1, a drain electrode connected to the first clock terminal CK1 to receive the first clock signal CK, and a source electrode The fourteenth transistor T14 is connected to the carry terminal CR. The carry unit 290 outputs the high period of the first clock signal CK to the carry terminal CR as the potential of the first node N1 is switched to the high level.

Here, the case where the carry signal outputted from the carry section 290 is supplied to the first input terminal IN1 of the next stage to control the start of operation is taken as an example. However, when the carry section 290 is removed and the output terminal OUT, The gate signal output from the signal may be provided to the first input terminal IN1 of the next stage. However, in the case of XGA or higher resolution panel or large panel, the load on the gate line is relatively larger than that of the low resolution model or the small panel. Therefore, when using the gate signal as a carry signal, the lower part of the panel may not be driven due to signal delay Since it may occur, it is preferable to have a separate carry part 290 as in the present embodiment.

4 and 5, the k-th noise removing circuit NRCk includes a first switching unit 310, a second switching unit 330, and a third switching unit 350.

The first switching unit 310 outputs a high level output signal through an output terminal. For example, the first switching unit 310 responds to the high level of the first clock signal CK. The first switching element TR1 outputting the high level of the signal CK and the second switching element TR2 outputting the high level of the second clock signal in response to the high level of the second clock signal CKB. It includes.

In detail, the first switching element TR1 includes a gate electrode and a source electrode connected in common with the first clock terminal CK1, and a drain electrode connected with the fourth node N4. The second switching element TR2 includes a gate electrode and a source electrode connected in common to the second clock terminal CK2, and a drain electrode connected to the fourth node N4.

The second switching unit 330 includes an input terminal to which a low level input signal is input, an output terminal connected to an output terminal of the first switching unit, and control terminals to sequentially input a plurality of control signals. The control terminals are referred to as first input terminal IN1 and second input terminal IN2.

For example, the second switching unit 330 may turn off the high level of the first clock signal CK in response to the high level of the m-th gate signal Gm, which is an output signal of the m-th stage SRCm. The third switching element TR3 discharges to the level of VOFF and the m + 1 gate signal Gm + 1, which is an output signal of the m + 1th stage SRCm + 1, in response to the high level. And a fourth switching element TR4 for discharging the high level of the two clock signals CKB to the level of the off voltage VOFF.

In detail, the third switching element TR3 includes a gate electrode connected to the first input terminal IN1, a source electrode connected to the fourth node N4, and a drain electrode connected to the voltage terminal VSS. The fourth switching element TR4 includes a gate electrode connected to the second input terminal IN2, a source electrode connected to the fourth node N4, and a drain electrode connected to the voltage terminal VSS.

The third switching unit 350 switches the first terminal and the second terminal based on a signal input to a control terminal connected to the output terminals of the first and second switching units 310 and 330. The first terminal is a terminal connected to the control terminal of the pull-up unit of the m-th stage SRCm, and the second terminal is a terminal connected to the control terminal of the pull-up unit of the m-th stage SRCm + 1.

For example, the third switching unit 350 includes a fifth switching element TR5. The fifth switching element TR5 controls the pull-up unit of the m-th stage SRCm in response to the level of the off voltage VOFF when the third or fourth switching elements TR3 and TR4 are turned on. And electrically open the control terminal of the pull-up unit of the m-th stage SRCm + 1. The fifth switching element TR5 is the first or second clock signal provided from the first or second switching elements TR1 and TR2 when the third and fourth switching elements TR3 and TR4 are turned off. In response to the high level of (CK, CKB), the control stage of the pull-up section of the m-th stage SRCm and the control stage of the pull-up section of the m-th stage SRCm + 1 are electrically shorted. Here, the control terminal of the pull-up unit of the m-th stage SRCm is the first node N1 of the m-th stage SRCm, and the control terminal of the pull-up unit of the m + 1th stage SRCm + 1 is the m-th stage. It is the 1st node N1 of the +1 stage SRCm + 1.

In detail, the fifth switching element TR5 includes a gate electrode connected to the fourth node N4 and a third input terminal through which a signal applied to the first node N1 of the mth stage SRCm is input. A source electrode connected to IN3 and a drain electrode connected to a fourth input terminal IN4 to which a signal applied to the first node N1 of the m + 1th stage SRCm + 1 is input. That is, the fifth switching element TR5 is the first node N1 of the mth stage SRCm and the m + 1th stage SRCm + based on a control signal applied to the fourth node N4. The first node N1 of 1) is electrically opened or shorted.

Specifically, the driving method of the k-th noise removing circuit NRCk is as follows.

When the m-th gate signal Gm is input from the first input terminal IN1, the third switching element TR3 is turned on so that the off voltage VOFF applied to the voltage terminal VSS is turned on. Is applied to the fourth node N4. When the fourth node N4 has the level of the off voltage VOFF, the fifth switching device TR5 is turned off to turn on the first node N1 of the m-th stage SRCm and the m- The first node N1 of the +1 stage SRCm + 1 is electrically open.

Meanwhile, when the m + 1 th gate signal Gm + 1 is input from the second input terminal IN2, the fourth switching element TR4 is turned on and applied to the voltage terminal VSS. An off voltage VOFF is applied to the fourth node N4. When the fourth node N4 has the level of the off voltage VOFF, the fifth switching element TR5 is turned off so that the first node N1 and the mth of the mth stage SRCm are turned off. The first node N1 of the +1 stage SRCm + 1 is electrically open.

That is, while the mth gate signal Gm and the m + 1th gate signal Gm + 1 are input to the first and second input terminals IN1 and IN2, the first stage of the mth stage SRCm The node N1 and the first node N1 of the m + 1th stage SRCm + 1 are electrically open.

Subsequently, the first and second clock terminals G1 and M + 1 gate signals Gm + 1 are not input to the first and second input terminals IN1 and IN2. The first and second clock signals CK and CKB are alternately input to CK1 and CK2.

When the first clock signal CK is input to the first clock terminal CK1, the first switching element TR1 is turned on so that the fourth node N4 is turned on to the first clock signal CK. Has a high level of. Accordingly, the fifth switching element TR5 is turned on so that the first node N1 of the mth stage SRCm and the first node N1 of the m + 1th stage SRCm + 1 are electrically connected. It becomes the short state.

In addition, when the first clock signal CK is not input to the first clock terminal CK1 and the second clock signal CKB is input to the second clock terminal CK2, the second switching device ( TR2 is turned on so that the fourth node N4 has a high level of the second clock signal CKB. Accordingly, the fifth switching element TR5 is turned on so that the first node N1 of the mth stage SRCm and the first node N1 of the m + 1th stage SRCm + 1 are electrically connected. It becomes the short state.

Of course, the first and second clock terminals CK1 may be input while the m-th gate signal Gm and the m + 1 th gate signal Gm + 1 are input to the first and second input terminals IN1 and IN2. The first and second clock signals CK and CKB are also input to CK2. Even when the first and second clock signals CK and CKB are input so that the first and second switching elements TR1 and TR2 are turned on, the third and fourth switching elements TR3 and TR4 are turned on. Since the fourth node N4 is in an on state, the fourth node N4 has a level of the off voltage VOFF. Accordingly, the first node N1 of the m th stage SRCm and the first node N1 of the m + 1 th stage SRCm + 1 are electrically open.

That is, the first and second clocks are input while low levels of the mth gate signal Gm and the m + 1th gate signal Gm + 1 are input to the first and second input terminals IN1 and IN2. The first node N1 of the mth stage SRCm and the first node N1 of the mth + 1th stage SRCm + 1 are electrically shorted by the signals CK and CKB.

Accordingly, the m th stage SRCm of the m th stage SRCm and the m + 1 th stage SRCm + 1 during the frame period in which the m th gate signal and the m th +1 th gate signal have a low level. The first node N1 of the mth stage SRCm is electrically shorted by electrically shorting the first node N1 and the first node N1 of the m + 1th stage SRCm + 1. Noise generated at the first node N1 of (SRCm + 1) is interfered with each other to cancel out

FIG. 6A is a signal waveform diagram of the first node N1 of the stage shown in FIG. 3, and FIG. 6B is an enlarged view of part “A” shown in FIG. 6A.

Referring to FIG. 6A, waveform diagrams of signals a, b, c, and d respectively detected from the first nodes N1 of four consecutive stages are shown. For example, at the first node N1 of the first and third stages generating the gate signal based on the first clock signal CK, the first signal a and the third signal c are detected. In the first node N1 of the second and fourth stages generating the gate signal based on the second clock signal CKB whose phase is inverted from the first clock signal CK, the second signal b and the fourth signal are generated. (d) was detected.

Accordingly, referring to FIG. 6B, noises a 'and c' included in the first and third signals a and c generated based on the first clock signal CK and the second clock signal are illustrated. It was also confirmed that the noises b 'and d' included in the second and fourth signals b and d generated based on CKB also generated 180 degrees of phase difference.

Therefore, through the noise removing circuit according to the embodiment of the present invention, the noise a 'of the first signal having a phase difference of 180 degrees and the noise b' of the second signal could be removed by interference and cancellation. The noise c 'of the third signal and the noise d' of the fourth signal may also be removed by interference and cancellation.

As a result, the reliability of the gate signal output based on the signal of the first node may be improved by removing noise included in the signal of each stage first node.

As described above, according to the present invention, the pull-up portion control stage of the odd-numbered stage and the pull-up portion control stage of the even-numbered stage are electrically connected in the period where the first node N1 of the odd- In the section in which the first node N1 maintains the low level, the controller may electrically short the noise to remove the noise of the control unit of the pull-up unit. By removing the noise generated at the control unit of the pull-up unit of the stage, the display quality may be improved by removing the noise of the gate signal output from the stage.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims. You will understand.

Claims (14)

delete delete delete delete An m-th stage including a pull-up unit configured to pull up the first clock signal to a high level of the m-th gate signal and output the m-th gate signal; A pull-up part connected to the m-th stage and configured to pull up a second clock signal whose phase is inverted from the first clock signal to a high level of an m + 1 th gate signal, and output an m + 1 th gate signal; M + 1 th stage; And Electrically controlling the control terminal of the pull-up unit of the m-th stage and the control terminal of the pull-up unit of the m + 1th stage in response to the m-th gate signal and the m + 1-th gate signal, and the first and second clock signals And a noise canceling circuit electrically connecting the control end of the pull-up part of the m-th stage and the control end of the pull-up part of the m + 1th stage in response to the pull-up part.  The noise canceling circuit of claim 5, wherein A first switching unit driving in response to the first clock signal or the second clock signal; A second switching unit driving in response to the m th gate signal or the m + 1 th gate signal; And Th stage and a control terminal of the pull-up unit of the (m + 1) -th stage in response to an output signal of the first and second switching units. The method of claim 6, wherein the first switching unit A first switching element configured to output a high level of the first clock signal in response to a high level of the first clock signal; And And a second switching element configured to output the high level of the second clock signal in response to the high level of the second clock signal. The method of claim 7, wherein the second switching unit A third switching element configured to output a high level of the first clock signal at a level of an off voltage in response to a high level of the m-th gate signal; And And a fourth switching device configured to output the high level of the second clock signal to the level of the off voltage in response to the high level of the m + 1 th gate signal. The method of claim 8, wherein the third switching unit When the third or fourth switching device is turned on, the control stage of the pull-up unit of the m-th stage and the control stage of the pull-up unit of the m + 1th stage are electrically opened in response to the level of the off voltage. When the third and fourth switching devices are turned off, the control stage of the pull-up part of the m-th stage and the m + 1 in response to the high level of the first or second clock signal provided from the first or second switching device. And a fifth switching element for electrically shorting the control terminal of the pull-up part of the second stage. A display panel including a display area in which gate lines and source lines intersecting each other are formed to display an image, and a peripheral area surrounding the display area; A source driving circuit which outputs data signals to the source wirings; And A gate driving circuit integrated in the peripheral region and including a plurality of stages for outputting gate signals to the gate lines; The gate driving circuit An m-th stage including a pull-up unit configured to pull up the first clock signal to a high level of the m-th gate signal and output the m-th gate signal; A pull-up part connected to the m-th stage and configured to pull up a second clock signal whose phase is inverted from the first clock signal to a high level of an m + 1 th gate signal, and output an m + 1 th gate signal; M + 1 th stage; And Electrically controlling the control terminal of the pull-up unit of the m-th stage and the control terminal of the pull-up unit of the m + 1th stage in response to the m-th gate signal and the m + 1-th gate signal, and the first and second clock signals And a noise removing circuit electrically connecting the control terminal of the pull-up unit of the m-th stage and the control terminal of the pull-up unit of the m + 1th stage in response to the plurality of signals.  The noise canceling circuit of claim 10, wherein A first switching unit driving in response to a high level of the first clock signal or the second clock signal; A second switching unit driving in response to the high level of the m-th gate signal or the m + 1-th gate signal; And And a third switching unit configured to switch a control terminal of the pull-up unit of the m-th stage and a control terminal of the pull-up unit of the m + 1th stage in response to output signals of the first and second switching units. The method of claim 11, wherein the first switching unit A first switching element configured to output a high level of the first clock signal in response to a high level of the first clock signal; And And a second switching element configured to output the high level of the second clock signal in response to the high level of the second clock signal. The method of claim 12, wherein the second switching unit A third switching element configured to output a high level of the first clock signal at a level of an off voltage in response to a high level of the m-th gate signal; And And a fourth switching device configured to output the high level of the second clock signal to the level of the off voltage in response to the high level of the m + 1 th gate signal. The method of claim 13, wherein the third switching unit When the third or fourth switching device is turned on, the control stage of the pull-up unit of the m-th stage and the control stage of the pull-up unit of the m + 1th stage are electrically opened in response to the level of the off voltage. When the third and fourth switching devices are turned off, the control stage of the pull-up part of the m-th stage and the m + 1 in response to the high level of the first or second clock signal provided from the first or second switching device. And a fifth switching element electrically shorting the control terminal of the pull-up part of the second stage.

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