CN106024065B - Shifting register, grid driving circuit, array substrate and display device - Google Patents
Shifting register, grid driving circuit, array substrate and display device Download PDFInfo
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- CN106024065B CN106024065B CN201610333143.3A CN201610333143A CN106024065B CN 106024065 B CN106024065 B CN 106024065B CN 201610333143 A CN201610333143 A CN 201610333143A CN 106024065 B CN106024065 B CN 106024065B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Shift Register Type Memory (AREA)
Abstract
The embodiment of the application provides a shift register, a gate driving circuit comprising the shift register, an array substrate comprising the gate driving circuit and a display panel comprising the array substrate, wherein the shift register comprises: the first switch, the second switch, the third switch, the fourth switch, the seventh switch, the first node, the second node and the output signal end, wherein the fourth switch is controlled by the first control signal, and is used for transmitting the second level signal to the second node, and is no longer controlled by the first node, thereby avoiding the mutual control and influence of the first node and the second node, causing poor stability of the shift register, and leading to the problem that the circuit can not work normally, and when the stability of the shift register is improved, the display effect of the display panel is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a shift register, a gate drive circuit, an array substrate and a display device.
Background
with the continuous development of display technology, various display applications, such as liquid crystal displays, organic light emitting displays, etc., are becoming mainstream products in the display industry at present. In a display, generally, a driving circuit provides a driving signal, such as a gate driving signal, to a pixel unit in the display, and the gate driving circuit located on a side of the display provides the driving signal to a gate of the pixel unit of the display, so as to drive the corresponding pixel unit to assume a desired display state.
The driving circuit in the display generally comprises shift registers, each shift register is cascaded with each other to transmit pulse signals to the progressive pixel units step by step, the shift registers generally comprise a plurality of switch units which are electrically connected with each other, in the process of actual work, phenomena such as distortion and disorder of output waveforms generally occur due to poor stability of the shift registers, circuit oscillation caused by mutual interference among different nodes in the shift registers is one of main reasons of poor stability of the shift registers, and therefore, how to improve the stability of the shift registers is an important problem to be solved urgently for improving the display quality of the display.
Disclosure of Invention
In view of the above, the present invention provides a shift register, a gate driving circuit, an array substrate and a display device, so as to improve the stability of the shift register, the gate driving circuit including the shift register, the array substrate and the display device.
In order to achieve the purpose, the invention provides the following technical scheme:
A shift register includes first to seventh switches, first and second nodes, and an output signal terminal;
The first switch is controlled by a first input signal and is used for transmitting a first level signal to the first node;
the second switch is controlled by a second input signal and is used for transmitting a second level signal to the first node;
the third switch is controlled by a level of the second node for transmitting the second level signal to the first node;
the fourth switch is controlled by a first control signal and is used for transmitting the second level signal to the second node;
The fifth switch is controlled by the level of the first node and is used for transmitting a first clock signal to the output signal end;
the sixth switch is controlled by the level of the second node and is used for transmitting the second level signal to the output signal end;
The seventh switch is controlled by a second clock signal and is used for transmitting the second level signal to the output signal end;
The shift register further includes a first control signal terminal, and the first control signal terminal provides the first control signal to the control terminal of the fourth switch.
a grid driving circuit comprises n stages of shift registers, wherein the n stages of shift registers comprise m shift register groups, the shift registers in each shift register group are electrically connected in a cascade mode, the shift registers are the shift registers, m and n are positive integers, m is larger than 1, and n is larger than 1.
An array substrate comprises a plurality of gate lines, a plurality of data lines intersecting with the gate lines in an insulating mode, pixel arrays arranged in an array mode and formed by enclosing the gate lines and the data lines, and the gate driving circuit arranged on at least one side of the array substrate, wherein the output end of each shift register is connected with one gate line.
A display device comprises the array substrate.
compared with the prior art, the technical scheme provided by the invention has the following advantages:
The shift register provided by the invention comprises: the fourth switch is controlled by a first control signal provided by the first control signal end and is used for transmitting the second level signal to the second node, and the first control signal end is not influenced by the voltage of the first node, so that the second node is not controlled by the first node any more, the mutual control and influence of the first node and the second node are avoided, the distortion or disorder phenomenon of the output waveform of the shift register is avoided, and the stability of the shift register is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating a shift register according to another embodiment of the present invention;
Fig. 3 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention;
FIG. 4 is a schematic diagram of an i-th shift register of the gate driving circuit in FIG. 3;
fig. 5 is a schematic structural diagram of an array substrate according to an embodiment of the invention.
Detailed Description
the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background section, the stability of the shift register in the related art is poor, so that the stability of the gate driving circuit and the display device including the shift register is also relatively poor.
generally, a shift register includes important nodes for changing a waveform output by the shift register, for example, when the output waveform is a high level pulse, the shift register includes a pull-up node for making the output waveform present a high level and a pull-down node for making the output waveform return to a low level, when the pull-up node and the pull-down node are controlled and interfered with each other, a circuit oscillation problem is easily generated, and the waveform output by the shift register is easily distorted or disordered, so that the stability of the shift register is poor, and the display effect of the display is affected.
An embodiment of the present invention provides a shift register, as shown in fig. 1, where fig. 1 is a schematic structural diagram of a shift register provided in an embodiment of the present invention, where the shift register includes: first to seventh switches T0-T6, first and second nodes PU and PD, and an output signal terminal Gn; the first switch T0 is controlled by a first input signal SET for transmitting a first level signal VGH to the first node PU; the second switch T1 is controlled by the second input signal Gn +1 for transmitting the second level signal VGL to the first node PU; the third switch T2 is controlled by the level of the second node PD for transmitting the second level signal VGL to the first node PU; the fourth switch T3 is controlled by the first control signal for transmitting the second level signal VGL to the second node PD; the fifth switch T4 is controlled by the level of the first node PU for transmitting the first clock signal CKB to the output signal terminal Gn; the sixth switch T5 is controlled by the level of the second node PD for transmitting the second level signal VGL to the output signal terminal Gn; the seventh switch T6 is controlled by the second clock signal CK for transmitting the second level signal VGL to the output signal terminal Gn; the shift register further includes a first control signal terminal 10, and the first control signal terminal 10 provides a first control signal to the control terminal of the fourth switch T3.
in the shift register provided in the embodiment of the present invention, the fourth switch T3 is controlled by the first control signal provided by the first control signal terminal, and is used for transmitting the second level signal to the second node, and the first control signal terminal is not affected by the voltage of the first node, so that the second node is no longer controlled by the first node, thereby avoiding the problem that the second node cannot normally operate when the first node has a problem, and improving the stability of the shift register.
in an embodiment of the present invention, as shown in fig. 2, fig. 2 is a schematic structural diagram of a shift register according to another embodiment of the present invention, where the shift register further includes a control signal source 20, the control signal source 20 is electrically connected to the first control signal terminal 10, provides the first control signal to the first control signal terminal 10, transmits the first control signal to the fourth switch T3 through the first control signal terminal 10, and controls on and off of the fourth switch T3. However, the present invention is not limited to this, and in other embodiments of the present invention, when the shift register is applied to the gate driving circuit in a cascade manner, the first control signal terminal may also be electrically connected to the output terminals of other shift registers, and controlled by the output signals of other shift registers, so as to simplify the circuit structures of the shift register and the gate driving circuit including the shift register, and the specific electrical connection relationship thereof is described later, and is not described herein again.
In an optional embodiment of the present invention, the first level signal VGH is a high level signal, the second level signal VGL is a low level signal, the first node PU is a pull-up node, the second node PD is a pull-down node, and the second clock signal CK is an inverted signal of the first clock signal CKB. However, the present invention is not limited thereto, as the case may be.
In one embodiment of the present invention, the shift register further includes: the circuit comprises a first input signal end, a second input signal end, a first clock signal end, a second clock signal end, a first level signal end and a second level signal end; the first input signal end is configured to receive a first input signal SET, the second input signal end is configured to receive a second input signal Gn +1, the first clock signal end is configured to receive a first clock signal CKB, the second clock signal end is configured to receive a second clock signal CK, the first level signal end is configured to receive a first level signal VGH, the second level signal end is configured to receive a second level signal VGL, a control end of the first switch T0 is connected to the first input signal end, a first end of the first switch T0 is connected to the first level signal end, and a second end of the first switch T0 is connected to the first node PU; a control terminal of the second switch T1 is connected to the second input signal terminal, a first terminal of the second switch T1 is connected to the second level signal terminal, and a second terminal of the second switch T1 is connected to the first node PU; a control terminal of the third switch T2 is connected to the second node PD, a first terminal of the third switch T2 is connected to the second level signal terminal, and a second terminal of the third switch T2 is connected to the first node PU; a control terminal of the fourth switch T3 is connected to the first control signal terminal, a first terminal of the fourth switch T3 is connected to the second level signal terminal, and a second terminal of the fourth switch T3 is connected to the second node PD; a control terminal of the fifth switch T4 is connected to the first node PU, a first terminal of the fifth switch T4 is connected to the first clock signal input terminal, and a second terminal of the fifth switch T4 is connected to the output signal terminal; a control terminal of the sixth switch T5 is connected to the second node PD, a first terminal of the sixth switch T5 is connected to the second level signal terminal, and a second terminal of the sixth switch T5 is connected to the output signal terminal; the control terminal of the seventh switch T6 is connected to the second clock signal terminal, the first terminal of the seventh switch T6 is connected to the second level signal terminal, and the second terminal of the seventh switch T6 is connected to the output signal terminal.
It should be noted that, in the above embodiment, the signal source of the first input signal terminal may be a trigger signal STP output by a trigger signal source, or may also be an output signal of a previous stage or a next stage shift register located in the same group as the shift register, and similarly, the signal source of the second input signal terminal may also be an output signal of a next stage or a previous stage shift register located in the same group as the shift register.
In one embodiment of the present invention, the shift register further includes: a first capacitor C1 and a second capacitor C2, wherein a first terminal of the first capacitor C1 is connected to the first clock signal terminal, and a second terminal of the first capacitor C1 is connected to the second node PD; a first terminal of the second capacitor C2 is connected to the first node PU, and a second terminal of the second capacitor C2 is connected to the output signal terminal. In the present embodiment, the first capacitor C1 is configured to couple the first clock signal to the second node PD when the fourth switch T3 is turned off, so that the second node PD varies with the variation of the first clock signal; the second capacitor C2 is used to couple the signal output from the output signal terminal to the first node PU when the fifth switch T4 is turned off, so that the signal of the first node PU varies with the variation of the signal output from the output signal terminal.
In one embodiment of the present invention, the shift register further includes: an eighth switch T8 and a ninth switch T7, wherein the eighth switch T8 is controlled by a Reset signal Reset for transmitting the second level signal VGL to the first node PU; the ninth switch T7 is controlled by a Reset signal Reset for transmitting the second level signal VGL to the output signal terminal.
optionally, in an embodiment of the present invention, the shift register further includes: a Reset signal terminal for receiving a Reset signal Reset; a control terminal of the eighth switch T8 is connected to the reset signal terminal, a first terminal of the eighth switch T8 is connected to the second level signal terminal, and a second terminal of the eighth switch T8 is connected to the first node PU; the control terminal of the ninth switch T7 is connected to the reset signal terminal, the first terminal of the ninth switch T7 is connected to the second level signal terminal, and the second terminal of the ninth switch T7 is connected to the output signal terminal. It should be noted that, in the embodiment of the present invention, the input signal of the reset signal terminal may be derived from a reset signal source, or may be derived from a signal output by an output signal terminal of a previous stage or a next stage shift register located in the same group as the shift register.
in an alternative embodiment of the present invention, the first to ninth switches T0 to T7 are PMOS transistors or NMOS transistors, the control terminals of the first to ninth switches T0 to T8 are gates of the transistors, and the first and second terminals are sources and drains of the transistors, respectively.
as can be seen from the above, in the shift register provided in the embodiment of the present invention, the fourth switch is controlled by the first control signal provided by the first control signal terminal, and is used for transmitting the second level signal to the second node, and the first control signal terminal is not affected by the voltage of the first node, so that the second node is no longer controlled by the first node, thereby avoiding the problem that the second node cannot normally operate when the first node has a problem, and improving the stability of the shift register.
Correspondingly, an embodiment of the present invention further provides a gate driving circuit, as shown in fig. 3, fig. 3 is a schematic circuit structure diagram of the gate driving circuit according to an embodiment of the present invention, where the gate driving circuit includes: the shift register comprises n stages of shift registers, each shift register in the n stages of shift registers comprises m shift register groups, the shift registers in each shift register group are electrically connected in a cascade mode, the shift registers are the shift registers provided by any one of the embodiments, m and n are positive integers, m is greater than 1, and n is greater than 1. Specifically, in the embodiment of the present invention, when the gate driving circuit scans in the forward direction, the first input signal control end of the first stage shift register in the same shift register group is electrically connected to the external trigger signal STP, and the signal output ends of the other shift registers are electrically connected to the first input signal end of the next stage shift register; when the grid driving circuit scans reversely, the first input signal end of the last stage of shift register in the same shift register group is electrically connected with the external trigger signal STP, and the signal output ends of the other shift registers are electrically connected with the first input signal end of the shift register of the previous stage.
In one embodiment of the present invention, the first control signal terminal L3 in each shift register is electrically connected to a control signal source, and the control signal source provides a first control signal; in another embodiment of the present invention, the first control signal terminals L3 of all the shift registers in the n-stage shift registers or the shift registers in the same shift register group are electrically connected to the same control signal source, and the control signal source provides the corresponding first control signal terminals with the first control signals, respectively, so as to simplify the structure of the gate driving circuit; in another embodiment of the present invention, the gate driving circuit is not provided with a control signal source, the first control signal terminal of each shift register is electrically connected to the other shift registers, and the other shift registers provide the first control signal.
in the gate driving circuit provided in the embodiment of the present invention, the fourth switch of each shift register is controlled by the first control signal provided by the first control signal terminal, and is used for transmitting the second level signal to the second node, and the first control signal terminal is not affected by the voltage of the first node, so that the second node is no longer controlled by the first node, thereby avoiding the problem that the second node cannot normally operate when the first node has a problem, improving the stability of the shift register, and further improving the stability of the gate driving circuit. The gate driving circuit provided in the embodiment of the present invention is described below by taking an example that when the gate driving circuit is not provided with a control signal source, the first control signal terminal in each shift register is electrically connected to other shift registers, and the other shift registers provide the first control signal.
in an embodiment of the present invention, when the scanning mode of the gate driving circuit is forward scanning, as shown in fig. 3, the first control signal terminal of the i-th shift register receives the output signal of the i-1 th shift register, and the i-th shift register and the i-1 th shift register belong to two shift register groups, respectively, in addition, referring to fig. 4, fig. 4 is a schematic structural diagram of the i-th shift register of the gate driving circuit in fig. 3, wherein the first control signal terminal of the i-th shift register receives the output signal Gn-1 of the i-1 th shift register for controlling the pull-down node PD; in another embodiment of the present invention, when the scanning mode of the gate driving circuit is reverse scanning, the first control signal terminal of the i-th shift register receives the output signal of the i + 1-th shift register, and the i-th shift register and the i + 1-th shift register belong to two shift register groups respectively. It should be noted that, although the drawings in the embodiments of the present invention illustrate that the n-stage shift register includes 2 shift register groups, the present invention is not limited to this, and when 3, 4 or more shift register groups are provided, the electrical connection relationship of each shift register is also applicable.
In another embodiment of the present invention, when the n-stage shift register includes 3 shift register groups, and when the scanning mode of the gate driving circuit is forward scanning, the first control signal terminal of the ith-stage shift register receives the output signal of the (i-1) th or (i-2) th-stage shift register, and the ith-stage shift register, the (i-1) th-stage shift register, and the (i-2) th-stage shift register belong to different shift register groups, respectively; in another embodiment of the present invention, when the scanning mode of the gate driving circuit is reverse scanning, the first control signal terminal of the ith shift register receives an output signal of the (i + 1) th or (i + 2) th shift register, and the ith shift register, the (i + 1) th shift register, and the (i + 2) th shift register belong to different shift register groups.
similarly, when the n-stage shift register includes m shift register groups and the scanning mode of the gate driving circuit is forward scanning, the first control signal terminal of the ith-stage shift register receives the output signal of the ith-p-stage shift register, and the ith-p-stage shift register belong to different shift register groups respectively; in another embodiment of the present invention, when the scanning mode of the gate driving circuit is reverse scanning, the first control signal terminal of the i-th stage shift register receives an output signal of the i + p-th stage shift register, and the i-th stage shift register and the i + p-th stage shift register belong to different shift register groups respectively. Where p can be any positive integer of [1, m), inclusive of 1, but exclusive of m.
It should be noted that, in any of the above embodiments, there is a signal delay of a preset time between the trigger signals of the shift registers in different groups and in the same row, where the preset time is greater than zero and less than the width of one pulse.
In one embodiment of the present invention, the gate driving circuit further includes: the shift register comprises an input signal line, a clock signal line and a reset signal line, wherein the input signal line provides a trigger signal STP for a first-stage shift register of each shift register group, first input signals of the rest shift registers of all the shift register groups are output signals of the previous-stage shift register, and/or the input signal line provides the trigger signal STP for a last-stage shift register of each shift register group, and second input signals of the rest shift registers of all the shift register groups are output signals of the next-stage shift register; each clock signal line provides a first clock signal CKB and a second clock signal CK to the shift registers in each shift register group; the Reset signal line supplies a Reset signal Reset to the shift registers in each shift register group, so that the shift registers are in a Reset state. Optionally, in an embodiment of the present invention, when each input signal line provides a first input signal to the first stage shift register of each shift register group, and the first input signals of the remaining shift registers of each shift register group are output signals of the previous stage shift register, a signal of the reset signal line corresponding to each shift register comes from a signal output by the output signal terminal of the next stage shift register located in the same shift register group; when the input signal lines provide the second input signal to the last stage shift register of each shift register group, and the second input signals of the remaining shift registers in each shift register group are the output signals of the next stage shift register, the signals of the reset signal lines corresponding to the shift registers are derived from the signals output by the output signal terminals of the previous stage shift register in the same shift register group, so as to simplify the circuit structure of the gate driving circuit.
In addition, the embodiment of the invention also provides an array substrate and a display panel comprising the array substrate. As shown in fig. 5, fig. 5 is a schematic structural diagram of an array substrate according to an embodiment of the present invention, where the array substrate includes: the shift register comprises a plurality of Gate lines Gate, a plurality of data lines S intersecting the Gate lines Gate in an insulating manner, a pixel array 100 formed by enclosing the Gate lines Gate and the data lines S and arranged in an array, and a Gate driving circuit 200 arranged on at least one side of the array substrate, wherein an output end of each shift register (not shown in the figure) is connected with one Gate line, the number of the Gate lines shown in the figure is only an example, and the specific number depends on the specific situation, and is not described herein again.
in summary, the shift register, the gate driving circuit including the shift register, the array substrate including the gate driving circuit, and the display panel including the array substrate provided in the embodiments of the present invention include: the shift register comprises a first switch, a second switch, a third switch, a fourth switch, a seventh switch, a first node, a second node and an output signal end, wherein the fourth switch is controlled by a first control signal and is used for transmitting a second level signal to the second node and is not controlled by the first node any more, so that the problem that the second node cannot normally work when the first node goes wrong is avoided, the stability of the shift register is improved, and further, the stability of a grid driving circuit comprising the shift register, an array substrate comprising the grid driving circuit and a display device comprising the array substrate is improved.
the embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
the previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (13)
1. A shift register is applied to a gate driving circuit, the gate driving circuit comprises n stages of shift registers, each n stage of shift register comprises m shift register groups, the shift registers in each shift register group are electrically connected in a cascade mode, each shift register comprises a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a first node, a second node and an output signal end, m and n are positive integers, m is greater than 1, and n is greater than 1;
the first switch is controlled by a first input signal and is used for transmitting a first level signal to the first node;
The second switch is controlled by a second input signal and is used for transmitting a second level signal to the first node;
The third switch is controlled by a level of the second node for transmitting the second level signal to the first node;
the fourth switch is controlled by a first control signal and is used for transmitting the second level signal to the second node;
the fifth switch is controlled by the level of the first node and is used for transmitting a first clock signal to the output signal end;
The sixth switch is controlled by the level of the second node and is used for transmitting the second level signal to the output signal end;
The seventh switch is controlled by a second clock signal and is used for transmitting the second level signal to the output signal end;
The shift register further includes a first control signal terminal and a first input signal terminal, the first control signal terminal provides the first control signal to the control terminal of the fourth switch, the first input signal terminal provides the first input signal to the control terminal of the first switch, and a time of the first control signal input by the first control signal terminal is asynchronous with a time of the first input signal input by the first input signal terminal.
2. the shift register according to claim 1, wherein the first level signal is a high level signal, the second level signal is a low level signal, the first node is a pull-up node, the second node is a pull-down node, and the second clock signal is an inverted signal of the first clock signal.
3. the shift register according to claim 1, further comprising a second input signal terminal, a first clock signal terminal, a second clock signal terminal, a first level signal terminal, and a second level signal terminal;
A control end of the first switch is connected with the first input signal end, a first end of the first switch is connected with the first level signal end, and a second end of the first switch is connected with the first node;
The control end of the second switch is connected with the second input signal end, the first end of the second switch is connected with the second level signal end, and the second end of the second switch is connected with the first node;
A control end of the third switch is connected with the second node, a first end of the third switch is connected with the second level signal end, and a second end of the third switch is connected with the first node;
A control end of the fourth switch is connected with the first control signal end, a first end of the fourth switch is connected with the second level signal end, and a second end of the fourth switch is connected with the second node;
A control end of the fifth switch is connected with the first node, a first end of the fifth switch is connected with the first clock signal end, and a second end of the fifth switch is connected with the output signal end;
a control end of the sixth switch is connected with the second node, a first end of the sixth switch is connected with the second level signal end, and a second end of the sixth switch is connected with the output signal end;
The control end of the seventh switch is connected with the second clock signal end, the first end of the seventh switch is connected with the second level signal end, and the second end of the seventh switch is connected with the output signal end.
4. The shift register according to claim 3, further comprising a first capacitor and a second capacitor;
a first end of the first capacitor is connected with the first clock signal end, and a second end of the first capacitor is connected with the second node;
And the first end of the second capacitor is connected with the first node, and the second end of the second capacitor is connected with the output signal end.
5. The shift register according to any one of claims 1 to 4, further comprising an eighth switch and a ninth switch;
the eighth switch is controlled by a reset signal for transmitting the second level signal to the first node;
The ninth switch is controlled by the reset signal and is used for transmitting the second level signal to the output signal end.
6. The shift register according to claim 5, further comprising a reset signal terminal;
a control end of the eighth switch is connected with the reset signal end, a first end of the eighth switch is connected with the second level signal end, and a second end of the eighth switch is connected with the first node;
the control end of the ninth switch is connected with the reset signal end, the first end of the ninth switch is connected with the second level signal end, and the second end of the ninth switch is connected with the output signal end.
7. The shift register according to claim 6, wherein the first to ninth switches are PMOS transistors or NMOS transistors, the control terminals of the first to ninth switches are gates of the transistors, and the first and second terminals are sources and drains of the transistors, respectively.
8. A gate driving circuit, comprising n stages of shift registers, wherein the n stages of shift registers comprise m shift register groups, the shift registers in each shift register group are electrically connected in a cascade manner, the shift register is as claimed in any one of claims 1 to 7, m and n are positive integers, and m > 1 and n > 1.
9. the gate driving circuit according to claim 8, wherein the first control signal terminal of an ith stage shift register receives an output signal of an ith-p stage shift register, and the ith stage shift register and the ith-p stage shift register belong to different shift register groups respectively;
or, the first control signal end of the ith stage shift register receives an output signal of an i + p stage shift register, and the ith stage shift register and the i + p stage shift register belong to different shift register groups respectively; wherein p is any positive integer of [1, m), inclusive of 1, and exclusive of m.
10. a gate driving circuit as claimed in claim 9, wherein the first control signal terminal of the i-th stage shift register receives an output signal of an i-1 th stage shift register, and the i-th stage shift register and the i-1 th stage shift register belong to two different shift register groups respectively;
Or, the first control signal end of the ith stage shift register receives an output signal of the (i + 1) th stage shift register, and the ith stage shift register and the (i + 1) th stage shift register belong to two different shift register groups respectively.
11. The gate drive circuit of claim 8, further comprising an input signal line, a clock signal line, and a reset signal line, wherein,
Each input signal line provides a first input signal to the first stage shift register of each shift register group, the first input signal of each shift register of the rest stages in each shift register group is the output signal of the previous stage shift register, and/or each input signal line provides a second input signal to the last stage shift register of each shift register group, and the second input signal of each shift register of the rest stages in each shift register group is the output signal of the next stage shift register;
each clock signal line provides a clock signal for the shift register in each shift register group;
The reset signal line provides a reset signal for the shift registers in each shift register group, so that the shift registers are in a reset state.
12. an array substrate, comprising a plurality of gate lines, a plurality of data lines intersecting the gate lines in an insulated manner, a pixel array formed by enclosing the gate lines and the data lines and arranged in an array manner, and a gate driving circuit according to any one of claims 8 to 11 arranged on at least one side of the array substrate, wherein the output end of each shift register is connected with one gate line.
13. a display device comprising the array substrate according to claim 12.
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| CN107403609B (en) * | 2017-09-04 | 2020-01-31 | 上海天马微电子有限公司 | Shift register and control method thereof, grid drive circuit and display device |
| WO2020097816A1 (en) * | 2018-11-14 | 2020-05-22 | 京东方科技集团股份有限公司 | Shift register unit, drive method, gate drive circuit, and display device |
| CN111599301B (en) * | 2020-06-30 | 2023-03-21 | 厦门天马微电子有限公司 | Shift register and display device |
| CN112951146B (en) * | 2021-04-25 | 2024-03-15 | 厦门天马微电子有限公司 | Shift register, driving method, scanning driving circuit, display panel and device |
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