CN105405383A - Shift registering unit, shift register, driving method of shift register and display device - Google Patents

Shift registering unit, shift register, driving method of shift register and display device Download PDF

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Publication number
CN105405383A
CN105405383A CN201510993310.2A CN201510993310A CN105405383A CN 105405383 A CN105405383 A CN 105405383A CN 201510993310 A CN201510993310 A CN 201510993310A CN 105405383 A CN105405383 A CN 105405383A
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China
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signal
transistor
node
output terminal
input
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CN201510993310.2A
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Chinese (zh)
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CN105405383B (en
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李玥
邹文晖
钱栋
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上海天马有机发光显示技术有限公司
天马微电子股份有限公司
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Priority to CN201510993310.2A priority Critical patent/CN105405383B/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Abstract

The invention discloses a shift registering unit, a shift register, a driving method of the shift register and a display device. The shift registering unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, a second capacitor, a third capacitor, an input signal end, a first clock signal end, a second clock signal end, a first voltage signal end, a second voltage signal end and a first output end. According to the invention, shift output of grid signals can be achieved via quite few transistors, power consumption of the shift register is reduced; a circuit failure caused by potential competence of nodes and threshold value drifting of the transistors can be avoided; and stability of circuit operation is enhanced.

Description

Shifting deposit unit, shift register and driving method thereof, display device

Technical field

The application relates to display technique field, is specifically related to shifting deposit unit, shift register and driving method thereof, display device.

Background technology

In a kind of conventional design of display panel, display panel can be provided with pel array, many grid lines, insulate with many grid lines crossing data line.In addition, display panel can also be provided with gate driver circuit.After the individual pulse signal of input is shifted by gate driver circuit step by step, each grid line of conducting, realizes the line scanning of pel array on display panel successively.

Fig. 1 shows a kind of structural representation of a driver element of existing gate driver circuit, and described driver element is for driving a grid line.As shown in Figure 1, driver element 100 comprises shifting deposit unit 11 and phase inverter 12.Wherein shifting deposit unit 11 will be for exporting after the individual pulse signal displacement of input, and phase inverter 12 exports for after the signal inversion that exported by shifting deposit unit 11.Driver element 100 shown in Fig. 1 comprises MA1 to MA12 totally 12 transistors.In signal shift phase, NA2 node is electronegative potential, by MA4 conducting, the low level signal that CKA2 inputs is passed to the output terminal next of shifting deposit unit 11.At this moment, output terminal next control MA2 conducting, is passed to NA1 node by high level signal VGH, thus is closed by MA5.Due to transistor MA4 the second pole output low level signal after transistor MA5 just close, second pole of transistor MA4 to output terminal next transmit low level signal and transistor MA5 close between may life period poor.Transistor MA4 and transistor MA5 conducting simultaneously within this mistiming, makes the problem that there is node potential competition in circuit, causes the jitter that output terminal next exports.

Fig. 2 shows the structural representation of a driver element of another kind of existing gate driver circuit.In the circuit 200 shown in Fig. 2, adopt the start signal of high level, when the level signal of CKB2 input changes low level signal into by high level signal, due to the coupling of electric capacity CB1, NB1 node potential is reduced, transistor MB2 conducting, MB5 ends, so high level signal VGH cannot be passed to NB1 node.NB1 node keeps electronegative potential, makes to occur between second pole of transistor MB9 and MB10 node potential competition, cannot by the signal VGH normal delivery of high level to output terminal E1, and circuit can not the shift signal of normal input high level.

Summary of the invention

All there is the problem of node potential competition in above two kinds of existing designs, and number of transistors is more, the power consumption of driving circuit is larger.In view of this, expect to provide a kind of shift register reducing number of transistors.Further, also expect to provide a kind of shift register node potential can avoided to compete, ensure circuit stability.In order to solve above-mentioned one or more problem, this application provides shifting deposit unit, shift register and driving method thereof, display device.

First aspect, this application provides a kind of shifting deposit unit, comprise the first transistor, transistor seconds, third transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor, the first electric capacity, the second electric capacity, the 3rd electric capacity, input signal end, the first clock signal terminal, second clock signal end, the first voltage signal end, the second voltage signal end and the first output terminal.Wherein, the signal that described the first transistor is inputted by described input signal end controls, for by described first voltage signal end input signal transmission to first node; The signal that described transistor seconds is inputted by described first clock signal terminal controls, for by the signal transmission of described input signal end input to Section Point; The signal that described third transistor is exported by described first output terminal controls, for by the signal transmission of described second clock signal end input to the 3rd node; Described 4th transistor is controlled by the electric potential signal of described first node, for by described first clock signal terminal input signal or described second voltage signal end input signal transmission to the 4th node; Described 5th transistor is controlled by the electric potential signal of described Section Point, for signal transmission extremely described 4th node by described first voltage signal end input; Described 6th transistor is controlled by the electric potential signal of described 4th node, for signal transmission extremely described first output terminal by described first voltage signal end input; Described 7th transistor is controlled by the electric potential signal of described Section Point, for signal transmission extremely described first output terminal by described second voltage signal end input; One end of described first electric capacity is for inputting the signal of described first clock signal terminal input, and the other end of described first electric capacity is for inputting the electric potential signal of described first node; One end of described second electric capacity is for inputting the electric potential signal of described 3rd node, and the other end of described second electric capacity is for inputting the electric potential signal of described Section Point; One end of described 3rd electric capacity is for inputting the signal of described first voltage signal end, and the other end of described 3rd electric capacity is for inputting the electric potential signal of described 4th node.

Second aspect, this application provides a kind of shift register, and comprise the shifting deposit unit of N number of cascade that the application's first aspect provides, wherein N is positive integer and N>1; The input signal end of first order shifting deposit unit is the shift signal input end of described shift register, and the second level is connected to the input signal end of every one-level shifting deposit unit in N level shifting deposit unit with the first output terminal of upper level shifting deposit unit.

The third aspect, this application provides the method for the shift register that a kind of the application's of driving second aspect provides, comprise: the first stage, the first level signal is provided to described first clock signal terminal and described input signal end, there is provided second electrical level signal to described second clock signal end, described first output terminal exports the second voltage signal; Subordinate phase, provides described second electrical level signal to described first clock signal terminal, and provide described first level signal to described input signal end and described second clock signal end, described first output terminal exports the first voltage signal; Phase III, provide described first level signal to described first clock signal terminal, provide described second electrical level signal to described input signal end and described second clock signal end, described first output terminal exports described first voltage signal; Fourth stage, provides described second electrical level signal to described first clock signal terminal and input signal end, provides described first level signal to described second clock signal end, and described first output terminal exports described second voltage signal; Five-stage, provides described first level signal to described first clock signal terminal, provides described second electrical level signal to described input signal end and described second clock signal end, and described first output terminal exports described second voltage signal.

Fourth aspect, this application provides the method for the another kind of shift register driving the application's second aspect to provide, comprise: in the first stage, described first level signal is provided to described first clock signal terminal, there is provided described second electrical level signal to described second clock signal, described input signal end, described first output terminal exports described first voltage signal; In subordinate phase, provide described second electrical level signal, provide described first level signal to described second clock signal end to described first clock signal terminal, described input signal end, described first output terminal exports described second voltage signal; In the phase III, provide described first level signal, provide described second electrical level signal to described second clock signal end to described first clock signal terminal, described input signal end, described first output terminal exports described second voltage signal; In fourth stage, provide described second electrical level signal to described first clock signal terminal, provide described first level signal to described second clock signal end, described input signal end, described first output terminal exports described first voltage signal; At five-stage, provide described first level signal, provide described second electrical level signal to described second clock signal end to described first clock signal terminal, input signal end, described first output terminal exports described first voltage signal.

5th aspect, this application provides a kind of display device, the shifting deposit unit that application the application first aspect provides and the driving method that the application's third aspect provides or the driving method that the application's fourth aspect provides.

The shifting deposit unit that the application provides, shift register and driving method thereof, display device, the displacement being realized signal by the transistor of lesser amt is exported, decrease the power consumption of shift register, can avoid, when the current potential reversion of shifting deposit unit output terminal, node potential competition occurs simultaneously and cause circuit malfunction, enhance the stability that circuit runs.

Accompanying drawing explanation

That is done with reference to the following drawings by reading is described in detail non-limiting example, and the other features, objects and advantages of the application will become more obvious:

Fig. 1 is a kind of structural representation of a driver element of existing gate driver circuit;

Fig. 2 is the structural representation of a driver element of another kind of existing gate driver circuit;

Fig. 3 is the electrical block diagram of a specific embodiment of the shifting deposit unit that the application provides;

Fig. 4 is the electrical block diagram of another specific embodiment of the shifting deposit unit that the application provides;

Fig. 5 is the electrical block diagram of another specific embodiment of the shifting deposit unit that the application provides;

Fig. 6 is the electrical block diagram of another specific embodiment of the shifting deposit unit that the application provides;

Fig. 7 is the structural representation of an embodiment of the shift register that the application provides;

Fig. 8 be embodiment illustrated in fig. 3 in a working timing figure of circuit structure;

Fig. 9 be embodiment illustrated in fig. 6 in a working timing figure of circuit structure;

Figure 10 be embodiment illustrated in fig. 3 in another working timing figure of circuit structure.

Embodiment

Below in conjunction with drawings and Examples, the application is described in further detail.Be understandable that, specific embodiment described herein is only for explaining related invention, but not the restriction to this invention.It also should be noted that, for convenience of description, in accompanying drawing, illustrate only the part relevant to Invention.

It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.Below with reference to the accompanying drawings and describe the application in detail in conjunction with the embodiments.

Please refer to Fig. 3, it illustrates the electrical block diagram of first specific embodiment of the shifting deposit unit that the application provides.As shown in Figure 3, shifting deposit unit 300 comprises the first transistor M1, transistor seconds M2, third transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7, the first electric capacity C1, the second electric capacity C2, the 3rd electric capacity C3, input signal end IN, the first clock signal terminal CK, second clock signal end XCK, the first voltage signal end VGH, the second voltage signal end VGL and the first output terminal EOUT.

In shifting deposit unit 300, the signal that the first transistor M1 is inputted by input signal end IN controls, for by first voltage signal end VGH input signal transmission to first node N1; The signal that transistor seconds M2 is inputted by described first clock signal terminal CK controls, for the signal transmission that described input signal end IN inputted to Section Point N2; The signal that third transistor M3 is exported by the first output terminal EOUT controls, for the signal transmission that inputted by second clock signal end XCK to the 3rd node N3; 4th transistor M4 is controlled by the electric potential signal of first node N1, for by first clock signal terminal CK input signal transmission to the 4th node N4; 5th transistor M5 is controlled by the electric potential signal of Section Point N2, for by first voltage signal end VGH input signal transmission to the 4th node N4; 6th transistor M6 is controlled by the electric potential signal of the 4th node N4, for the signal VGH of the first voltage signal end input is passed to described first output terminal EOUT; Described 7th transistor M7 is controlled by the electric potential signal of described Section Point N2, for the signal transmission extremely described first output terminal EOUT by described second voltage signal end VGL input; One end of first electric capacity C1 is for inputting the signal of the first clock signal terminal CK input, and the other end of the first electric capacity C1 is for inputting the electric potential signal of first node N1; One end of second electric capacity C2 is for inputting the electric potential signal of the 3rd node N3, and the other end of the second electric capacity C2 is for inputting the electric potential signal of Section Point N2; One end of 3rd electric capacity C3 is for inputting the signal of the first voltage signal end VGH, and the other end of the 3rd electric capacity C3 is for inputting the electric potential signal of the 4th node N4.

Particularly, the grid of the first transistor M1 is connected with input signal end IN, and first pole of the first transistor M1 is connected with the first voltage signal end VGH, and second pole of the first transistor M1 is connected with first node N1.The grid of transistor seconds M2 is connected with the first clock signal terminal CK, and first pole of transistor seconds M2 is connected with input signal end IN, and second pole of transistor seconds M2 is connected with Section Point N2.The grid of third transistor M3 is connected with the first output terminal EOUT of shifting deposit unit, and first pole of third transistor M3 is connected with second clock signal end XCK, and second pole of third transistor M3 is connected with the 3rd node N3.The grid of the 4th transistor M4 is connected with first node N1, and first pole of the 4th transistor M4 is connected with the first clock signal terminal CK, and second pole of the 4th transistor M4 is connected with the 4th node N4.The grid of the 5th transistor M5 is connected with Section Point N2, and first pole of the 5th transistor M5 is connected with the first voltage signal end VGH, and second pole of the 5th transistor M5 is connected with the 4th node N4; The grid of the 6th transistor M6 is connected with the 4th node N4, and first pole of the 6th transistor M6 is connected with the first voltage signal end VGH, and second pole of the 6th transistor M6 is connected with the first output terminal EOUT.The grid of the 7th transistor M7 is connected with Section Point N2, and first pole of the 7th transistor M7 is connected with the second voltage signal end VGL, and second pole of the 7th transistor M7 is connected with the first output terminal EOUT.One end of first electric capacity C1 is connected with the first clock signal terminal CK, and the other end of the first electric capacity C1 is connected with first node N1.One end of second electric capacity C2 is connected with the 3rd node N3, and the other end of the second electric capacity C2 is connected with Section Point N2.One end of 3rd electric capacity C3 is connected with the first voltage signal end VGH, and the other end of the 3rd electric capacity C3 is connected with the 4th node N4.

In the above-described embodiments, the electric potential signal of the 3rd node N3 is controlled by the first output terminal EOUT of shifting deposit unit, again by the coupling of the second electric capacity C2, the further current potential affecting Section Point N2, the threshold drift of the 7th transistor M7 can be compensated, ensure the output terminal of shift signal totally tansitive to shifting deposit unit.And, when the signal upset that the output terminal EOUT of shifting deposit unit exports,, therefore there is not the problem of node potential competition, enhance the stability of circuit in the impact of the signal that the current potential of Section Point and the 4th node does not export by the output terminal of shifting deposit unit.In addition, adopt the transistor of two clock signals and lesser amt can realize the displacement of signal, can driving power consumption be reduced, be conducive to the design of narrow frame.

With further reference to Fig. 4, it illustrates the electrical block diagram of another specific embodiment of the shifting deposit unit that the application provides.As can be seen from Figure 4, be only with difference technical characteristic embodiment illustrated in fig. 3, in shifting deposit unit 400, first pole of the 4th transistor M4 is connected with the second voltage signal end VGL.Because VGL signal is a kind of stable direct current signal, and the first clock signal terminal CK is a kind of pulse signal, its stability, not as direct current signal, can affect the stability of the 4th node N4 in the process of constantly upset.Therefore, in the shifting deposit unit 400 that provides of the present embodiment first pole of the 4th transistor M4 be connected with the second voltage signal end VGL can ensure the 4th node N4 stability by the impact of the first pole input signal of the 4th transistor M4.When the first output terminal EOUT exports high level signal, what the present embodiment can ensure that the 4th transistor M4 transmits is low level signal, thus the current potential of the 4th node N4 is remained on electronegative potential, the 6th transistor M6 is made to keep conducting state, first output terminal EOUT exports high level signal, the signal avoiding the first clock signal terminal CK to input impacts the current potential of the 4th node N4 when there is upset, enhances the stability of circuit.

With further reference to Fig. 5, it illustrates the electrical block diagram of another specific embodiment of the shifting deposit unit that the application provides.As shown in Figure 5, the shifting deposit unit 500 that the present embodiment provides can also comprise the 8th transistor M8 on the basis of the shifting deposit unit 300 shown in Fig. 3.8th transistor M8 is controlled by the electric potential signal of the 4th node N4, and the signal transmission inputted by the first voltage signal inputs VGH is to the 3rd node N3.Particularly, the grid of the 8th transistor M8 is connected with the 4th node N4, and first pole of the 8th transistor M8 is connected with the first voltage signal end VGH, and second pole of the 8th transistor M8 is connected with the 3rd node N3.

As can be seen from Figure 5, compared with embodiment illustrated in fig. 3, the high level signal of the first voltage signal end VGH input under the control of the electric potential signal of the 4th node N4, can be passed to the 3rd node N3 by the 8th transistor M8 of increase.When the current potential of Section Point N2 is noble potential, the current potential of the 3rd node N3 is maintained noble potential, avoids the 3rd node N3 to be in suspended state, and then the current potential ensureing Section Point N2 is electronegative potential, the normal output low level signal of first output terminal EOUT, enhances the stability of circuit.

Please refer to Fig. 6, it illustrates the electrical block diagram of another specific embodiment of the shifting deposit unit that the application provides.As shown in Figure 6, the shifting deposit unit 600 that the present embodiment provides can also comprise the 9th transistor M9, the tenth transistor M10, the 11 transistor M11, the 4th electric capacity C4 and the second output terminal SOUT on the basis of the shifting deposit unit 400 shown in Fig. 3.Wherein, the second output terminal SOUT is for exporting gate drive signal.9th transistor M9 is controlled by the electric potential signal of Section Point N2, for signal transmission to the second output terminal SOUT by the first voltage signal end VGH input.Tenth transistor M10 is controlled by the electric potential signal of the 4th node N4, for signal transmission to the second output terminal SOUT inputted by second clock signal end XCK.The signal that 11 transistor M11 is exported by the second output terminal SOUT controls, for by first voltage signal end VGH input signal transmission to Section Point N2.One end of 4th electric capacity C4 is for inputting the electric potential signal of the 4th node N4, and the other end of the 4th electric capacity C4 is for inputting the signal of the second output terminal SOUT output.

In the embodiment shown in fig. 6, shift signal exports by the first output terminal EOUT after the signal that input signal end IN inputs by shifting deposit unit is shifted.The signal that first output terminal EOUT exports can as the input signal of next stage shifting deposit unit.The sweep trace that second output terminal SOUT of shifting deposit unit is used for driving to shifting deposit unit exports gate drive signal.

Particularly, in the embodiment shown in fig. 6, the grid of the 9th transistor M9 is connected with Section Point N2, and first pole of the 9th transistor M9 is connected with the first voltage signal end VGH, and second pole of the 9th transistor M9 is connected with described second output terminal SOUT.The grid of the tenth transistor M10 is connected with the 4th node N4, and first pole of the tenth transistor M10 is connected with second clock signal end XCK, and second pole of the tenth transistor M10 is connected with the second output terminal SOUT.The grid of the 11 transistor is connected with the second output terminal SOUT, and first pole of the 11 transistor M11 is connected with the first voltage signal end VGH, and second pole of the 11 transistor M11 is connected with Section Point N2.One end of 4th electric capacity C4 is connected with the 4th node N4, and the other end of the 4th electric capacity C4 is connected with the second output terminal SOUT.

With embodiment illustrated in fig. 3 unlike, shifting deposit unit 600 shown in Fig. 6 can realize shift signal and gate drive signal exports simultaneously, and, during due to the second output terminal SOUT output low level signal, 11 transistor M11 conducting, the high level signal of the first voltage signal end VGH input is passed to Section Point N2, when the second output terminal SOUT output low level signal, the current potential of Section Point N2 is maintained noble potential, avoid node potential competition, enhance the stability of circuit.

It should be noted that, the transistor in the shifting deposit unit that each embodiment of the application provides can be P-type crystal pipe or N-type transistor.Although schematically illustrate the structure of shifting deposit unit in Fig. 3 to Fig. 6 with P-type crystal pipe, do not form the restriction to transistor types in the application.

The embodiment of the present application additionally provides a kind of shift register comprising above-mentioned shifting deposit unit.Please refer to Fig. 7, it illustrates the structural representation of an embodiment of the shift register that the application provides.As shown in Figure 7, shift register 700 comprises the shifting deposit unit of N number of cascade, wherein, 71,72,73,74 ..., 7 (N-1), 7N represent respectively first order shifting deposit unit, second level shifting deposit unit, third level shifting deposit unit, fourth stage shifting deposit unit ..., (N-1) level shifting deposit unit and N level shifting deposit unit.Wherein, N is positive integer and N>1.Every one-level shifting deposit unit can for any one shifting deposit unit described in above composition graphs 3 to Fig. 6, and the input signal end of first order shifting deposit unit is the shift signal input end IN of shift register, for inputting shift signal.For n-th grade of shift register, its input signal is the output signal of (n-1)th grade of shift register first output terminal EOUT: n for being greater than 1, and is not more than the positive integer of N.Every one-level shifting deposit unit is connected with the first clock signal terminal CK and second clock signal end XCK.Every one-level shifting deposit unit can also comprise the second output terminal SOUT.Such as, in Fig. 7, first output terminal of first order shifting deposit unit 71, second level shifting deposit unit 72, third level shifting deposit unit 73, fourth stage shifting deposit unit 74, (N-1) level shifting deposit unit 7 (N-1) and N level shifting deposit unit 7N is respectively EOUT1, EOUT2, EOUT3, EOUT4, EOUT (N-1), EOUT (N), and the second output terminal is respectively SOUT1, SOUT2, SOUT3, SOUT4, SOUT (N-1), SOUT (N).

In further embodiments, each shifting deposit unit of shift register can also cascade in the following manner: the input signal end of N level shifting deposit unit is as the shift signal input end of shift register, n-th grade of shift register, its input signal is the output signal of (n+1)th grade of shift register first output terminal EOUT: n for being greater than 1, and is less than the positive integer of N.

The embodiment of the present application additionally provides a kind of driving method being applied to above-mentioned shift register.With further reference to Fig. 8, it illustrates embodiment illustrated in fig. 3 in the working timing figure of shifting deposit unit.

Be P-type crystal pipe for the transistor in each embodiment below, the principle of work of the driving method of the shift register that the application provides is described.Wherein, the first level is high level, and second electrical level is low level, and the first voltage is high voltage, and the second voltage is low-voltage.In actual applications, in shifting deposit unit, each transistor also can be N-type transistor, and at this moment the first level is low level, and second electrical level is high level, and the first voltage is low-voltage, and the second voltage is high voltage.

As shown in Figure 8, in a moment before first stage T1, the first clock signal terminal CK inputs second electrical level signal, controls transistor seconds M2 conducting, the current potential of Section Point N2, to Section Point N2, is set to electronegative potential by the second electrical level signal transmission inputted by input signal end IN.5th transistor M5 conducting under the electronegative potential of Section Point N2 controls, is passed to the 4th node N4 by the first voltage signal of the first voltage signal end VGH input.The second electrical level signal that input signal end IN inputs controls the first transistor M1 conducting, thus the first voltage signal of the first voltage signal end VGH input is passed to first node N1.

At first stage T1, provide the first level signal to the first clock signal terminal CK and input signal end IN, provide second electrical level signal to second clock signal end XCK.At this moment, Section Point N2 maintained the electronegative potential in a upper moment, and control the 7th transistor M7 conducting, the first output terminal EOUT of shifting deposit unit exports the second voltage signal VGL.Simultaneously, first output terminal EOUT controls third transistor M3 conducting, the second electrical level signal transmission inputted by second clock signal end XCK is to the 3rd node N3,3rd node N3 is set to electronegative potential, and pass through the coupling of the second electric capacity C2, the current potential of Section Point N2 is reduced further, thus also can conducting the 7th transistor M7 when the 7th transistor M7 threshold of generation value drift, by the second voltage signal VGL totally tansitive to the first output terminal EOUT.Now first node N1 and the 4th node N4 all keeps the noble potential in a moment.

At subordinate phase T2, provide second electrical level signal to the first clock signal terminal CK, provide the first level signal to input signal end IN and second clock signal end XCK.At this moment, the second electrical level signal transmission inputted by the first clock signal terminal CK by the coupling of the first electric capacity C1, to first node N1, makes the current potential of first node N1 keep electronegative potential.The low-potential signal of first node N1 controls the 4th transistor M4 conducting, the second electrical level signal transmission inputted by first clock signal terminal CK is to the 4th node N4, the 4th node N4 is made to keep electronegative potential, thus control the 6th transistor M6 conducting, first voltage signal of the first voltage signal end VGH input is passed to the first output terminal EOUT of shifting deposit unit, the first output terminal EOUT exports the first voltage signal.The second electrical level signal that first clock signal terminal CK inputs controls transistor seconds M2 conducting, the first level signal that input signal end IN inputs is passed to Section Point N2, make Section Point N2 keep high potential state at subordinate phase T2, thus the 7th transistor M7 is ended.In this stage, the 3rd node N3 keeps high potential state under the coupling of the second electric capacity C2.

At phase III T3, provide the first level signal to the first clock signal terminal CK, provide second electrical level signal to input signal end IN and second clock signal end XCK.At this moment, conducting under the control of the low level signal that the first transistor M1 inputs at input signal end IN, is passed to first node N1 by the first voltage signal of the first voltage signal end input, makes first node N1 keep high potential state.The high level signal that first output terminal EOUT exports at the end of subordinate phase T2 controls third transistor M3 cut-off, the current potential of the 3rd node N3 is not by the impact that the level signal of second clock signal end XCK changes, maintain high potential state, the current potential of Section Point N2 also maintains high potential state on last stage under the effect of the second electric capacity C2.Now, 5th transistor M5 cut-off under the noble potential of Section Point N2 controls, 4th node N4 maintains low-potential state on last stage under the effect of the 3rd electric capacity C3, control the 6th transistor M6 conducting, first voltage signal of the first voltage signal end input is passed to the first output terminal EOUT of shifting deposit unit, the first voltage signal described in the first output terminal EOUT exports.

At fourth stage T4, provide second electrical level signal to the first clock signal terminal CK and input signal end IN, provide the first level signal to second clock signal end XCK.Conducting under the control of the second electrical level signal that transistor seconds M2 inputs at the first clock signal terminal CK, the second electrical level signal transmission inputted by input signal end IN, to Section Point N2, makes Section Point N2 change low-potential state into.Conducting under the control of the second electrical level signal that the first transistor M1 inputs at input signal end IN, is passed to first node N1 by the first voltage signal of the first voltage signal end input, makes first node N1 maintain high potential state.5th transistor M5 conducting under the control of the electronegative potential of Section Point N2, the first voltage signal of the first voltage signal end VGH input is passed to the 4th node N4, thus control the 6th transistor M6 ends.7th transistor M7 conducting under the control of the electronegative potential of Section Point N2, second voltage signal of the second voltage signal end input is passed to the first output terminal EOUT of shifting deposit unit, first output terminal EOUT exports the second voltage signal, control third transistor M3 conducting, the first level signal that second clock signal end XCK inputs is passed to the 3rd node N3, makes the 3rd node N3 keep high potential state.

At five-stage T5, provide the first level signal to the first clock signal terminal CK, provide second electrical level signal to input signal end IN and second clock signal end XCK.At this moment, Section Point N2 maintains electronegative potential on last stage, and control the 7th transistor M7 conducting, the first output terminal EOUT exports the second voltage signal.Simultaneously, first output terminal EOUT controls third transistor M3 conducting, the second electrical level signal transmission inputted by second clock signal end XCK is to the 3rd node N3,3rd node N3 is set to electronegative potential, and pass through the coupling of the second electric capacity C2, the current potential of Section Point N2 is reduced further, thus also can conducting the 7th transistor M7 when the 7th transistor M7 threshold of generation value drift, by the second voltage signal VGL totally tansitive to the first output terminal EOUT.Now first node N1 and the 4th node N4 all keeps high potential state on last stage.

In above-mentioned working timing figure, due to shifting deposit unit by export signal feedback to the 3rd node N3, in first stage and five-stage, Section Point N2 being stabilized in low-potential state, can not there is distortion in the signal that shifting deposit unit is exported.And, when signal due to the first output terminal EOUT input at shifting deposit unit overturns, the current potential of Section Point N2 and the 4th node M 4 is unaffected, therefore there is not node potential competition and causes outputing signal abnormal problem, enhance the stability of circuit.

Further, if the structure of shifting deposit unit is circuit structure as shown in Figure 5.Its driving method is consistent with the driving method that above-mentioned composition graphs 8 describes.Compared with the driving method of the shifting deposit unit shown in Fig. 3, in the driving method of the shifting deposit unit shown in Fig. 5, at subordinate phase T2 and phase III T3,8th transistor M8 conducting under the electronegative potential of the 4th node controls, first voltage signal of the first voltage signal end VGH input is passed to the 3rd node N3, avoid the 3rd node N3 to be in suspended state, by the coupling of the second electric capacity C2, the current potential of Section Point N2 is maintained high potential state simultaneously.Thus make the first output terminal EOUT two ends there is not node potential competition, ensure that circuit stability exports.

With further reference to Fig. 9, it illustrates embodiment illustrated in fig. 6 in a working timing figure of circuit structure.In embodiment illustrated in fig. 6, shifting deposit unit adds the second output terminal SOUT, the 9th transistor M9, the tenth transistor M10, the 11 transistor M11 and the 4th electric capacity C4.With Fig. 8 unlike, sequential chart shown in Fig. 9 adds the clock signal schematic diagram of the second output terminal SOUT.

At first stage T1, the 9th transistor M9 conducting under the electronegative potential of Section Point N2 controls, is passed to the second output terminal SOUT by the first voltage signal of the first voltage signal end VGH input.Tenth transistor M10 cut-off under the noble potential of the 4th node N4 controls, the second output terminal SOUT exports high level signal, the 11 transistor M11 cut-off under the high level signal that the second output terminal SOUT exports controls.

At subordinate phase T2,9th transistor M9 cut-off under the noble potential of Section Point N2 controls, tenth transistor M10 conducting under the electronegative potential of the 4th node N4 controls, the high level signal that second clock signal end XCK inputs is passed to the second output terminal SOUT, second output terminal SOUT exports high level signal, the 11 transistor M11 cut-off under the high level signal that the second output terminal SOUT exports controls.

At phase III T3,9th transistor M9 cut-off under the noble potential of Section Point N2 controls, tenth transistor M10 conducting under the electronegative potential of the 4th node N4 controls, the low level signal that second clock signal end XCK inputs is passed to the second output terminal SOUT, the second output terminal SOUT output low level signal.11 transistor M11 conducting under the low level signal that the second output terminal SOUT exports controls, is passed to Section Point N2 by the first voltage signal of the first voltage signal end VGH input, ensures that Section Point maintains high potential state within this stage.

At fourth stage T4, the 9th transistor M9 conducting under the electronegative potential of Section Point N2 controls, is passed to the second output terminal SOUT by the first voltage signal of the first voltage signal end VGH input.Tenth transistor M10 cut-off under the noble potential of the 4th node N4 controls, the second output terminal SOUT exports high level signal, the 11 transistor M11 cut-off under the high level signal that the second output terminal SOUT exports controls.

At five-stage T5, the 9th transistor M9 conducting under the electronegative potential of Section Point N2 controls, is passed to the second output terminal SOUT by the first voltage signal of the first voltage signal end VGH input.Tenth transistor M10 cut-off under the noble potential of the 4th node N4 controls, the second output terminal SOUT exports high level signal, the 11 transistor M11 cut-off under the high level signal that the second output terminal SOUT exports controls.

As can be seen from Figure 9, the signal that input signal end IN can input by the second output terminal SOUT of shifting deposit unit is shifted and anti-phase rear output.First output terminal EOUT can be connected with the input signal end of next stage shifting deposit unit, as the input signal of next stage shifting deposit unit.Second output terminal SOUT can be connected with the sweep trace on display panel, and the signal that the second output terminal SOUT exports as thin film transistor (TFT) corresponding to sweep signal conducting a line grid line, can be charged to this row sub-pixel by data line.

The embodiment of the present application additionally provides the driving method that another kind is applied to above-mentioned shift register.Please refer to Figure 10, it illustrates embodiment illustrated in fig. 3 in another working timing figure of circuit structure.With embodiment illustrated in fig. 8 unlike, the inversion signal of signal that the signal that in sequential chart shown in Figure 10, input signal end IN inputs inputs for input signal end IN in sequential chart shown in Fig. 8.

As shown in Figure 10, in a moment before first stage T1, the first clock signal terminal CK inputs second electrical level signal, controls transistor seconds M2 conducting, the first level signal that input signal end IN inputs is passed to Section Point N2, the current potential of Section Point N2 is set to noble potential.First node N1 is maintaining low-potential state in the coupling of the first electric capacity C1, controls the 4th transistor M4 conducting, and the second electric potential signal that the first clock signal terminal CK inputs is passed to the 4th node N4, makes the 4th node N4 keep low-potential state.

At first stage T1, provide described first level signal to the first clock signal terminal CK, provide described second electrical level signal to second clock signal XCK, input signal end IN.Conducting under the control of the second electrical level signal that the first transistor M1 inputs at input signal end IN, is passed to first node N1 by the first voltage signal of the first voltage signal end VGH input, makes first node N1 keep high potential state.End under the control of the first level signal that transistor seconds M2 inputs at the first clock signal terminal CK, Section Point N2 kept the high potential state in a upper moment, and control the 7th transistor M7 ends; 4th node N4 kept the low-potential state in a upper moment, controlled the 6th transistor M6 conducting, by signal transmission to the first output terminal EOUT of the first voltage signal end VGH input.At this moment, the first output terminal EOUT exports the first voltage signal.

At subordinate phase T2, provide second electrical level signal to the first clock signal terminal CK, input signal end IN, provide the first level signal to second clock signal end XCK.Conducting under the control of the second electrical level signal that the first transistor M1 inputs at input signal end IN, is passed to first node N1 by the first voltage signal of the first voltage signal end VGH input, makes the current potential of first node N1 keep high potential state.Conducting under the control of the second electrical level signal that transistor seconds M2 inputs at the first clock signal terminal CK, the second electric potential signal that input signal end IN inputs is passed to Section Point N2, Section Point N2 is made to be converted to low-potential state, and then conducting the 7th transistor M7, the second voltage signal of the second voltage signal end VGL input is passed to the first output terminal EOUT.First output terminal EOUT exports the second voltage signal, control third transistor M3 conducting, the second electrical level signal transmission inputted by second clock signal end XCK, to the 3rd node N3, makes the 3rd node N3 keep low-potential state, drags down the current potential of Section Point N2 further.5th transistor M5 conducting under the electronegative potential of Section Point controls, is passed to the 4th node N4 by the first voltage signal of the first voltage signal end VGH input, makes the 4th node N4 keep high potential state.

At phase III T3, provide the first level signal to the first clock signal terminal CK, input signal end IN, provide second electrical level signal to second clock signal end XCK.One end of first electric capacity C1 inputs the first level signal, and first node N1 maintains high potential state under the coupling of the first electric capacity C1.Section Point N2 keeps low-potential state on last stage, conducting the 7th transistor M7, and the second voltage signal of the second voltage signal end VGL input is passed to the first output terminal EOUT.First output terminal EOUT exports the second voltage signal, controls third transistor M3 conducting, and the second electrical level signal transmission inputted by second clock signal end XCK, to the 3rd node N3, makes the 3rd node N3 keep low-potential state.Under the coupling of the second electric capacity C2, the electronegative potential of Section Point N2 drags down further, 5th transistor M5 conducting under the electronegative potential of Section Point N2 controls, first voltage signal of the first voltage signal end VGH input is passed to the 4th node N4, make the 4th node N4 keep high potential state, thus control the 6th transistor M6 end.

At fourth stage T4, provide second electrical level signal to the first clock signal terminal CK, provide the first level signal to second clock signal end XCK, input signal end IN.Transistor seconds M2 conducting under the second electrical level signal that the first clock signal terminal CK inputs controls, is passed to Section Point N2 by the first level signal that input signal end IN inputs, and makes Section Point N2 keep high potential state.End under the control of the first level signal that the first transistor M1 inputs at input signal end IN, first node N1 is converted to low-potential state under the coupling of the first electric capacity C1, thus conducting the 4th transistor M4, the second electrical level signal transmission inputted by first clock signal terminal CK is to the 4th node N4, the 4th node N4 is made to keep low-potential state in this stage, thus conducting the 6th transistor M6, first voltage signal of the first voltage signal end VGH input is passed to the first output terminal EOUT, first output terminal EOUT exports the first voltage signal, control third transistor M3 cut-off, 3rd node N3 is converted to high potential state under the coupling of the second electric capacity C2.

At five-stage, provide the first level signal to the first clock signal terminal CK, input signal end IN, provide described second electrical level signal to second clock signal end XCK.End under the control of the first level signal that the first transistor M1 inputs at input signal end IN, end under the control of the first level signal that transistor seconds M2 inputs at the first clock signal terminal CK, Section Point N2 kept the high potential state in a upper moment, controlled the 7th transistor M7 and ended; First node N1 changes high potential state under the coupling of the first electric capacity C1, therefore, 4th node N4 maintains low-potential state on last stage, controls the 6th transistor M6 conducting, by signal transmission to the first output terminal EOUT of the first voltage signal end VGH input.At this moment, the first output terminal EOUT exports the first voltage signal.

The driving method of the shift register that the embodiment of the present application provides, the signal no matter input signal end inputs is high level signal or low level signal, all can realize the displacement of signal.Owing to being controlled the electric potential signal of the 3rd node N3 by the first output terminal EOUT of shifting deposit unit, drag down the current potential of Section Point N2 further, the threshold drift due to transistor can be compensated, ensure the output terminal of shift signal totally tansitive to shifting deposit unit, thus increase the process window of circuit, improve the stability of circuit.

On the basis of above-described embodiment, the embodiment of the present application additionally provides a kind of display device, applies the driving method of shifting deposit unit described by above embodiment and shifting deposit unit.Be appreciated that display device can also comprise other known structures, as pel array, multi-strip scanning line, insulate with multi-strip scanning line crossing a plurality of data lines etc.

More than describe and be only the preferred embodiment of the application and the explanation to institute's application technology principle.Those skilled in the art are to be understood that, invention scope involved in the application, be not limited to the technical scheme of the particular combination of above-mentioned technical characteristic, also should be encompassed in when not departing from described inventive concept, other technical scheme of being carried out combination in any by above-mentioned technical characteristic or its equivalent feature and being formed simultaneously.The technical characteristic that such as, disclosed in above-mentioned feature and the application (but being not limited to) has similar functions is replaced mutually and the technical scheme formed.

Claims (10)

1. a shifting deposit unit, comprise the first transistor, transistor seconds, third transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor, the first electric capacity, the second electric capacity, the 3rd electric capacity, input signal end, the first clock signal terminal, second clock signal end, the first voltage signal end, the second voltage signal end and the first output terminal, wherein
The signal that described the first transistor is inputted by described input signal end controls, for by described first voltage signal end input signal transmission to first node;
The signal that described transistor seconds is inputted by described first clock signal terminal controls, for by the signal transmission of described input signal end input to Section Point;
The signal that described third transistor is exported by described first output terminal controls, for by the signal transmission of described second clock signal end input to the 3rd node;
Described 4th transistor is controlled by the electric potential signal of described first node, for by described first clock signal terminal input signal or described second voltage signal end input signal transmission to the 4th node;
Described 5th transistor is controlled by the electric potential signal of described Section Point, for signal transmission extremely described 4th node by described first voltage signal end input;
Described 6th transistor is controlled by the electric potential signal of described 4th node, for signal transmission extremely described first output terminal by described first voltage signal end input;
Described 7th transistor is controlled by the electric potential signal of described Section Point, for signal transmission extremely described first output terminal by described second voltage signal end input;
One end of described first electric capacity is for inputting the signal of described first clock signal terminal input, and the other end of described first electric capacity is for inputting the electric potential signal of described first node;
One end of described second electric capacity is for inputting the electric potential signal of described 3rd node, and the other end of described second electric capacity is for inputting the electric potential signal of described Section Point;
One end of described 3rd electric capacity is for inputting the signal of described first voltage signal end, and the other end of described 3rd electric capacity is for inputting the electric potential signal of described 4th node.
2. shifting deposit unit according to claim 1, it is characterized in that, the grid of described the first transistor is connected with described input signal end, and the first pole of described the first transistor is connected with described first voltage signal end, and the second pole of described the first transistor is connected with described first node;
The grid of described transistor seconds is connected with described first clock signal terminal, and the first pole of described transistor seconds is connected with described input signal end, and the second pole of described transistor seconds is connected with described Section Point;
The grid of described third transistor is connected with the first output terminal of described shifting deposit unit, and the first pole of described third transistor is connected with described second clock signal end, and the second pole of described third transistor is connected with described 3rd node;
The grid of described 4th transistor is connected with described first node, and the first pole of described 4th transistor is connected with described first clock signal terminal or described second voltage signal end, and the second pole of described 4th transistor is connected with described 4th node;
The grid of described 5th transistor is connected with described Section Point, and the first pole of described 5th transistor is connected with described first voltage signal end, and the second pole of described 5th transistor is connected with described 4th node;
The grid of described 6th transistor is connected with described 4th node, and the first pole of described 6th transistor is connected with described first voltage signal end, and the second pole of described 6th transistor is connected with described first output terminal;
The grid of described 7th transistor is connected with described Section Point, and the first pole of described 7th transistor is connected with described second voltage signal end, and the second pole of described 7th transistor is connected with described first output terminal;
One end of described first electric capacity is connected with described first clock signal terminal, and the other end of described first electric capacity is connected with described first node;
One end of described second electric capacity is connected with described 3rd node, and the other end of described second electric capacity is connected with described Section Point;
One end of described 3rd electric capacity is connected with described first voltage signal end, and the other end of described 3rd electric capacity is connected with described 4th node.
3. shifting deposit unit according to claim 1, it is characterized in that, described shifting deposit unit also comprises the 8th transistor, and described 8th transistor is controlled by the electric potential signal of described 4th node, by the signal transmission of described first voltage signal end input to described 3rd node.
4. shifting deposit unit according to claim 3, the grid of described 8th transistor is connected with described 4th node, first pole of described 8th transistor is connected with described first voltage signal end, and the second pole of described 8th transistor is connected with described 3rd node.
5. shifting deposit unit according to claim 1, is characterized in that, described shifting deposit unit also comprises:
Second output terminal;
9th transistor, is controlled by the electric potential signal of described Section Point, for signal transmission extremely described second output terminal by described first voltage signal end input;
Tenth transistor, is controlled by the electric potential signal of described 4th node, for signal transmission extremely described second output terminal by described second clock signal end input;
11 transistor, the signal exported by described second output terminal controls, for the signal transmission extremely described Section Point by described first voltage signal end input;
4th electric capacity, one end of described 4th electric capacity is for inputting the electric potential signal of described 4th node, and the other end of described 4th electric capacity is for inputting the signal of described second output terminal output.
6. shifting deposit unit according to claim 5, it is characterized in that, the grid of described 9th transistor is connected with described Section Point, and the first pole of described 9th transistor is connected with described first voltage signal end, and the second pole of described 9th transistor is connected with described second output terminal;
The grid of described tenth transistor is connected with described 4th node, and the first pole of described tenth transistor is connected with described second clock signal end, and the second pole of described tenth transistor is connected with described second output terminal;
The grid of described 11 transistor is connected with described second output terminal, and the first pole of described 11 transistor is connected with described first voltage signal end, and the second pole of described 11 transistor is connected with described Section Point;
One end of described 4th electric capacity is connected with described 4th node, and the other end of described 4th electric capacity is connected with described second output terminal.
7. a shift register, comprises the shifting deposit unit of the N number of cascade described in any one of claim 1-6.
8. drive a method for the shifting deposit unit as described in any one of claim 1-6, comprising:
First stage, provide the first level signal to described first clock signal terminal and described input signal end, provide second electrical level signal to described second clock signal end, described first output terminal exports the second voltage signal;
Subordinate phase, provides described second electrical level signal to described first clock signal terminal, provides described first level signal to described input signal end and described second clock signal end, described first output terminal first voltage signal;
Phase III, provide described first level signal to described first clock signal terminal, provide described second electrical level signal to described input signal end and described second clock signal end, described first output terminal exports described first voltage signal;
Fourth stage, provides described second electrical level signal to described first clock signal terminal and input signal end, provides described first level signal to described second clock signal end, and described first output terminal exports described second voltage signal;
Five-stage, provides described first level signal to described first clock signal terminal, provides described second electrical level signal to described input signal end and described second clock signal end, and described first output terminal exports described second voltage signal.
9. drive a method for the shifting deposit unit as described in any one of claim 1-6, comprising:
In the first stage, provide described first level signal to described first clock signal terminal, provide described second electrical level signal to described second clock signal, described input signal end, described first output terminal exports described first voltage signal;
In subordinate phase, provide described second electrical level signal, provide described first level signal to described second clock signal end to described first clock signal terminal, described input signal end, described first output terminal exports described second voltage signal;
In the phase III, provide described first level signal, provide described second electrical level signal to described second clock signal end to described first clock signal terminal, described input signal end, described first output terminal exports described second voltage signal;
In fourth stage, provide described second electrical level signal to described first clock signal terminal, provide described first level signal to described second clock signal end, described input signal end, described first output terminal exports described first voltage signal;
At five-stage, provide described first level signal, provide described second electrical level signal to described second clock signal end to described first clock signal terminal, input signal end, described first output terminal exports described first voltage signal.
10. a display device, applies the shifting deposit unit as described in any one of claim 1-6 and the driving method as described in claim 8 or 9.
CN201510993310.2A 2015-12-25 2015-12-25 Shifting deposit unit, shift register and its driving method, display device CN105405383B (en)

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