CN104575419A - Shifting register and driving method thereof - Google Patents

Shifting register and driving method thereof Download PDF

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Publication number
CN104575419A
CN104575419A CN201410738158.9A CN201410738158A CN104575419A CN 104575419 A CN104575419 A CN 104575419A CN 201410738158 A CN201410738158 A CN 201410738158A CN 104575419 A CN104575419 A CN 104575419A
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reset
module
transistor
shift register
reset transistor
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CN104575419B (en
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孙云刚
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Tianma Microelectronics Co Ltd
Shanghai Tianma Microelectronics Co Ltd
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Tianma Microelectronics Co Ltd
Shanghai Tianma Microelectronics Co Ltd
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Abstract

The invention discloses a shifting register and a driving method thereof. The shifting register comprises a plurality stages of cascaded shifting register circuits, a first reset module and a second reset module, wherein each stage of shifting register circuit comprises a main output end, a main input module, a first output module and a second output module; the node between each main input module and each first output module is a first node; the first reset module is used for resetting the first nodes and the main output ends to low level according to a first reset signal input by a reset signal input end; the second reset module is used for receiving a second reset signal output by the next stage of shifting register circuit to reset the first nodes and the main output ends to low level. Before inputting an initial signal, the first reset module resets voltage of the first nodes and the main output ends, so that the gate driving signals are not influenced by the threshold voltage shifting of thin film transistors and the problem that the display units display abnormally due to the threshold voltage shifting of the thin film transistors in the prior art is solved.

Description

A kind of shift register and driving method thereof
Technical field
The present invention relates to liquid crystal flat-panel display technique field, particularly relate to a kind of shift register and driving method thereof.
Background technology
Liquid crystal display (LCD) is generally made up of the drive unit of display panels and outside thereof, and drive unit is used for providing drive singal for display unit.At present, integrated drive unit on a display panel can make the more compact structure of display, such as, be integrated on display pannel for the pixel cell of display panel provide gate drive signal amorphous silicon gate could electrode driving device, because amorphous silicon film transistor technology is relatively ripe, homogeneity is good, and cost is lower, and therefore amorphous silicon gate could electrode driving device is widely used in liquid crystal display.
Shift register in amorphous silicon drive unit; comprise multiple shifting deposit unit; the shift register circuit of each shifting deposit unit is made up of multiple thin film transistor (TFT) usually; change when easily making its threshold voltage under the state that thin film transistor (TFT) is in long-term conducting; be called the drift of threshold voltage; the accumulation of the drift of this threshold voltage can make gate drive apparatus produce extremely the driving of display unit usually, causes the abnormal show of display unit.Such as there is the pull-down transistor of drop-down current potential effect, because when the row pixel cell of display panel is not by driving, pull-down transistor in the gate drive apparatus of this row pixel cell will be in conducting state always, and the threshold voltage shift being in the thin film transistor (TFT) under conducting state for a long time easily makes the output signal of gate drive apparatus abnormal.
To sum up, there is the thin film transistor (TFT) in gate drive apparatus in prior art and can produce the driving of display unit abnormal because of the drift of threshold voltage, cause the problem of the abnormal show of display unit.
Summary of the invention
The embodiment of the present invention provides a kind of shift register and driving method thereof, can produce the driving of display unit abnormal in order to solve the thin film transistor (TFT) in the gate drive apparatus that exists in prior art because of the drift of threshold voltage, cause the problem of the abnormal show of display unit.
The embodiment of the present invention provides a kind of shift register, comprises the shift register circuit of multi-stage cascade, and every one-level shift register circuit, comprising:
Main output terminal, for output drive signal;
Primary input module, for receiving initialize signal;
First output module, is connected between described primary input module and described main output terminal, and for exporting high level drive singal according to second clock signal, the node between described primary input module and described first output module is first node;
Second output module, is connected with described main output terminal, for according to the first clock signal output low level drive singal;
Also comprise:
First reseting module, for the first reset signal inputted according to reset signal input end, makes described first node and described main output terminal be reset to low level;
Wherein, described first reseting module comprises: the first reset transistor M1, the second reset transistor M2; The grid of described first reset transistor M1, the grid of described second reset transistor M2 are all connected with described reset signal input end, first electrode of described first reset transistor M1 is connected with described first node, and first electrode of described second reset transistor M2 is connected with described main output terminal; Second electrode of described first reset transistor M1, second electrode of described second reset transistor M2 are all connected with low level signal input end;
Second reseting module, is connected between described first node and described first reseting module, for receiving the second reset signal that next stage shift-register circuit exports, makes described first node and described main output terminal be reset to low level.
A kind of shift register that above-described embodiment provides, the first reset transistor M1 that in every one-level shift register circuit, the first reseting module comprises and the second reset transistor M2 can realize before the switching transistor input initialize signal to every one-level shift register circuit, by the voltage amplitude of first node and main output terminal, the gate drive signal that the shift register circuit of every one-level is produced is not by the impact of the drift of the threshold voltage of thin film transistor (TFT), ensure the driven of shift register and the normal display of display unit, relative to prior art, when not increasing thin film transistor (TFT), solve the drift meeting of the thin film transistor (TFT) in the gate drive apparatus existed in prior art because of threshold voltage to the driving generation exception of display unit, cause the problem of the abnormal show of display unit.In addition, the first reset transistor M1 that in every one-level shift register circuit, the first reseting module comprises and the second reset transistor M2, can also realize when the output terminal of the shift register circuit of next stage export high level drive singal and the reset signal fed back to this shift register circuit time, by the voltage amplitude of first node and main output terminal, no longer export high level drive singal to the grid of display unit to make this grade of shift register circuit.
Further, described first reseting module also comprises: the 3rd reset transistor M0;
Reset signal input end described in the grid of described 3rd reset transistor M0, the first Electrode connection, the grid of the first reset transistor M1 described in the second Electrode connection, the grid of described second reset transistor M2.This embodiment adds the thin film transistor (TFT) M0 used as diode on the basis of above-described embodiment, for receiving the first reset signal, and according to the normal startup of high and low Automatic level control first reseting module of the first reset signal and closedown.That is when the first reset signal is high level, or when receiving the first reset signal of high level, thin film transistor (TFT) M0 is as diode current flow, make the first reset transistor M1, second reset transistor M2 conducting, realize before the switching transistor input initialize signal to every one-level shift register circuit, by the voltage amplitude of first node and main output terminal, the gate drive signal that the shift register circuit of every one-level is produced is not by the impact of the drift of the threshold voltage of thin film transistor (TFT), ensure the driven of shift register and the normal display of display unit, first reset signal is low level, or when the first reset signal of high level disappears, thin film transistor (TFT) M0 ends, make the first reset transistor M1, the second reset transistor M2 ends, first reseting module is resetted terminate, start to make the switching transistor to every one-level shift register circuit to receive input initialize signal, produce for display unit and export gate drive signal.
Further, described second reseting module comprises the 4th reset transistor M7;
The described grid of the 4th reset transistor M7 is connected with the main output terminal of next stage shift-register circuit, and first Electrode connection of the first electrode and described first reset transistor M1, the second electrode is connected with low level control signal input part.
Further, described primary input module comprises switching transistor M3;
The grid of described switching transistor M3 is connected with initialize signal input end, and the first electrode is connected with high-level control signal input end, and the second electrode is connected with described first node.
Further, described first output module comprises the first electric capacity C1 and the M4 that pulls up transistor;
Wherein, described first electric capacity C1 is connected between described first node and described main output terminal, described in the pull up transistor grid of M4 be connected with described first node, the first electrode is connected with second clock signal input part, and the second electrode is connected with described main output terminal.
Further, described second output module comprises transistor M5;
The grid of described transistor M5 is connected with the first clock signal input terminal, and the first electrode is connected with described main output terminal, and the second electrode is connected with low level signal input end.
Further, between described first node and described first output module, drop-down module is also had access to; Described drop-down module comprises: pull-down transistor M6 and the second electric capacity C2;
Wherein, the grid of described pull-down transistor M6 is connected with described first node, first electrode is connected with the first end of described second electric capacity C2, second electrode is connected with low level signal input end, and second end of described second electric capacity C2 is connected with the second clock signal input part of described first output module.
Based on a kind of shift register that above-described embodiment provides, embodiments provide a kind of driving method of every one-level shift register circuit of shift register, the method comprises:
Described every one-level shift register circuit comprises the first reseting stage;
At the first reseting stage, the first reset signal is inputted at described reset signal input end, cause the first reset transistor M1 of described first reseting module, the second reset transistor M2 conducting, the voltage amplitude of described first node and described main output terminal is low level.
In above-described embodiment, at the first reseting stage, in the first reset signal of the high level of reset signal input end input, trigger the normal startup of the first reseting module, realize after making the first reset transistor M1 and the second reset transistor M2 conducting before the switching transistor input initialize signal to every one-level shift register circuit, by the voltage amplitude of first node and main output terminal, the gate drive signal that the shift register circuit of every one-level is produced is not by the impact of the drift of the threshold voltage of thin film transistor (TFT), ensure the driven of shift register and the normal display of display unit.Relative to prior art, when not increasing thin film transistor (TFT), solving the thin film transistor (TFT) in the gate drive apparatus existed in prior art can produce abnormal because of the drift of threshold voltage to the driving of display unit, cause the problem of the abnormal show of display unit.
Further, at the first reseting stage, the first reset signal is inputted at described reset signal input end, cause the 3rd reset transistor M0 of described first reseting module, the first reset transistor M1, the second reset transistor M2 conducting, cause the voltage amplitude of described first node and described main output terminal to be low level.
In above-described embodiment, at the first reseting stage, in the first reset signal of the high level of reset signal input end input, make the thin film transistor (TFT) M0 conducting used as diode, trigger the normal startup of the first reseting module, realize after making the first reset transistor M1 and the second reset transistor M2 conducting before the switching transistor input initialize signal to every one-level shift register circuit, by the voltage amplitude of first node and main output terminal, the gate drive signal that the shift register circuit of every one-level is produced is not by the impact of the drift of the threshold voltage of thin film transistor (TFT), ensure the driven of shift register and the normal display of display unit.
Further, described every one-level shift register circuit also comprises: level signal generation phase, low level drive singal export the stage, high level drive singal exports stage, the second reseting stage;
At level signal generation phase, at described primary input end input initialize signal, cause described first node to be high level, the first reset transistor M1 of described first reseting module and the grid of the second reset transistor M2 are low level;
Export the stage at low level drive singal, in the first clock signal of described first clock signal input terminal input high level, cause the second output module to described main output terminal output low level drive singal;
Export the stage at high level drive singal, at the second clock signal of described second clock signal input part input high level, cause the first output module to export high level drive singal to described main output terminal;
At the second reseting stage, high level second reset signal that the main output terminal that described second reseting module receives next stage shift-register circuit exports, described first node is caused to be reset to low level, the second clock signal of the first reset transistor M1 of described first reseting module and the grid input high level of the second reset transistor M2, causes described main output terminal to be reset to low level.In above-described embodiment, at the second reseting stage, high level second reset signal that the main output terminal that second reseting module receives next stage shift-register circuit exports, trigger the second reseting module to start, the first reset transistor M1 that first reseting module in every one-level shift register circuit is comprised and the second reset transistor M2, realize output terminal output high level drive singal when the shift register circuit of next stage and the reset signal fed back to this shift register circuit time, by the voltage amplitude of first node and main output terminal, no longer high level drive singal is exported to the grid of display unit to make this grade of shift register circuit.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly introduced, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these attached+-Tu.
The circuit diagram of a kind of shift register circuit that Fig. 1 provides for the embodiment of the present invention;
The circuit diagram of every one-level shift register circuit of a kind of shift register that Fig. 2 provides for the embodiment of the present invention;
The circuit diagram of every one-level shift register circuit of a kind of shift register that Fig. 3 provides for the embodiment of the present invention;
The structural representation of a kind of shift register that Fig. 4 provides for the embodiment of the present invention;
A kind of shift register working timing figure that Fig. 5 provides for the embodiment of the present invention.
Embodiment
In order to make the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the present invention is described in further detail, and obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the design concept of the embodiment of the present invention, those of ordinary skill in the art also should fall within protection scope of the present invention not making other embodiments all obtained by carrying out the mode of replacing etc. to the type of thin film transistor (TFT) under creative work prerequisite.
Can produce abnormal in order to solve the thin film transistor (TFT) in the gate drive apparatus that exists in prior art to the driving of display unit because of the drift of threshold voltage, cause the problem of the abnormal show of display unit, inventor proposes, by comprising multiple thin film transistor (TFT) as reseting module in each shifting deposit unit, realize the grid potential set again by thin film transistor (TFT) output terminal and thin film transistor (TFT) before shifting deposit unit produces drive singal, the impact of the drift of thin film transistor (TFT) threshold voltage is not subject to the drive singal that display unit exports to make gate drive apparatus, specifically see embodiment 1.
Embodiment 1
The circuit diagram of a kind of shift register circuit as shown in Figure 1, it comprises 9 thin film transistor (TFT)s, 2 electric capacity C1 and C2, wherein, reseting module comprises two thin film transistor (TFT) M1 and M2, switching thin-film transistor M3, for thin film transistor (TFT) M4 and M5 of output drive signal, for the thin film transistor (TFT) M6 of drop-down current potential, M7, M8, M9.Wherein first node is P, Section Point is Q, Gout is main output, primary input end STP, for inputting initialize signal, Gn+1 is the input end of the signal of next stage shift register circuit output terminal feedback, and VGL is low level signal source, reset signal Reset input end, first clock signal clk input end, second clock signal CLKB input end, wherein, the first clock signal clk and second clock signal CLKB anti-phase.The driving process that shift register circuit as shown in Figure 1 produces drive singal is:
First stage, hold the initialize signal of input high level at STP before, the Reset signal of input high level, thin film transistor (TFT) M1 and M2 conducting, cause P point and main output terminal Gout to be reset to low level;
Subordinate phase, at the initialize signal of primary input end STP input high level, cause M3 conducting, P point is high level, M4 conducting, because P point is high level, cause pull-down thin film M6 conducting, Q point is connected with low level signal source, and in the first half clock cycle, the first clock signal clk of input high level causes Gout output low level drive singal, and in the second half clock cycle, the second clock signal CLKB of input high level makes Gout export high level drive singal;
Phase III, after Gout to export the drive singal of a clock period to display unit, the feedback signal of Gn+1 input end input high level, cause thin film transistor (TFT) M7 conducting, P point is connected with low level signal source, P point becomes low level, pull-down thin film M6 is caused to end, Q point unsettled (not namely being connected with low level signal source VGL), the second clock signal CLKB of high level makes Q point be high level by C2, thin film transistor (TFT) M8 and M9 conducting, P point is caused to be connected with low level signal source VGL with Gout point, the main output terminal of Gout is made no longer to export gate drive signal to display unit at following clock cycle.
To sum up, shift register circuit as shown in Figure 1, by increasing reseting module, be low level by the current potential set of main for Gout output terminal before the initialize signal of primary input end STP input high level, make drive singal that gate drive apparatus exports to display unit by the impact of the drift of thin film transistor (TFT) threshold voltage.But the reseting module of shift register circuit is as shown in Figure 1 made up of two thin film transistor (TFT) M1 and M2, two thin film transistor (TFT)s newly increased and wire frame thereof can take larger space, are unfavorable for narrow frame and the lightness of liquid crystal display.
In order to obtain more excellent embodiment, the present invention is on the basis of shift register circuit as shown in Figure 1, such scheme is carried out improving and expanding, thin film transistor (TFT) M1 and M2 of shift register circuit is as shown in Figure 1 removed, by the access of reset signal Reset input end between thin film transistor (TFT) M8 and M9, controlling thin film transistor (TFT) M8 and M9 before the initialize signal of primary input end STP input high level by Reset reset signal is low level by the current potential set of main for Gout output terminal, gate drive apparatus is made not to be subject to the impact of the drift of thin film transistor (TFT) threshold voltage to the drive singal that display unit exports, solve the drift meeting driving to display unit of the thin film transistor (TFT) in the gate drive apparatus existed in prior art because of threshold voltage ' produce extremely, cause the problem of the abnormal show of display unit.
Thin film transistor (TFT) M1 and M2 of shift register circuit as shown in Figure 1 removes by the embodiment of the present invention, saves taking up room of shift register, is conducive to narrow frame and the lightness of liquid crystal display.
In addition, the above-mentioned improvement of the embodiment of the present invention, makes thin film transistor (TFT) M8 and M9 all play the effect of drop-down current potential in first stage and phase III, thus improves the utilization factor of thin film transistor (TFT) M8 and M9.
Below in conjunction with a kind of shift register that accompanying drawing provides the embodiment of the present invention, and the every one-level shift register circuit in shift register is described in detail.
Embodiment 2
A kind of shift register that the embodiment of the present invention as shown in Figure 2 provides, this shift register comprises the shift register circuit of multi-stage cascade, and every one-level shift register circuit, comprising:
Main output terminal Gout, for output drive signal, comprises high level drive singal and low level drive singal;
Primary input module 201, for receiving initialize signal STP;
First output module 202, be connected between described primary input module 201 and described main output terminal Gout, for exporting high level drive singal according to second clock signal, the node between described primary input module 201 and described first output module 202 is first node P point;
Second output module 203, is connected with described main output terminal Gout, for according to the first clock signal output low level drive singal;
Also comprise: the first reseting module 204, for the first reset signal RESET inputted according to reset signal input end, make described first node P and described main output terminal Gout be reset to low level; Wherein, described first reseting module 204 comprises: the first reset transistor M1, the second reset transistor M2; The grid of described first reset transistor M1, the grid of described second reset transistor M2 are all connected with described reset signal input end, first electrode of described first reset transistor M1 is connected with described first node, and first electrode of described second reset transistor M2 is connected with described main output terminal Gout; Second electrode of described first reset transistor M1, second electrode of described second reset transistor M2 are all connected with low level signal VGL input end;
Second reseting module 205, is connected between described first node P and described first reseting module 204, for receiving the second reset signal Gn+1 that next stage shift-register circuit exports, makes described first node P and described main output terminal Gout be reset to low level.
In above-described embodiment, first clock signal is the CKL clock signal of high level, second clock signal is the CKB clock signal of high level, and second clock signal is the inverting clock signal of the first clock signal, and the cycle of the first clock signal and second clock signal is half clock period.
Preferably, in circuit as shown in Figure 2, described primary input module 201 comprises switching transistor M3; The grid of described switching transistor M3 is connected with initialize signal input end, and the first electrode is connected with high-level control signal DIR1 input end, and the second electrode is connected with described first node P.
Described first output module 202 comprises the first electric capacity C1 and the M4 that pulls up transistor; Wherein, described first electric capacity C1 is connected between described first node P and described main output terminal Gout, the grid of the described M4 of pulling up transistor is connected with described first node P, and the first electrode is connected with second clock signal input part, and the second electrode is connected with described main output terminal Gout.
Described second output module 203 comprises transistor M5; The grid of described transistor M5 is connected with the first clock signal input terminal, and the first electrode is connected with described main output terminal Gout, and the second electrode is connected with low level signal VGL input end.
Described second reseting module 205 comprises the 4th reset transistor M7; The grid of described 4th reset transistor M7 is connected with the main output terminal Gout of next stage shift-register circuit, first Electrode connection of the first electrode and described first reset transistor M1, and the second electrode is connected with low level control signal DIR2 input end.
Drop-down module 206 is also had access between described first node P and described first output module 202; Described drop-down module 206 comprises: pull-down transistor M6 and the second electric capacity C2; Wherein, the grid of described pull-down transistor M6 is connected with described first node P, first electrode is connected with the first end of described second electric capacity C2, second electrode is connected with low level signal VGL input end, and second end of described second electric capacity C2 is connected with the second clock signal input part of described first output module 202.
A kind of shift register that above-described embodiment provides, the first reset transistor M1 that in every one-level shift register circuit, the first reseting module comprises and the second reset transistor M2 can realize before the switching transistor input initialize signal to every one-level shift register circuit, by the voltage amplitude of first node and main output terminal, the gate drive signal that the shift register circuit of every one-level is produced is not by the impact of the drift of the threshold voltage of thin film transistor (TFT), ensure the driven of shift register and the normal display of display unit, relative to prior art, when not increasing thin film transistor (TFT), solve the drift meeting of the thin film transistor (TFT) in the gate drive apparatus existed in prior art because of threshold voltage to the driving generation exception of display unit, cause the problem of the abnormal show of display unit.In addition, the first reset transistor M1 that in every one-level shift register circuit, the first reseting module comprises and the second reset transistor M2, can also realize when the output terminal of the shift register circuit of next stage export high level drive singal and the reset signal fed back to this shift register circuit time, by the voltage amplitude of first node and main output terminal, no longer export high level drive singal to the grid of display unit to make this grade of shift register circuit.
Embodiment 3
A kind of shift register that a kind of embodiment of the present invention as shown in Figure 3 provides, this shift register comprises the shift register circuit of multi-stage cascade, every one-level shift register circuit is on the basis of shift register circuit as shown in Figure 2, a thin film transistor (TFT) M0 is added in the first reseting module, as shown in Figure 3, this shift register circuit comprises: main output terminal Gout, for output drive signal, comprises high level drive singal and low level drive singal;
Primary input module 201, for receiving initialize signal STP;
First output module 202, be connected between described primary input module 201 and described main output terminal Gout, for exporting high level drive singal according to second clock signal, the node between described primary input module 201 and described first output module 202 is first node P point;
Second output module 203, is connected with described main output terminal Gout, for according to the first clock signal output low level drive singal;
First reseting module 204, for the first reset signal RESET inputted according to reset signal input end, makes described first node P and described main output terminal Gout be reset to low level; Wherein, described first reseting module 204 comprises: the first reset transistor M1, the second reset transistor M2, the 3rd reset transistor M0; Reset signal RESET input end described in the grid of described 3rd reset transistor M0, the first Electrode connection, the grid of the first reset transistor M1 described in the second Electrode connection, the grid of described second reset transistor M2; First electrode of described first reset transistor M1 is connected with described first node P, and first electrode of described second reset transistor M2 is connected with described main output terminal Gout; Second electrode of described first reset transistor M1, second electrode of described second reset transistor M2 are all connected with low level signal VGL input end;
Second reseting module 205, is connected between described first node P and described first reseting module 204, for receiving the second reset signal Gn+1 that next stage shift-register circuit exports, makes described first node P and described main output terminal Gout be reset to low level.
In above-described embodiment, first clock signal is the CKL clock signal of high level, second clock signal is the CKB clock signal of high level, and second clock signal is the inverting clock signal of the first clock signal, and the cycle of the first clock signal and second clock signal is half clock period.
Preferably, in circuit as shown in Figure 3, described primary input module 201 comprises switching transistor M3; The grid of described switching transistor M3 is connected with initialize signal STP input end, and the first electrode is connected with high-level control signal DIR1 input end, and the second electrode is connected with described first node P.
Described first output module 202 comprises the first electric capacity C1 and the M4 that pulls up transistor; Wherein, described first electric capacity C1 is connected between described first node P and described main output terminal Gout, the grid of the described M4 of pulling up transistor is connected with described first node P, and the first electrode is connected with second clock signal input part, and the second electrode is connected with described main output terminal Gout.
Described second output module 203 comprises transistor M5; The grid of described transistor M5 is connected with the first clock signal input terminal, and the first electrode is connected with described main output terminal Gout, and the second electrode is connected with low level signal VGL input end.
Described second reseting module 205 comprises the 4th reset transistor M7; The grid of described 4th reset transistor M7 is connected with the main output terminal Gout of next stage shift-register circuit, first Electrode connection of the first electrode and described first reset transistor M1, and the second electrode is connected with low level control signal DIR2 input end.
Drop-down module 206 is also had access between described first node P and described first output module 202; Described drop-down module 206 comprises: pull-down transistor M6 and the second electric capacity C2; Wherein, the grid of described pull-down transistor M6 is connected with described first node P, first electrode is connected with the first end of described second electric capacity C2, second electrode is connected with low level signal VGL input end, and second end of described second electric capacity C2 is connected with the second clock signal input part of described first output module 202.
This embodiment adds the thin film transistor (TFT) M0 used as diode on the basis of above-described embodiment, for receiving the first reset signal, and according to the normal startup of high and low Automatic level control first reseting module of the first reset signal and closedown.That is when the first reset signal is high level, or when receiving the first reset signal of high level, thin film transistor (TFT) M0 is as diode current flow, make the first reset transistor M1, second reset transistor M2 conducting, realize before the switching transistor input initialize signal to every one-level shift register circuit, by the voltage amplitude of first node and main output terminal, the gate drive signal that the shift register circuit of every one-level is produced is not by the impact of the drift of the threshold voltage of thin film transistor (TFT), ensure the driven of shift register and the normal display of display unit, first reset signal is low level, or when the first reset signal of high level disappears, thin film transistor (TFT) M0 ends, make the first reset transistor M1, the second reset transistor M2 ends, first reseting module is resetted terminate, start to make the switching transistor to every one-level shift register circuit to receive input initialize signal, produce for display unit and export gate drive signal.
Embodiment 4
Based on embodiment 2 and embodiment 3, embodiments provide a kind of structure of shift register, as shown in Figure 4.
Shift register comprises the shift register circuit of multi-stage cascade, every one-level shift register circuit produces the display that gate drive signal controls display unit, and the drive singal that the main output terminal being equivalent to one-level shift-register circuit exports controls the unlatching of the grid of display unit one-row pixels unit.In the shift register 401 shown in Fig. 4, the primary input end IN (grid of switching transistor M3) of first order shift register circuit receives initialize signal STP, the primary input end IN of (n+1)th grade of shift register circuit is connected with the main output terminal Gout of n-th grade of shift register circuit, the output signal of every one-level shift register circuit is made to control the unlatching of the primary input module of its next stage shift register circuit, such as, the primary input end IN of the 2nd grade of shift register circuit is connected with the main output terminal Gout of the 1st grade of shift register circuit, the output signal Gout (1) of the 1st grade of shift register circuit is made to control the unlatching of the primary input module of the 2nd grade of shift register circuit.The main output terminal Gout of (n+1)th grade of shift register circuit is connected with the second reset signal input end Gn+1 of n-th grade of shift register circuit, the output signal of every one-level shift register circuit is made to control the unlatching of the second reseting module of its upper level shift register circuit, such as, the main output terminal Gout of the 2nd grade of shift register circuit is connected with the second reset signal input end G2 of the 1st grade of shift register circuit, makes the output signal of the 2nd grade of shift register circuit control the unlatching of the second reseting module of the 1st grade of shift register circuit; Second reset signal input end of afterbody shift register circuit is connected with " END " signal source, for receiving " END " signal, controls the unlatching of the second reseting module of afterbody shift register circuit.Wherein, n be more than or equal to 1 positive integer.
In addition, the shift register of the embodiment of the present invention also should comprise the shift register circuit of odd level and the shift register circuit of even level, for the ease of understanding, only give the sketch of shift register structure in Fig. 4, the CONSTRUCTED SPECIFICATION of shift register determines according to the detail of device.Every one-level shift register circuit is except being connected with the first clock signal C KL, second clock signal CLKB, also should be connected with low level VGL signal source, high level DIR1 control signal source, low level control DIR2 signal source, the first reset RESET signal source, in Fig. 4, omit the connection of above-mentioned signal.
Embodiment 5
Based on a kind of shift register that above-described embodiment 2 provides, and a kind of shift register working timing figure as shown in Figure 5, embodiments provide a kind of driving method of every one-level shift register circuit of shift register, the method comprises:
First reseting stage, level signal generation phase, low level drive singal export the stage, high level drive singal exports stage, the second reseting stage;
At the first reseting stage, the first reset signal RESET is inputted at described reset signal input end, cause the first reset transistor M1 of described first reseting module 204, the second reset transistor M2 conducting, the voltage amplitude of described first node P and described main output terminal Gout is low level, and namely first node P and described main output terminal Gout is all connected with low level VGL signal source.Wherein, if the first reset transistor M1, the second reset transistor M2 are N-type metal-oxide-semiconductor, then the described first reset signal RESET of the first reseting stage input is high level.The present embodiment is N-type metal-oxide-semiconductor for all thin film transistor (TFT)s, is described each driving stage following.
At level signal generation phase, at described primary input end input initialize signal, cause described first node P to be high level, the first reset transistor M1 of described first reseting module and the grid of the second reset transistor M2 are low level; Wherein, if shift register circuit is first order shift register circuit, then initialize signal STP is original trigger signal, if the shift register circuit shift register circuit that to be the second level or the second level later, then initialize signal is the high level signal that upper level shift register circuit output terminal exports.
Concrete, at level signal generation phase, because of the input of high level initialize signal, first node P is made to be high level, cause switching transistor M3 conducting, the high-level control signal DIR1 of high-level control signal input end input, first electrode of described switching transistor M3 is caused to be high level, the described M4 conducting that pulls up transistor, described pull-down transistor M6 conducting, the conducting of described pull-down transistor M6 causes the first reset transistor M1 of described first reseting module and the grid of the second reset transistor M2 to be low level, namely the first reset transistor M1 is connected with low level VGL signal source with the second reset transistor M2.
Export the stage at low level drive singal, at the first clock signal clk of described first clock signal input terminal input high level, cause the second output module 203 to described main output terminal Gout output low level drive singal;
Concrete, at the first clock signal clk of described first clock signal input terminal input high level, at the first clock signal clk B of described second clock signal input part input low level, cause the transistor M5 conducting of described second output module 203, make the gate drive signal of described main output terminal Gout output low level, namely main output terminal Gout is connected with low level VGL signal source.
Export the stage at high level drive singal, at the second clock signal CLKB of described second clock signal input part input high level, cause the first output module 201 to export high level drive singal to described main output terminal Gout;
Concrete, at the first clock signal clk of described first clock signal input terminal input low level, the transistor M5 of the second output module 203 is caused to end, at the second clock signal CLKB of described second clock signal input part input high level, described main output terminal Gout is caused to export the gate drive signal of high level.
At the second reseting stage, the high level second reset signal Gn+1 that the main output terminal that described second reseting module 205 receives next stage shift-register circuit exports, described first node P is caused to be reset to low level, the second clock signal CLKB of the first reset transistor M1 of described first reseting module 204 and the grid input high level of the second reset transistor M2, causes described main output terminal Gout to be reset to low level;
Concrete, the grid of the 4th reset transistor M7 of described second reseting module 205 receives the high level second reset signal Gn+1 of the main output terminal output of next stage shift-register circuit, cause the 4th reset transistor M7 conducting, the low level control signal DIR2 that the conducting of the 4th reset transistor M7 makes low level control signal input part input is connected with first node P, first node P is made to be reset to low level, described pull-down transistor M6 is caused to end, the second clock signal CLKB of high level transfers to the first reset transistor M1 of the first reseting module 204 and the grid of the second reset transistor M2 through described second electric capacity C2, auxiliary reset module, make the first reset transistor M1 and the second reset transistor M2 conducting, the conducting of the first reset transistor M1 and the second reset transistor M2 causes Gout to be reset to low level, namely main output terminal Gout is connected with low level VGL signal source.
In above-described embodiment, at the first reseting stage, in the first reset signal of the high level of reset signal input end input, trigger the normal startup of the first reseting module, realize after making the first reset transistor M1 and the second reset transistor M2 conducting before the switching transistor input initialize signal to every one-level shift register circuit, by the voltage amplitude of first node and main output terminal, the gate drive signal that the shift register circuit of every one-level is produced is not by the impact of the drift of the threshold voltage of thin film transistor (TFT), ensure the driven of shift register and the normal display of display unit.Relative to prior art, when not increasing thin film transistor (TFT), solving the thin film transistor (TFT) in the gate drive apparatus existed in prior art can produce abnormal because of the drift of threshold voltage to the driving of display unit, cause the problem of the abnormal show of display unit.
In above-described embodiment, at the second reseting stage, high level second reset signal that the main output terminal that second reseting module receives next stage shift-register circuit exports, trigger the second reseting module to start, the first reset transistor M1 that first reseting module in every one-level shift register circuit is comprised and the second reset transistor M2, realize output terminal output high level drive singal when the shift register circuit of next stage and the reset signal fed back to this shift register circuit time, by the voltage amplitude of first node and main output terminal, no longer high level drive singal is exported to the grid of display unit to make this grade of shift register circuit.
Embodiment 6
Based on a kind of shift register that above-described embodiment 3 provides, and a kind of shift register working timing figure as shown in Figure 5, embodiments provide a kind of driving method of every one-level shift register circuit of shift register, the method comprises:
First reseting stage, level signal generation phase, low level drive singal export the stage, high level drive singal exports stage, the second reseting stage;
Preferably, at the first reseting stage, the first reset signal RESET is inputted at described reset signal input end, cause the 3rd reset transistor M0 of described first reseting module 204, the first reset transistor M1, the second reset transistor M2 conducting, cause the voltage amplitude of described first node P and described main output terminal to be low level;
Concrete, at the first reseting stage, at the first reset signal RESET of described reset signal input end input high level, cause the 3rd reset transistor M0 of described first reseting module 204 as diode current flow, the conducting of the 3rd reset transistor M0 makes high level reset signal transfer to the first reset transistor M1, the grid of the second reset transistor M2, cause the first reset transistor M1, second reset transistor M2 conducting, first reset transistor M1, after second reset transistor M2 conducting, the voltage amplitude of described first node P and described main output terminal Gout is low level, namely first node P and described main output terminal Gout is all connected with low level VGL signal source.
The driving process of the level signal generation phase in the present embodiment, low level drive singal output stage, high level drive singal output stage, the second reseting stage, specifically see embodiment 3, is not repeated herein.
In above-described embodiment, at the first reseting stage, in the first reset signal of the high level of reset signal input end input, make the thin film transistor (TFT) M0 conducting used as diode, trigger the normal startup of the first reseting module, realize after making the first reset transistor M1 and the second reset transistor M2 conducting before the switching transistor input initialize signal to every one-level shift register circuit, by the voltage amplitude of first node and main output terminal, the gate drive signal that the shift register circuit of every one-level is produced is not by the impact of the drift of the threshold voltage of thin film transistor (TFT), ensure the driven of shift register and the normal display of display unit.
Although describe the preferred embodiments of the present invention, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of the scope of the invention.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.

Claims (10)

1. a shift register, comprises the shift register circuit of multi-stage cascade, it is characterized in that, every one-level shift register circuit, comprising:
Main output terminal, for output drive signal;
Primary input module, for receiving initialize signal;
First output module, is connected between described primary input module and described main output terminal, and for exporting high level drive singal according to second clock signal, the node between described primary input module and described first output module is first node;
Second output module, is connected with described main output terminal, for according to the first clock signal output low level drive singal;
Also comprise:
First reseting module, for the first reset signal inputted according to reset signal input end, makes described first node and described main output terminal be reset to low level;
Wherein, described first reseting module comprises: the first reset transistor M1, the second reset transistor M2; The grid of described first reset transistor M1, the grid of described second reset transistor M2 are all connected with described reset signal input end, first electrode of described first reset transistor M1 is connected with described first node, and first electrode of described second reset transistor M2 is connected with described main output terminal; Second electrode of described first reset transistor M1, second electrode of described second reset transistor M2 are all connected with low level signal input end;
Second reseting module, is connected between described first node and described first reseting module, for receiving the second reset signal that next stage shift-register circuit exports, makes described first node and described main output terminal be reset to low level.
2. shift register as claimed in claim 1, it is characterized in that, described first reseting module also comprises: the 3rd reset transistor M0;
Reset signal input end described in the grid of described 3rd reset transistor M0, the first Electrode connection, the grid of the first reset transistor M1 described in the second Electrode connection, the grid of described second reset transistor M2.
3. shift register as claimed in claim 1 or 2, it is characterized in that, described second reseting module comprises the 4th reset transistor M7;
The described grid of the 4th reset transistor M7 is connected with the main output terminal of next stage shift-register circuit, and first Electrode connection of the first electrode and described first reset transistor M1, the second electrode is connected with low level control signal input part.
4. shift register as claimed in claim 1 or 2, it is characterized in that, described primary input module comprises switching transistor M3;
The grid of described switching transistor M3 is connected with initialize signal input end, and the first electrode is connected with high-level control signal input end, and the second electrode is connected with described first node.
5. shift register as claimed in claim 1 or 2, is characterized in that, described first output module comprises the first electric capacity C1 and the M4 that pulls up transistor;
Wherein, described first electric capacity C1 is connected between described first node and described main output terminal, described in the pull up transistor grid of M4 be connected with described first node, the first electrode is connected with second clock signal input part, and the second electrode is connected with described main output terminal.
6. shift register as claimed in claim 1 or 2, it is characterized in that, described second output module comprises transistor M5;
The grid of described transistor M5 is connected with the first clock signal input terminal, and the first electrode is connected with described main output terminal, and the second electrode is connected with low level signal input end.
7. shift register as claimed in claim 1 or 2, is characterized in that, between described first node and described first output module, also have access to drop-down module; Described drop-down module comprises: pull-down transistor M6 and the second electric capacity C2;
Wherein, the grid of described pull-down transistor M6 is connected with described first node, first electrode is connected with the first end of described second electric capacity C2, second electrode is connected with low level signal input end, and second end of described second electric capacity C2 is connected with the second clock signal input part of described first output module.
8. be applied to a driving method for every one-level shift register circuit of the shift register as described in any one of claim 1-7, it is characterized in that, described every one-level shift register circuit comprises the first reseting stage;
At the first reseting stage, the first reset signal is inputted at described reset signal input end, cause the first reset transistor M1 of described first reseting module, the second reset transistor M2 conducting, the voltage amplitude of described first node and described main output terminal is low level.
9. driving method as claimed in claim 8, is characterized in that,
At the first reseting stage, the first reset signal is inputted at described reset signal input end, cause the 3rd reset transistor M0 of described first reseting module, the first reset transistor M1, the second reset transistor M2 conducting, cause the voltage amplitude of described first node and described main output terminal to be low level.
10. driving method as claimed in claim 8 or 9, it is characterized in that, described every one-level shift register circuit also comprises: level signal generation phase, low level drive singal export the stage, high level drive singal exports stage and the second reseting stage;
At level signal generation phase, at described primary input end input initialize signal, cause described first node to be high level, the first reset transistor M1 of described first reseting module and the grid of the second reset transistor M2 are low level;
Export the stage at low level drive singal, in the first clock signal of described first clock signal input terminal input high level, cause the second output module to described main output terminal output low level drive singal;
Export the stage at high level drive singal, at the second clock signal of described second clock signal input part input high level, cause the first output module to export high level drive singal to described main output terminal;
At the second reseting stage, high level second reset signal that the main output terminal that described second reseting module receives next stage shift-register circuit exports, described first node is caused to be reset to low level, the second clock signal of the first reset transistor M1 of described first reseting module and the grid input high level of the second reset transistor M2, causes described main output terminal to be reset to low level.
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Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104809985A (en) * 2015-05-15 2015-07-29 京东方科技集团股份有限公司 Shifting register unit as well as drive method thereof and grid electrode drive circuit
CN105448259A (en) * 2015-12-25 2016-03-30 上海中航光电子有限公司 Gate driver and display panel
CN105448258A (en) * 2015-12-25 2016-03-30 上海中航光电子有限公司 Gate driver and display panel
CN105590601A (en) * 2015-12-18 2016-05-18 上海中航光电子有限公司 Driving circuit, array substrate, and display device
CN106024065A (en) * 2016-05-18 2016-10-12 上海天马微电子有限公司 Shifting register, gate drive circuit, array substrate and display device
CN106128352A (en) * 2016-09-05 2016-11-16 京东方科技集团股份有限公司 GOA unit, driving method, GOA circuit and display device
CN107123390A (en) * 2017-07-04 2017-09-01 京东方科技集团股份有限公司 A kind of shift register, its driving method, gate driving circuit and display device
WO2017211149A1 (en) * 2016-06-06 2017-12-14 京东方科技集团股份有限公司 Shift register, drive method thereof, and gate drive device
CN107731180A (en) * 2017-09-12 2018-02-23 昆山龙腾光电有限公司 Gate driving circuit
CN108062935A (en) * 2017-12-08 2018-05-22 昆山龙腾光电有限公司 A kind of gate driving circuit and display device
US10083658B2 (en) 2015-09-10 2018-09-25 Boe Technology Group Co., Ltd. Pixel circuits with a compensation module and drive methods thereof, and related devices
WO2018171133A1 (en) * 2017-03-20 2018-09-27 京东方科技集团股份有限公司 Shift register unit, gate driving circuit, and driving method
WO2018196317A1 (en) * 2017-04-27 2018-11-01 京东方科技集团股份有限公司 Shift register unit, shift register circuit, drive method, and display device
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CN109994064A (en) * 2018-01-02 2019-07-09 京东方科技集团股份有限公司 Shift register cell, gate driving circuit and its driving method and display device
CN110738953A (en) * 2018-07-20 2020-01-31 深超光电(深圳)有限公司 Gate driver and display device having the same
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050053808A (en) * 2003-12-03 2005-06-10 삼성전자주식회사 Display device, and driving apparatus thereof
US20090135991A1 (en) * 2007-11-26 2009-05-28 Chung-Chun Chen Pre-charge circuit and shift register with the same
CN102654986A (en) * 2011-11-25 2012-09-05 京东方科技集团股份有限公司 Shift register electrode, grid electrode driver, array substrate and display device
CN102682689A (en) * 2012-04-13 2012-09-19 京东方科技集团股份有限公司 Shift register, grid drive circuit and display device
CN103456365A (en) * 2013-08-30 2013-12-18 合肥京东方光电科技有限公司 Shift register unit, shift register and display device
CN103489483A (en) * 2013-09-02 2014-01-01 合肥京东方光电科技有限公司 Shift register unit circuit, shift register, array substrate and display device
CN103971628A (en) * 2014-04-21 2014-08-06 京东方科技集团股份有限公司 Shift register unit, gate driving circuit and display device
CN103996370A (en) * 2014-05-30 2014-08-20 京东方科技集团股份有限公司 Shifting register unit, grid drive circuit, display device and drive method

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050053808A (en) * 2003-12-03 2005-06-10 삼성전자주식회사 Display device, and driving apparatus thereof
US20090135991A1 (en) * 2007-11-26 2009-05-28 Chung-Chun Chen Pre-charge circuit and shift register with the same
CN102654986A (en) * 2011-11-25 2012-09-05 京东方科技集团股份有限公司 Shift register electrode, grid electrode driver, array substrate and display device
CN102682689A (en) * 2012-04-13 2012-09-19 京东方科技集团股份有限公司 Shift register, grid drive circuit and display device
CN103456365A (en) * 2013-08-30 2013-12-18 合肥京东方光电科技有限公司 Shift register unit, shift register and display device
CN103489483A (en) * 2013-09-02 2014-01-01 合肥京东方光电科技有限公司 Shift register unit circuit, shift register, array substrate and display device
CN103971628A (en) * 2014-04-21 2014-08-06 京东方科技集团股份有限公司 Shift register unit, gate driving circuit and display device
CN103996370A (en) * 2014-05-30 2014-08-20 京东方科技集团股份有限公司 Shifting register unit, grid drive circuit, display device and drive method

Cited By (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016184027A1 (en) * 2015-05-15 2016-11-24 京东方科技集团股份有限公司 Shift register unit, driving method therefor and grid electrode driving circuit thereof
US10134339B2 (en) 2015-05-15 2018-11-20 Boe Technology Group Co., Ltd. Shift register unit and driving method thereof, gate driving circuit
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US10083658B2 (en) 2015-09-10 2018-09-25 Boe Technology Group Co., Ltd. Pixel circuits with a compensation module and drive methods thereof, and related devices
US10643561B2 (en) 2015-12-18 2020-05-05 Shanghai Avic Opto Electronics Co., Ltd. Driving circuit, array substrate and display device
CN105590601A (en) * 2015-12-18 2016-05-18 上海中航光电子有限公司 Driving circuit, array substrate, and display device
CN105590601B (en) * 2015-12-18 2018-06-26 上海中航光电子有限公司 Driving circuit, array substrate and display device
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CN105448258A (en) * 2015-12-25 2016-03-30 上海中航光电子有限公司 Gate driver and display panel
CN105448259A (en) * 2015-12-25 2016-03-30 上海中航光电子有限公司 Gate driver and display panel
CN106024065A (en) * 2016-05-18 2016-10-12 上海天马微电子有限公司 Shifting register, gate drive circuit, array substrate and display device
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WO2017211149A1 (en) * 2016-06-06 2017-12-14 京东方科技集团股份有限公司 Shift register, drive method thereof, and gate drive device
US10095058B2 (en) 2016-06-06 2018-10-09 Boe Technology Group Co., Ltd. Shift register and driving method thereof, gate driving device
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WO2018171133A1 (en) * 2017-03-20 2018-09-27 京东方科技集团股份有限公司 Shift register unit, gate driving circuit, and driving method
US10803823B2 (en) 2017-03-20 2020-10-13 Boe Technology Group Co., Ltd. Shift register unit, gate driving circuit, and driving method
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