CN112820227B

CN112820227B - Gate driving circuit

Info

Publication number: CN112820227B
Application number: CN201911130247.4A
Authority: CN
Inventors: 陈逸轩; 叶政谚; 赵广雄; 康沐楷
Original assignee: Hannstar Display Corp
Current assignee: Hannstar Display Corp
Priority date: 2019-11-18
Filing date: 2019-11-18
Publication date: 2024-05-07
Anticipated expiration: 2039-11-18
Also published as: CN112820227A

Abstract

The invention discloses a grid driving circuit for driving a display panel, which comprises a multi-stage shift register for sequentially outputting scanning signals to the display panel. The first-stage shift register comprises a plurality of transistors arranged side by side along a first direction, each transistor comprises a source electrode and a drain electrode, and the source electrode or the drain electrode comprises a main electrode and a plurality of branch electrodes connected with the main electrode. The branch electrodes of the transistors extend along the second direction, and the first direction and the second direction are not parallel.

Description

Gate driving circuit

Technical Field

The present invention relates to a gate driving circuit, and more particularly, to a gate driving circuit capable of reducing occupied space in a peripheral region.

Background

The display panel is composed of two substrates, a plurality of film layers arranged between the two substrates and various electronic components, so as to achieve the function of displaying pictures. Because the display panel has the characteristics of light and thin profile, low power consumption, no radiation pollution, etc., it has been widely used in various portable or wearable electronic products such as notebook computers (notebook), smart phones (smart phones), watches, and car displays, etc., to provide more convenient information transmission and display.

In order to meet the requirements, the frame width of the display panel is continuously reduced, so that the space for arranging the circuits in the peripheral area is reduced. Therefore, the structure of the gate driving circuit must be simplified to arrange the output stage thin film transistors of a sufficiently large size in a limited space, thereby avoiding the occurrence of insufficient voltage thrust when driving the gate lines.

Disclosure of Invention

The invention provides a gate driving circuit and a driving method of a display panel to solve the above technical problems, so as to reduce the occupied space of the gate driving circuit in the peripheral area and further reduce the frame width of the display panel.

In order to solve the above-mentioned problems, the present invention provides a gate driving circuit for driving a display panel, the gate driving circuit includes a multi-stage shift register for sequentially outputting a plurality of scan signals to the display panel, wherein one stage of the shift register includes a plurality of transistors arranged side by side along a first direction, each transistor includes a source electrode and a drain electrode, and the source electrode or the drain electrode includes a main electrode and a plurality of branch electrodes connected to the main electrode, wherein the branch electrodes of the transistors extend along a second direction, and the first direction and the second direction are not parallel.

In the gate driving circuit of the present invention, the branch electrodes of the plurality of transistors in the shift register are all extended along the same direction (e.g. the second direction), so that the transistors can be more closely arranged, for example, at least three transistors can be arranged at one side of the second capacitor. Therefore, the space occupied by the shift register can be reduced, and the width of the peripheral area can be further reduced. On the other hand, the light transmission area in the shift register can be increased to further help the frame glue to be solidified. In addition, the transistors can be arranged side by side along the first direction, so that the complexity of electric connection between the transistors and the signal lines can be reduced, the capacitive load caused by mutual crossing of the signal lines is reduced, and the space occupied by the signal lines is reduced.

Drawings

Fig. 1 is a schematic view of a display panel according to a first embodiment of the invention.

Fig. 2 is a schematic diagram of a gate driving circuit according to a first embodiment of the present invention.

Fig. 3 is an equivalent circuit diagram of an i-th stage shift register in the gate driving circuit of fig. 2.

Fig. 4 is a circuit layout diagram of a shift register according to a first embodiment of the present invention.

Fig. 5 is a partially enlarged schematic view of a display panel according to a first embodiment of the invention.

Fig. 6 is a circuit layout diagram of a shift register according to a second embodiment of the present invention.

Wherein reference numerals are as follows:

10. Display panel

100. Substrate board

102. 1021, 1022 Gate drive circuit

104. Control integrated circuit

106. Wiring

108. Pre-charging unit

10R region

110. Pull-up unit

112. Pull-down unit

114. A first conductive layer

116. Second conductive layer

118. Semiconductor layer

120. Frame glue

A1, A2 area

A3 Sum of areas

BD boundary

BE branch electrode

C1-C8 patterned semiconductor layer

CL1-CL8 clock signal line

CLK1 first clock signal

CLK2 second clock signal

CP1 first capacitor

CP2 second capacitor

CS1-CS8 clock signals

D1 First direction

D1-D8 drain electrode

DR display area

E1, E2 side

EL end signal line

ES end signal

G1-G8 grid electrode

IL initial signal line

IN1 first input signal

IN2 second input signal

IS initiation signal

M1-M8 transistors

ME main electrode

OUT (i), OUT (i+1), OUT (i-1), scanning signals OUT (1) -OUT (N)

P1 first part

P2 second part

P3 third part

PR peripheral region

S1-S8 source electrode

SG1-SG11 signal line

SL scan line

SP sub-pixel

SR (1) -SR (N), SR (i), SR shift register

VGL reference potential

X1 first node

X2 second node

Detailed Description

The following description sets forth the preferred embodiments of the invention and, together with the drawings, provides further details of the invention and its intended advantages, as will be apparent to those skilled in the art. It should be noted that the drawings are simplified schematic diagrams, and thus only show components and combinations related to the present invention, so as to provide a clearer description of the basic architecture or implementation of the present invention, and actual components and arrangements may be more complex. In addition, for convenience of explanation, the components shown in the drawings of the present invention are not drawn in the same scale as the number, shape, size, etc. of actual implementations, and the detailed proportion thereof may be adjusted according to the design requirements.

It should be understood that although the terms first, second, and third … may be used to describe various components, the components are not limited by this term. This term is used only to distinguish a single component from other components within the specification. The same terms may not be used in the claims but instead the first, second, third … are substituted in the order in which the elements were recited in the claims. Thus, in the following description, a first component may be a second component in the claims.

Fig. 1 is a schematic diagram of a display panel according to a first embodiment of the invention. The display panel 10 of the present invention may be any of various types of display panels, such as a liquid crystal display panel, an electrophoretic display panel, an organic light emitting display panel or a micro light emitting diode display panel, but is not limited thereto. As shown in fig. 1, the substrate 100 of the display panel 10 has a surface including a display region DR and a peripheral region PR disposed at least one side outside the display region DR. In the present embodiment, the peripheral region PR surrounds the display region DR, but is not limited thereto. The substrate 100 may be a hard substrate such as a glass substrate, a plastic substrate, a quartz substrate or a sapphire substrate, or may be a flexible substrate including a Polyimide (PI) material or a polyethylene terephthalate (polyethylene terephthalate, PET) material, for example, but not limited thereto. The display panel 10 includes a plurality of scan lines SL disposed in the display region DR, and the scan lines SL may extend into the display region DR from the peripheral region PR, for example, and may be electrically connected to sub-pixels in the display region DR.

The display panel 10 may include at least one gate driving circuit (GATE DRIVER circuits) 102 disposed in the peripheral region PR and disposed on one side of the display region DR. The gate driving circuit 102 is electrically connected to the scan line SL, and can transmit a scan signal to the scan line SL to drive the sub-pixels in the display region DR. In addition, the gate driving circuit 102 may be electrically connected to at least one control integrated circuit (INTEGRATED CIRCUIT, IC) 104, and the control integrated circuit 104 may transmit control signals (e.g., clock signals, start signals, and end signals) to the gate driving circuit 102. The control integrated circuit 104 may also be disposed in the peripheral region PR, but is not limited thereto. In the present embodiment, the display panel 10 includes two gate driving circuits 1021 and 1022 respectively disposed on two sides of the display region DR, but the number and disposition of the gate driving circuits 108 and the control integrated circuits 104 are not limited to the above. As shown in fig. 1, one of the adjacent two scanning lines SL may be electrically connected to the gate driving circuit 1021, and the other may be electrically connected to the gate driving circuit 1022.

In this embodiment, each row of sub-pixels in the display region DR may be electrically connected to two scan lines SL, a portion of the sub-pixels in the sub-pixel row may be electrically connected to the gate driving circuit 1021 through one of the scan lines SL, and another portion of the sub-pixels in the sub-pixel row may be electrically connected to the gate driving circuit 1022 through the other of the scan lines SL. For example, when the display panel 10 has 1440 columns of sub-pixels, the display panel 10 may have 2880 scan lines SL, wherein 1440 scan lines SL may be electrically connected to the gate driving circuit 1021, and another 1440 scan lines SL may be electrically connected to the gate driving circuit 1022, but not limited thereto.

The gate driving circuits 1021 and 1022 are, but not limited to, array substrate row driving (GOA) circuit structures. In some embodiments, the gate driving circuit 102 may be fabricated as a chip and then disposed on the substrate 100, or disposed on a flexible or hard circuit board and then electrically connected to a connection pad on the substrate 100, and the connection pad is electrically connected to the scan line SL. For example, the gate driving circuit 102 may include a plurality of control signal lines (e.g., a clock signal line, a start signal line, and an end signal line) electrically connected to the control integrated circuit 104 through the trace 106, so that the control integrated circuit 104 may transmit control signals (e.g., a clock signal, a start signal, and an end signal) to the gate driving circuit 102. The components and structures of the gate driving circuit 102 will be described in detail below.

Referring to fig. 2, which is a schematic diagram of a gate driving circuit according to a first embodiment of the present invention, the gate driving circuit 102 of the present embodiment includes clock signal lines CL1-CL8, a start signal line IL, an end signal line EL, and 1 st to nth shift registers SR (1) -SR (N), wherein N is a positive integer greater than or equal to 9, but is not limited thereto. The clock signal lines CL1-CL8 provide clock signals CS1-CS8 to corresponding shift registers SR (1) -SR (N). The number of clock signal lines of the present invention is not limited to 8. In other embodiments, the number of clock signal lines may be 4 or 6, but not limited thereto. The 1 st to nth shift registers SR (1) -SR (N) may be Array substrate row driving (GOA) circuit structures.

In addition, the start signal line IL may provide a start signal IS to the 1 st stage shift register SR (1), and the end signal line EL may provide an end signal ES to the nth stage shift register SR (N). The gate driving circuit 102 may be applied to a bidirectional scan driving. The gate driving circuit 102 of the present embodiment can be applied to forward scan driving, but in some embodiments, the gate driving circuit 102 can also be applied to backward scan driving. When the gate driving circuit 102 is applied to the inverse scan driving, the nth stage shift register SR (N) may receive the start signal, and the 1 st stage shift register SR (1) may receive the end signal, but not limited thereto. The clock signal lines CL1-CL8, the start signal line IL, and the end signal line EL may be coupled to one or more chips, i.e., the clock signals CS1-CS8, the start signal IS, and the end signal ES may be provided from one or more chips, such as a driving chip and/or a timing control chip, but not limited thereto.

Please refer to fig. 3, which is an equivalent circuit diagram of the i-th stage shift register in the gate driving circuit of fig. 2. The i-th stage (i is a positive integer greater than or equal to 1, for example, a positive integer from 1 to N) shift register SR (i) includes a precharge unit 108, a pull-up unit 110 and a pull-down unit 112, wherein one ends of the precharge unit 108 and the pull-up unit 110 are coupled to a first node X1, and a second node X2 at the other end of the pull-up unit 110 can output the i-th stage scan signal OUT (i) to the corresponding scan line SL. The precharge unit 108 receives a first input signal IN1 and a second input signal IN2, and controls the potential of the first node X1 according to the first input signal IN1 or the second input signal IN 2. The precharge unit 108 includes a transistor M1 (or referred to as a second transistor) and a transistor M2 (or referred to as a third transistor). IN the present embodiment, the gate driving circuit 102 is a bi-directional scanning driving circuit, and IN the shift registers SR (1) -SR (N), a first terminal of the transistor M1 receives the first input signal IN1, a gate of the transistor M1 is coupled to the first terminal of the transistor M1, and a second terminal of the transistor M1 is coupled to the first node X1. A first terminal of the transistor M2 receives the second input signal IN2, a gate of the transistor M2 is coupled to the first terminal of the transistor M2, and a second terminal of the transistor M2 is coupled to the first node X1. Herein, the "first end" and "second end" of the thin film transistor refer to the source and drain of the thin film transistor, respectively, or refer to the drain and source of the thin film transistor, respectively. In addition, a gate driving circuit for unidirectional scanning may be included in some embodiments, in which case the setting transistor M2 may be omitted in these shift registers.

If the shift register SR (i) IS a1 st stage shift register (i.e., i IS 1), the first input signal IN1 IS the start signal IS, and the second input signal IN2 IS the scan signal OUT (i+1) (i.e., the 2 nd stage scan signal OUT (2)) output from the (i+1) th stage shift register SR (i+1). If the shift register SR (i) is any one of the shift registers from the 2 nd stage to the (N-1) stage (i.e., i is any positive integer from 2 to (N-1)), the first input signal IN1 and the second input signal IN2 are the (i-1) th stage scan signal OUT (i-1) output by the (i-1) th stage shift register SR (i-1) and the (i+1) th stage scan signal OUT (i+1) output by the (i+1) th stage shift register SR (i+1), respectively. If the shift register SR (i) is an N-th shift register (i.e., i is N), the first input signal IN1 is the scan signal OUT (i-1) output by the (i-1) -th shift register SR (i.e., the (N-1) -th scan signal OUT (N-1)), and the second input signal IN2 is the end signal ES. Thereby, the shift registers in the gate driving circuit 102 can sequentially output the scan signals OUT (1) -OUT (N) from the shift register SR (1) to the shift register SR (N) to the scan lines SL of the display panel 10. Note that, when the gate driving circuit 102 IS forward scanning, IS a start signal and ES IS an end signal; when the gate driving circuit 102 IS in the reverse scan mode, ES IS a start signal and IS an end signal.

The pull-up unit 110 and the precharge unit 108 are coupled to the first node X1, and receive a first clock signal CLK1, and output a scan signal OUT (i) from the second node X2 according to the potential of the first node X1 and the first clock signal CLK1, wherein the first clock signal CLK1 is any one of the clock signals CS1-CS 8. In an embodiment where N is a multiple of 8, if i is 1, 9, …, (N-7), then the first clock signal CLK1 is the clock signal CS1; if i is 2, 10, …, (N-6), the first clock signal CLK1 is a clock signal CS2; if i is 3, 11, …, (N-5), the first clock signal CLK1 is a clock signal CS3; if i is 4, 12, …, (N-4), then the first clock signal CLK1 is a clock signal CS4; if i is 5, 13, …, (N-3), the first clock signal CLK1 is a clock signal CS5; if i is 6, 14, …, (N-2), the first clock signal CLK1 is a clock signal CS6; if i is 7, 15, …, (N-1), then the first clock signal CLK1 is a clock signal CS7; if i is 8, 16, …, N, the first clock signal CLK1 is a clock signal CS8.

The pull-up unit 110 includes a transistor M4 (or referred to as a first transistor) and a first capacitor CP1. A gate of the transistor M4 is coupled to the first node X1, a first terminal of the transistor M4 receives the first clock signal CLK1, and a second terminal of the transistor M4 is coupled to the second node X2 and outputs the scan signal OUT (i). The transistor M4 may be electrically connected to one scan line SL in the display panel 10, and the transistor M4 may output the scan signal OUT (i) to the scan line SL. A first terminal of the first capacitor CP1 is coupled to the first node X1 and the gate of the transistor M4, and a second terminal of the first capacitor CP1 is coupled to the second node X2 and the second terminal of the transistor M4.

As shown in fig. 3, one ends of the precharge unit 108, the pull-up unit 110, and the pull-down unit 112 are coupled to the first node X1, and the other ends of the pull-up unit 110 and the pull-down unit 112 are coupled to the second node X2. The pull-down unit 112 includes a second capacitor CP2, a transistor M3 (or referred to as an eighth transistor), a transistor M5 (or referred to as a fourth transistor), a transistor M6 (or referred to as a fifth transistor), a transistor M7 (or referred to as a sixth transistor), and a transistor M8 (or referred to as a seventh transistor). The transistors M1 to M8 of the present embodiment may be, for example, thin film transistors. A gate of the transistor M3 receives a second clock signal CLK2, a first terminal of the transistor M3 receives a reference potential VGL, and a second terminal of the transistor M3 is coupled to the first node X1. A first terminal of the second capacitor CP2 receives the first clock signal CLK1. A gate of the transistor M5 is coupled to the first node X1, a first terminal of the transistor M5 receives the reference voltage VGL, and a second terminal of the transistor M5 is coupled to a second terminal of the second capacitor CP 2. A gate of the transistor M6 is coupled to the second terminal of the second capacitor CP2, a first terminal of the transistor M6 receives the reference voltage VGL, and a second terminal of the transistor M6 is coupled to the first node X1. A gate of the transistor M7 is coupled to the second terminal of the second capacitor CP2, a first terminal of the transistor M7 receives the reference potential VGL, and a second terminal of the transistor M7 is coupled to the second node X2. A gate of the transistor M8 receives the second clock signal CLK2, a first terminal of the transistor M8 receives the reference voltage VGL, and a second terminal of the transistor M8 is coupled to the second node X2.

For example, the reference Voltage VGL may be a Gate Low Voltage (VGL), but is not limited thereto. The second clock signal CLK2 is any one of the clock signals CS1-CS 8. Further, the start time of transfer of the second clock signal CLK2 is after the end time of transfer of the first clock signal CLK 1. In an embodiment where N is a multiple of 8, if i is 1, 9, …, (N-7), then the second clock signal CLK2 is the clock signal CS6; if i is 2, 10, …, (N-6), the second clock signal CLK2 is a clock signal CS7; if i is 3, 11, …, (N-5), the second clock signal CLK2 is a clock signal CS8; if i is 4, 12, …, (N-4), the second clock signal CLK2 is a clock signal CS1; if i is 5, 13, …, (N-3), the second clock signal CLK2 is a clock signal CS2; if i is 6, 14, …, (N-2), the second clock signal CLK2 is a clock signal CS3; if i is 7, 15, …, (N-1), the second clock signal CLK2 is a clock signal CS4; if i is 8, 16, …, N, the second clock signal CLK2 is a clock signal CS5, but not limited thereto.

In some gate driving circuits, each stage of shift register is electrically connected to the first two stages of shift registers and/or the last two stages of shift registers. In this case, the number of connection wires between the shift registers of different stages or the number of times that mutually crossing wires is required is large. However, in the gate driving circuit 102 of the present embodiment, as shown in fig. 2 and 3, each stage of the shift register SR (i) is electrically connected to the previous stage of the shift register SR (i-1) and/or the next stage of the shift register SR (i+1), or each stage of the shift register SR (i) receives the previous stage of the scan signal OUT (i-1) and/or the next stage of the scan signal OUT (i+1). Therefore, in the gate driving circuit 102 of the present embodiment, the number of connection wires between different stages of shift registers or the number of times of crossing wires is reduced, so that the wiring of the connection wires is simpler, or the space occupied by the connection wires can be reduced, and the width of the peripheral region PR can be further reduced.

In addition, in some gate driving circuits, each stage of shift register may include thirteen thin film transistors. However, each stage of the shift register SR (i) of the present embodiment includes eight thin film transistors. Therefore, the space occupied by the gate driving circuit 102 of the present embodiment is relatively small, so that the width of the peripheral region PR can be reduced. On the other hand, in the display panel, since the number of shift registers is larger than that of a general display panel, the space condition in which each shift register is disposed in the peripheral region PR is more severe. However, since the number of thin film transistors and the occupied area of the shift register of the present embodiment are small, the output stage thin film transistor with a large size (such as the channel width (CHANNEL WIDTH)) can be provided, so that the shift register can be ensured to have enough output voltage to turn on the thin film transistor of the pixel and input the correct voltage value.

Fig. 4 is a circuit layout diagram of a shift register according to a first embodiment of the present invention. Fig. 4 may be, for example, but not limited to, one stage of shift register in the gate driving circuit 1022 of fig. 1. For simplifying the drawing, fig. 4 only shows one stage of the shift register SR (i), and only shows the first conductive layer 114, the second conductive layer 116, the semiconductor layer 118, and the sealant 120. In fig. 4, the range of the sealant 120 in a partial region is shown by a thick solid line, however, the range of the sealant 120 in the peripheral region PR is not limited thereto and may extend along the edge of the display panel 10. In the present embodiment, the first conductive layer 114 is disposed between the second conductive layer 116 and the substrate 100, the semiconductor layer 118 is disposed between the first conductive layer 114 and the second conductive layer 116, and the sealant 120 is disposed on the second conductive layer 116, but not limited thereto. The shift register SR (i) is electrically connected to one scan line SL in the display region DR, in other words, the shift register SR (i) can drive the sub-pixels electrically connected to the scan line SL through the corresponding scan line SL. As shown in fig. 4, the shift register SR (i) includes transistors M1 to M8, and each of the transistors M1 to M8 includes a gate electrode, a source electrode, a drain electrode, and a patterned semiconductor layer. The gates G1-G8 in the transistors M1-M8 are formed by the first conductive layer 114, the sources S1-S8 and the drains D1-D8 are formed by the second conductive layer 116, and the patterned semiconductor layers C1-C8 are formed by the semiconductor layer 118. The first conductive layer 114 and the second conductive layer 116 may be metal materials, but are not limited thereto. The semiconductor layer 118 may be amorphous silicon, but is not limited thereto.

As shown in fig. 4, the transistors M1-M8 are arranged substantially side by side along a first direction D1. In addition, the multi-stage shift register may be disposed along a second direction D2, wherein the first direction D1 and the second direction D2 are not parallel. In the present embodiment, the first direction D1 may be perpendicular to the second direction D2, but is not limited thereto. The pull-up unit 110 includes a first portion P1 of transistors M1-M8, and the first portion P1 includes transistor M4. The precharge unit 108 includes a transistor of a second portion P2 of the transistors M1-M8, the transistor of the second portion P2 includes the transistor M1 and the transistor M2, and the transistor M2 is disposed on one side of the transistor M1 in the first direction D1. The pull-down unit 112 includes a transistor of a third portion P3 of the transistors M1-M8, and the transistor of the third portion P3 of the pull-down unit 112 is disposed between the transistor of the first portion P1 of the pull-up unit 110 and the transistor of the second portion P2 of the precharge unit 108 in the first direction D1. The transistors of the third portion P3 include, but are not limited to, a transistor M3, a transistor M5, a transistor M6, a transistor M7, and a transistor M8, which may be a transistor M5, a transistor M6, a transistor M3, a transistor M8, and a transistor M7 in order in the first direction D1.

In fig. 4, at least three transistors M1-M8 are disposed on one side of the second capacitor CP2 in the second direction D2, wherein the second capacitor CP2 has a side E1 and a side E2 in the first direction D1, and the at least three transistors are disposed within a range formed by extending the sides E1 and E2 of the second capacitor CP2 along the second direction D2. For example, the transistor M3, the transistor M7 and the transistor M8 are disposed on one side of the second capacitor CP2 in the second direction D2, and the transistor M3, the transistor M7 and the transistor M8 are disposed in a range formed by extending the side E1 and the side E2 of the second capacitor CP2 along the second direction D2. For example, the ratio of the area of the second capacitor CP2 to the area of the transistor M4 is in the range of 0.1 to 0.5, but is not limited thereto. The area A1 of the second capacitor CP2 may be, for example, the area of one electrode formed by the first conductive layer 114 in the second capacitor CP2, or the area of one electrode formed by the second conductive layer 116 in the second capacitor CP2, but not limited thereto. The area A2 of the transistor M4 may be, for example, the area of the gate G4 or the area of the patterned semiconductor layer C4, but is not limited thereto.

In each transistor, the source and the drain have a gate structure. Taking the source electrode S4 of the transistor M4 as an example, the gate structure includes a main electrode ME and a plurality of branch electrodes BE connected to the main electrode ME, and the branch electrodes BE of the source electrode S4 and the drain electrode D4 are alternately arranged with each other, so that the source electrode S4 and the drain electrode D4 form an integrated structure. In the present embodiment, the branch electrodes BE of the transistors M1-M8 can all extend along the second direction D2. The area A2 of the transistor M4 may be, for example, an area of an integrated structure formed by combining the source S4 and the drain D4, but is not limited thereto.

As shown in fig. 4, the signal lines SG1-SG11 may generally extend in the second direction D2. The signal line SG11 may be used for transmitting the reference potential VGL and may be disposed between the transistor M2 and the transistor M7, but is not limited thereto. The signal lines SG1 to SG10 may be disposed at one side of the multistage shift register and electrically connected thereto, the signal line SG1 may be a start signal line IL, the signal line SG2 may be a clock signal line CL8, the signal line SG3 may be a clock signal line CL7, the signal line SG4 may be a clock signal line CL6, the signal line SG5 may be a clock signal line CL5, the signal line SG6 may be a clock signal line CL4, the signal line SG7 may be a clock signal line CL3, the signal line SG8 may be a clock signal line CL2, the signal line SG9 may be a clock signal line CL1, and the signal line SG10 may be a power line (power line), but not limited thereto. For example, the shift register SR (i) of fig. 4 may be electrically connected to the signal line SG2 and the signal line SG7, but is not limited thereto. In the present embodiment, the width of each signal line may be, for example, about 11 μm, but not limited thereto. In addition, the ratio of the sum of areas A3 of the plurality of signal lines SG1-SG10 corresponding to the one stage shift register SR (i) to the area A2 of the transistor M4 may be in the range of 0.5 to 1, but is not limited thereto. In some embodiments, the sum of areas A3 of the plurality of signal lines SG1-SG10 may be, for example, the sum of areas of wire segments of the signal lines SG1-SG10 corresponding to the range of one of the stage shift registers SR (i). For example, in the transistor M4 of fig. 4, the integrated structure formed by combining the source S4 and the drain D4 has an upper boundary and a lower boundary in the second direction D2, and the area calculation range of the signal lines SG1-SG10 corresponding to the shift register SR (i) can be defined by the upper boundary and the lower boundary, for example, and the sum of the areas of the wire segments of the signal lines SG1-SG10 within the range can be calculated, but is not limited thereto.

As shown in fig. 4, the display panel 10 further includes a sealant 120 disposed in the peripheral region PR, wherein the sealant 120 at least partially covers the shift register SR (i). For example, the sealant 120 can cover the signal lines SG1-SG11, the transistor M1, the transistor M2, the transistor M3, the transistor M7, the transistor M8 and the second capacitor CP2, but is not limited thereto. Since the sealant 120 of the present embodiment may be, for example, a photo-curable adhesive, there may be multiple light-transmitting regions (such as regions not masked by a metal layer or a semiconductor layer) in the shift register SR (i), and these regions may overlap with the sealant 120 to help the photo-curable adhesive cure.

In this embodiment, the transistors (e.g., the transistors M3-M8) can BE more closely arranged, for example, at least three transistors can BE arranged on one side of the second capacitor CP2, by the design that the branch electrodes BE of the transistors M1-M8 extend along the same direction (e.g., the second direction D2). Therefore, the space occupied by the shift register SR (i) can be reduced, and the width of the peripheral region PR can be further reduced. On the other hand, the light-transmitting area of the adjacent regions of the transistors M1 and M2 can be increased to further help the frame glue 120 to be cured. For example, the ratio of the light-transmitting area overlapping the sealant 120 to the whole area of the sealant 120 can be raised to about 41.5%, but is not limited thereto. In addition, by the design that the branch electrodes BE in the transistors M1-M8 extend along the same direction, the transistors M1-M8 can BE arranged side by side along the first direction D1, the complexity of the electric connection between the transistors M1-M8 and the signal lines SG1-SG11 can BE reduced, the capacitive load (C loading) caused by the mutual crossing of the signal lines SG1-SG11 is reduced, and the space occupied by the signal lines SG1-SG11 is reduced.

Fig. 5 is a schematic enlarged view of a portion of a display panel according to a first embodiment of the invention. Fig. 5 may be, for example, an enlarged schematic view of region 10R in fig. 1. In the region 10R, the boundary BD of the display region DR may have a curved shape, and the shift register SR may be arranged along the boundary BD. In the present embodiment, the signal lines SG1 to SG10 are disposed at one side of the multistage shift register SR and may extend obliquely along the boundary BD, and the signal lines SG1 to SG10 may not have a turning portion. Therefore, damage of the signal lines SG1 to SG10 due to electrostatic discharge (electro-STATIC DISCHARGE, ESD) at the turning portions can be reduced, and the space occupied by the signal lines SG1 to SG10 can be reduced. In addition, in fig. 5, a portion of the sub-pixels SP may be disposed outside the display region DR (or within the peripheral region PR), and the sub-pixels SP may be dummy sub-pixels, and the light emitted by the sub-pixels SP may be blocked by the upper shielding layer, so that the user can only observe the light in the display region DR, but not limited thereto.

The gate driving circuit of the present invention is not limited to the above embodiments. Other embodiments of the present invention will be further disclosed below, but in order to simplify the description and highlight differences between the embodiments, the same reference numerals are used to designate the same components below, and overlapping parts will not be repeated.

Please refer to fig. 6, which is a circuit layout diagram of a shift register according to a second embodiment of the present invention. The difference from the first embodiment is that in the present embodiment (refer to fig. 1), one of the adjacent two sub-pixel rows may be electrically connected to the gate driving circuit 1021 through one of the scanning lines SL, and the other of the adjacent two sub-pixel rows may be electrically connected to the gate driving circuit 1022 through the other of the scanning lines SL. For example, when the display panel 10 has 1440 columns of sub-pixels, the display panel 10 may have 1440 scan lines SL, wherein 720 scan lines SL may be electrically connected to the gate driving circuit 1021, and another 720 scan lines SL may be electrically connected to the gate driving circuit 1022, but not limited thereto. Therefore, the number of shift registers in the gate driving circuit 1021 or the gate driving circuit 1022 is also smaller than that in the first embodiment.

As shown in fig. 6, since the number of shift registers in the gate driving circuit 1021 or the gate driving circuit 1022 is small, the space available for each transistor in the shift register SR (i) is large, and the light transmission area in the shift register SR (i) can be larger than that of the shift register SR (i) of the first embodiment. In the case where the ratio of the channel width to the channel length of the transistor M4 of the present embodiment is kept the same as the transistor M4 of the first embodiment, the magnitude of the thrust (driving power) of the shift register SR (i) can also be kept the same. At this time, the length of the transistor M4 (or other transistors) in the shift register SR (i) in the second direction D2 can be increased, and the width of the transistor M4 (or other transistors) in the shift register SR (i) in the first direction D1 can be reduced, so as to reduce the width of the peripheral region PR, but not limited thereto. It is added that the channel width herein may be the length of the meandering path between the source and the drain, while the channel length may be the distance between the source and the drain.

On the other hand, similar to the first embodiment, the present embodiment can enable the transistors (e.g. the transistors M3-M8) to BE more closely arranged by the design that the branch electrodes BE of the transistors M1-M8 all extend along the same direction (e.g. the second direction D2), for example, at least three transistors can BE arranged on one side of the second capacitor CP 2. In the present embodiment, the ratio of the light-transmitting area overlapping the frame glue 120 to the whole area of the frame glue 120 can be raised to about 61.49%, but is not limited thereto.

In summary, in the gate driving circuit of the present invention, the branch electrodes of the transistors in the shift register are all extended along the same direction (e.g. the second direction), so that the transistors can be more closely arranged, for example, at least three transistors can be arranged on one side of the second capacitor. Therefore, the space occupied by the shift register can be reduced, and the width of the peripheral area can be further reduced. On the other hand, the light transmission area in the shift register can be increased to further help the frame glue to be solidified. In addition, the transistors can be arranged side by side along the first direction, so that the complexity of electric connection between the transistors and the signal lines can be reduced, the capacitive load caused by mutual crossing of the signal lines is reduced, and the space occupied by the signal lines is reduced. The signal line may be disposed at one side of the multi-stage shift register and may extend obliquely along a boundary of the display region, and the signal line may not have a turning portion. Therefore, the damage of the signal line caused by the ESD of the turning part can be reduced.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A gate driving circuit for driving a display panel, the gate driving circuit comprising:

the multi-stage shift register sequentially outputs a plurality of scanning signals to the display panel, wherein one stage of shift register of the multi-stage shift register comprises:

A plurality of transistors arranged side by side along a first direction, each transistor of the plurality of transistors comprising a source and a drain, and the source or the drain comprising a main electrode and a plurality of branch electrodes connected to the main electrode,

Wherein, one of the shift registers is an i-th shift register, and the i-th shift register includes:

a precharge unit for receiving a first input signal and a second input signal and controlling the potential of a first node according to the first input signal or the second input signal; the pull-up unit is coupled with the first node, receives a first clock signal and outputs an ith scanning signal from a second node according to the potential of the first node and the first clock signal, wherein i is a positive integer greater than or equal to 1; and

A pull-down unit coupled to the first node and the second node respectively,

Wherein the pull-up unit includes a transistor of a first portion of the plurality of transistors, the precharge unit includes a transistor of a second portion of the plurality of transistors, the pull-down unit includes a transistor of a third portion of the plurality of transistors, and the transistor of the third portion of the pull-down unit is disposed between the transistor of the first portion of the pull-up unit and the transistor of the second portion of the precharge unit in the first direction,

Wherein the plurality of branch electrodes of the plurality of transistors extend along a second direction, and the first direction and the second direction are not parallel.

2. The gate driving circuit as recited in claim 1, wherein said one-stage shift register further comprises a capacitor, at least three of said plurality of transistors being disposed on one side of said capacitor in said second direction, wherein said capacitor has two sides in said first direction, and said at least three transistors being disposed within a range formed by extending said two sides of said capacitor along said second direction.

3. The gate driving circuit of claim 2, wherein the plurality of transistors includes a first transistor electrically connected to a scan line of the display panel, and the first transistor outputs one of the scan signals to the scan line,

Wherein the ratio of an area of the capacitor to an area of the first transistor ranges from 0.1 to 0.5.

4. The gate driving circuit of claim 1, further comprising a plurality of signal lines disposed on one side of the multi-stage shift register and electrically connected to the multi-stage shift register, the plurality of transistors including a first transistor electrically connected to a scan line of the display panel, and the first transistor outputting one of the scan signals to the scan line, wherein a ratio of a sum of areas of the plurality of signal lines to an area of the first transistor ranges from 0.5 to 1.

5. The gate driving circuit of claim 1, wherein the transistors of the first portion of the pull-up unit comprise a first transistor and the pull-up unit further comprises a first capacitor, wherein,

A gate of the first transistor is coupled to the first node, a first end of the first transistor receives the first clock signal, and a second end of the first transistor is coupled to the second node, and

A first end of the first capacitor is coupled to the first node, and a second end of the first capacitor is coupled to the second node.

6. The gate drive circuit of claim 1, wherein the transistors of the second portion of the precharge unit comprise:

A second transistor having a first end receiving the first input signal, a gate coupled to the first end of the second transistor, and a second end coupled to the first node; and

A third transistor, a first end of the third transistor receiving the second input signal, a gate of the third transistor being coupled to the first end of the third transistor, and a second end of the third transistor being coupled to the first node.

7. The gate driving circuit of claim 1, wherein when i is any positive integer from 2 to (N-1), the first input signal is an (i-1) th stage scan signal output from an (i-1) th stage shift register, and the second input signal is an (i+1) th stage scan signal output from an (i+1) th stage shift register, wherein N is a positive integer greater than 2.

8. The gate drive circuit of claim 1, wherein the pull-down unit further comprises a second capacitor, a first end of the second capacitor receives the first clock signal, and the transistor of the third portion of the pull-down unit comprises:

a fourth transistor, a gate of the fourth transistor being coupled to the first node, a first terminal of the fourth transistor receiving a reference potential, and a second terminal of the fourth transistor being coupled to a second terminal of the second capacitor;

a fifth transistor, a gate of the fifth transistor being coupled to the second terminal of the second capacitor, a first terminal of the fifth transistor receiving the reference potential, and a second terminal of the fifth transistor being coupled to the first node;

a sixth transistor, a gate of the sixth transistor being coupled to the second terminal of the second capacitor, a first terminal of the sixth transistor receiving the reference potential, and a second terminal of the sixth transistor being coupled to the second node;

a seventh transistor having a gate receiving a second clock signal, a first end receiving the reference potential and a second end coupled to the second node, and

An eighth transistor having a gate receiving the second clock signal, a first terminal receiving the reference potential, and a second terminal coupled to the first node.

9. The gate driver circuit according to claim 8, wherein the sixth transistor, the seventh transistor, and the eighth transistor are provided on one side of the second capacitor in the second direction, wherein the second capacitor has two sides in the first direction, and wherein the sixth transistor, the seventh transistor, and the eighth transistor are provided within a range formed by extending the two sides of the second capacitor in the second direction.