CN108182921B - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
- Publication number
- CN108182921B CN108182921B CN201810005105.4A CN201810005105A CN108182921B CN 108182921 B CN108182921 B CN 108182921B CN 201810005105 A CN201810005105 A CN 201810005105A CN 108182921 B CN108182921 B CN 108182921B
- Authority
- CN
- China
- Prior art keywords
- shift register
- transistor
- register unit
- cascade
- array substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
Abstract
The invention discloses an array substrate, a display panel and a display device, wherein the array substrate comprises a grid drive circuit, the grid drive circuit comprises a plurality of cascaded shift register units, each level of shift register unit is connected with a row of scanning lines, and the cascaded shift register units are electrically connected through cascaded routing lines; each shift register unit comprises a bootstrap capacitor; the bootstrap capacitor comprises a first polar plate, the first polar plate and the cascade wiring are arranged in an overlapping mode, and the part, overlapped with the first polar plate, of the cascade wiring is reused as a second polar plate of the bootstrap capacitor. Therefore, the second polar plate of the bootstrap capacitor does not need to be additionally and independently arranged, the layout area occupied by the bootstrap capacitor on the array substrate can be reduced, the layout area of the whole gate drive circuit can be reduced, and the narrow frame design of the display device is facilitated.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.
Background
Display devices such as Liquid Crystal Display (LCD) or Organic Light Emitting Diode (OLED) display devices have the advantages of low radiation, small size and low power consumption, and are widely used in information products such as notebook computers, Personal Digital Assistants (PDAs), flat panel televisions and mobile phones.
The drive circuit of the display device includes: an array of pixels for displaying an image; a data driving circuit supplying a data signal to the pixel array through the data line; gate pulses (or scan pulses) synchronized with the data signals are sequentially supplied to the gate driving circuit of the pixel array through the scan lines, and the like.
Currently, the GOA technology is a gate driving circuit technology commonly used in display devices, and a TFT (Thin film transistor) gate switch circuit is integrated on an array substrate of a display panel to form a scan drive for the display panel, so that a bonding area and a peripheral wiring space of the gate driving circuit can be omitted. The functions of the GOA circuit mainly include: the high level signal output by the previous scanning line is used for charging the capacitor in the shift register unit, so that the scanning line of the current row outputs the high level signal, and then the high level signal output by the scanning line of the next row is used for realizing the reset. When the number of scan lines increases due to an increase in resolution of the display panel, the size of the gate driving circuit increases, which increases the bezel area of the display panel, and is disadvantageous for a narrow bezel design of the display device.
Disclosure of Invention
The embodiment of the invention provides an array substrate capable of reducing the size of a gate drive circuit, and a display panel and a display device comprising the array substrate are favorable for the narrow frame design of the display device.
Firstly, an embodiment of the present invention provides an array substrate, including a gate driving circuit, where the gate driving circuit includes a first clock signal line and a plurality of cascaded shift register units, and each stage of the shift register unit is connected to a row of scan lines, where the plurality of cascaded shift register units are electrically connected through a cascaded trace; each shift register unit comprises a logic module, a driving transistor and a bootstrap capacitor; the grid electrode of the driving transistor is connected with the driving signal output end of the logic module, the first pole of the driving transistor is connected to the first clock signal line, and the second pole of the driving transistor is connected with the current-stage signal output end of the shift register unit; the bootstrap capacitor comprises a first polar plate, the first polar plate is overlapped with the cascade wiring, the first polar plate of the bootstrap capacitor is connected with the grid electrode of the driving transistor, and the part of the cascade wiring, which is overlapped with the first polar plate, is reused as a second polar plate of the bootstrap capacitor.
In an embodiment of the present invention, the gate driving circuit further includes a first driving signal line and a second driving signal line, and the logic module includes a charging transistor and a discharging transistor, wherein a first pole of the charging transistor is connected to the first driving signal line, and a second pole of the charging transistor is connected to a second pole of the discharging transistor and the gate of the driving transistor; a first electrode of the discharge transistor is connected to the second driving signal line; from the second-stage shift register unit to the penultimate shift register unit, the grid electrode of the charging transistor is connected to the current-stage signal output end of the previous-stage shift register unit adjacent to the charging transistor through the cascade routing; the grid of the discharge transistor is connected to the signal output end of the current stage of the next stage of the shift register unit adjacent to the discharge transistor through the cascade routing.
In an embodiment of the invention, the first plate of the bootstrap capacitor and the second plate of the charging transistor are formed in the same layer, and the cascade trace and the gate of the charging transistor are formed in the same layer.
In an embodiment of the present invention, the cascade trace is connected to the signal output end of the shift register unit at the current stage; the bootstrap capacitor further comprises a third polar plate, the third polar plate is located on one side of the first polar plate far away from the cascade wiring, and the third polar plate is connected with the signal output end of the shift register unit.
In an embodiment of the present invention, the third plate is connected to the signal output end of the current stage of the shift register unit through a first via, and the third plate is connected to the cascade trace of the shift register unit through a second via.
In an embodiment of the present invention, the first plate of the bootstrap capacitor includes a first conductive layer and a second conductive layer connected to each other, and the second conductive layer and the third plate are transparent conductive layers; the array substrate further comprises a first metal layer and a second metal layer, the first metal layer comprises cascade wiring and a grid electrode of the charging transistor, and the second metal layer comprises a first conductive layer; the overlapping area of the second conducting layer and the third polar plate is larger than that of the first conducting layer and the third polar plate.
In an embodiment of the invention, at least a portion of the second conductive layer has a width in a direction perpendicular to the extending direction of the cascade trace that is greater than a width of the first conductive layer in the direction perpendicular to the extending direction of the cascade trace, at least a portion of the third electrode plate has a width in the direction perpendicular to the extending direction of the cascade trace that is greater than a width of the first conductive layer in the direction perpendicular to the extending direction of the cascade trace, and a portion of the second conductive layer having a greater width is disposed corresponding to a portion of the third electrode plate having a greater width.
In one embodiment of the present invention, the array substrate further includes a first transparent conductive layer and a second transparent conductive layer, wherein the first transparent conductive layer includes one of the pixel electrode and the common electrode, the second transparent conductive layer includes the other of the pixel electrode and the common electrode, and the first transparent conductive layer is located on one side of the second transparent conductive layer close to the second metal layer; the first transparent conductive layer further comprises a second conductive layer, and the second transparent conductive layer further comprises a third polar plate.
In an embodiment of the present invention, the first metal layer further includes a scan line, and the second metal layer further includes a data line.
In one embodiment of the present invention, for a first stage shift register unit: the grid electrode of the charging transistor receives an initial signal, and the grid electrode of the discharging transistor is connected to the current-stage signal output end of the second-stage shift register unit through the cascade routing; for the penultimate stage shift register unit (i.e., the last stage shift register unit): the grid electrode of the charging transistor is connected to the current-stage signal output end of the penultimate shift register unit through the cascade routing, and the grid electrode of the discharging transistor receives the reset signal.
In an embodiment of the present invention, the gate driving circuit further includes a second clock signal line, and the logic module further includes a pull-down transistor, wherein a gate of the pull-down transistor is connected to the second clock signal line, a first pole of the pull-down transistor is connected to the second driving signal line, and a second pole of the pull-down transistor is connected to the present-stage signal output terminal of the shift register unit.
In addition, the invention also provides a display panel which comprises the array substrate.
In addition, the invention also provides a display device which comprises the display panel.
The array substrate, the display panel and the display device provided by the embodiment of the invention comprise the gate drive circuit, and the part of the cascade wiring of the gate drive circuit, which is overlapped with the first polar plate of the bootstrap capacitor, is reused as the second polar plate of the bootstrap capacitor, so that the second polar plate of the bootstrap capacitor is not required to be separately arranged, the layout area occupied by the bootstrap capacitor on the array substrate can be reduced, the layout area of the whole gate drive circuit can be reduced, and the narrow-frame design of the display device is facilitated.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic view of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a gate driving circuit according to an embodiment of the invention;
FIG. 3 is a diagram of a shift register according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a gate driving circuit according to an embodiment of the invention;
fig. 5 is a schematic diagram of another gate driving circuit according to an embodiment of the invention;
FIG. 6 is a cross-sectional view taken along line A-A' of FIG. 5;
fig. 7 is a cross-sectional view of a portion of another gate driving circuit according to an embodiment of the present invention;
fig. 8 is a schematic diagram of another gate driving circuit according to an embodiment of the invention;
fig. 9 is a sectional view taken along B-B' in fig. 8.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
First, the present invention provides an array substrate, as shown in fig. 1, fig. 1 is a schematic view of an array substrate according to an embodiment of the present invention. Specifically, the array substrate 100 includes a display region 101, a non-display region 102 disposed around the display region, and a pixel array disposed in the display region 101, where the pixel array includes a plurality of data lines DL disposed in parallel and a plurality of scan lines GL disposed in parallel, the plurality of data lines DL and the plurality of scan lines GL are crossed to define a plurality of sub-pixels P, each sub-pixel P includes a display driving switch and a pixel electrode, and the display driving switch may be, for example, a thin film transistor having three terminals, i.e., a gate terminal, a source terminal, and a drain terminal, and the pixel electrode is connected to the source terminal (or the drain terminal) of the thin film transistor. The pixel array may include, for example, a plurality of rows and a plurality of columns of sub-pixels P, the drain (or source) of the thin film transistor in each column of sub-pixels P may be connected to the same data line DL, for example, the data line DL provides a data signal for the sub-pixels P in the corresponding column, the gate of the thin film transistor in each row of sub-pixels P may be connected to the same scanning line GL, for example, the scanning line GL provides a scanning signal for the sub-pixels P in the corresponding row, and for the sake of brief description, the structure of each sub-pixel is schematically illustrated in fig. 1.
The array substrate 100 further includes a data driving circuit 02 and a gate driving circuit 01 located in the non-display region 102, the gate driving circuit 01 includes at least two stages of shift register units, each stage of shift register unit is connected to one row of scan lines, so that scan signals can be sequentially input to the scan lines to implement the progressive scanning of the scan lines. The data driving circuit 02 may include, for example, a plurality of data pins connected to the plurality of data lines DL, and may sequentially input data signals to the data lines DL and realize display of a predetermined image under the control of a scan signal.
In the schematic diagram shown in fig. 1, the gate driver circuit 01 is located in the non-display region 102 on the display region 101 side, and all the scanning lines GL are connected to corresponding shift register cells in the gate driver circuit 01. The following steps can be also included: the gate driving circuit 01 comprises two parts which are respectively positioned at two sides of the display area 101, wherein a shift register unit in one part of the gate driving circuit 01 is connected with odd-numbered scanning lines, and a shift register unit in the other part of the gate driving circuit 01 is connected with even-numbered scanning lines; or, two ends of each row of scanning lines are respectively and simultaneously connected to the corresponding shift register units at two sides, so that the driving capability is improved, and the signal delay is reduced.
Referring to fig. 2, fig. 2 is a schematic diagram of a gate driving circuit according to an embodiment of the present invention, in the embodiment, the gate driving circuit 01 includes a plurality of cascaded shift register units 10 and a plurality of driving signal buses (e.g., DR1, DR2, CK1, and CK2 in the figure), the number of the shift register units 10 is equal to the number of scanning lines in a display area, the cascaded shift register units 10 are electrically connected through cascaded traces 11, and each stage of the shift register units 10 is connected to one row of the scanning lines in the display area, so that the input scanning signals are shifted through the cascaded shift register units to implement progressive scanning of the rows of the scanning lines. The signal bus may include, for example: a first driving signal line DR1 for providing a first driving signal to each stage of the shift register unit 10, which may be a high level signal or a low level signal according to the requirement of the scanning line driving; a second driving signal line DR2 for providing a second driving signal to each stage of the shift register unit 10, which may be a high level signal or a low level signal according to the requirement of the scanning line driving; a first clock signal line CK1 for supplying a first clock signal to each stage of the shift register unit 10, and a second clock signal line CK2 for supplying a second clock signal to each stage of the shift register unit 10, and so on.
In the gate driving circuit 01, except for the first stage shift register unit, the first signal Input terminal of each of the other shift register units is connected to the current stage signal output terminal Gout (or the scan line connected to the previous stage shift register unit) of the previous stage shift register unit adjacent thereto through the cascade trace 11, and the high level signal output by the previous scan line is used to charge the capacitor in the shift register unit, so that the current scan line outputs the high level signal. The first signal Input end of the first stage shift register unit receives the start signal STP, and charges a capacitor in the first stage shift register unit, so that the scanning line of the row outputs a high level signal.
Except the last stage (the last but one stage) of shift register unit, the second signal input end Reset of each other stage of shift register unit is connected with the current stage signal output end Gout (or the scanning line connected with the next stage of shift register unit) of the next stage of shift register unit adjacent to the last stage of shift register unit through the cascade wiring 11, and the high level signal output by the next row of scanning line is used for realizing the Reset. The second signal input terminal Reset of the last stage shift register unit may input a Reset signal.
The gate driving circuit may start from the first stage shift register unit to scan stage by stage, and certainly, may also implement scanning in different directions according to different input positions of the start signal STP.
Specifically, when the first signal Input terminal Input of the first stage shift register unit in each stage of the shift register units of the gate driving circuit receives the start signal STP and the second signal Input terminal Reset of the last stage shift register unit inputs the Reset signal, the present signal Output terminal Gout of each stage of the shift register units sequentially outputs the scan signal to the scan line corresponding thereto from top to bottom, and when the second signal Input terminal Reset of the last stage shift register unit in each stage of the shift register units of the gate driving circuit receives the start signal STV and the first signal Input terminal Input of the first stage shift register unit inputs the Reset signal, the present signal Output terminal Output of each stage sequentially outputs the scan signal to the scan line corresponding thereto from bottom to top.
Referring to fig. 3, fig. 3 is a schematic diagram of a shift register unit according to an embodiment of the present invention, in which each shift register unit includes a logic module 12, a driving transistor T1, and a bootstrap capacitor Cs. The gate of the driving transistor T1 is connected to the driving signal Output terminal Output of the logic module, the first pole of the driving transistor T1 is connected to the first clock signal line CK1 of the gate driving circuit, and the second pole of the driving transistor T1 is connected to the current-stage signal Output terminal Gout of the shift register unit, or to the scan line GL connected to the current-stage shift register unit. A first terminal of the bootstrap capacitor Cs is connected to the gate of the driving transistor T1, and a second terminal of the bootstrap capacitor Cs is connected to the second pole of the driving transistor T1, or connected to the current-stage signal output terminal Gout of the shift register unit, or connected to the scan line GL connected to the current-stage shift register unit. When the gate of the driving transistor T1 is about to receive a driving signal transmitted from the driving signal Output terminal Output of the logic module to the gate, the second end of the bootstrap capacitor Cs is in a floating state, and as the gate potential of the driving transistor T1 rises, the potential of the second end of the bootstrap capacitor Cs rises, and the voltage of the first end of the bootstrap capacitor Cs is coupled and rises accordingly, generally, the voltage of the first end is coupled to be very high, so that the gate potential of the driving transistor T1 is raised, the equivalent resistance of the driving transistor T1 is very small, the loss of the driving transistor is reduced, and thus the voltage of the scan line can be kept as close to the signal voltage given by the first clock signal line CK1 as possible, and the driving capability of the gate driving circuit is improved.
Referring to fig. 4, fig. 4 is a schematic diagram of another gate driving circuit according to an embodiment of the present invention, and of course, in order to clearly show a connection manner of the bootstrap capacitor Cs according to the embodiment of the present invention, fig. 4 only shows a partial structure of the gate driving circuit, and the components of the gate driving circuit according to the embodiment of the present invention are not limited to the portions shown in the drawing.
In the present embodiment, referring to fig. 2, 3 and 4, the gate driving circuit 01 includes a driving signal bus (e.g., CK1, CK2, DR1, DR2, etc.) and a plurality of cascaded shift register units 10, the driving signal bus includes a first clock signal line CK1, a second clock signal line CK2, a first driving signal line DR1 and a second driving signal line DR2, the shift register unit 10 includes a driving transistor T1, a bootstrap capacitor Cs and a logic module 12, and the logic module 12 includes at least a charging transistor T2 and a discharging transistor T3.
The first electrode T11 of the driving transistor T1 is connected to the first clock signal line CK1 for receiving a first clock signal; the second pole T12 of the driving transistor T1 is connected to the signal output terminal Gout of the current stage of the shift register unit, or to the scan line GL connected to the current stage of the shift register unit.
For the second stage shift register unit to the next to last stage shift register unit:
the first pole T21 of the charging transistor T2 is connected to the first driving signal line DR1 for receiving the first driving signal, the second pole T22 of the charging transistor T2 is connected to the gate T10 of the driving transistor T1, and the gate T20 of the charging transistor T2 is connected to the signal output terminal Gout of the current stage of the previous stage shift register unit adjacent thereto through the cascade wiring 11.
The first pole T31 of the discharging transistor T3 is connected to the second driving signal line DR2 for receiving the second driving signal, the second pole T32 of the discharging transistor T3 is connected to the second pole T22 of the charging transistor T2 and the gate T10 of the driving transistor T1 at the same time, and the gate T30 of the discharging transistor T3 is connected to the signal output terminal Gout of the current stage of the next stage of shift register unit adjacent thereto through the cascade trace 11.
In addition, for the first stage shift register unit: a first pole T21 of the charging transistor T2 is connected to the first driving signal line DR1 for receiving the first driving signal, a second pole T22 of the charging transistor T2 is connected to the gate T10 of the driving transistor T1, and the gate T20 of the charging transistor T2 receives the start signal; a first pole T31 of the discharging transistor T3 is connected to the second driving signal line DR2 for receiving the second driving signal, a second pole T32 of the discharging transistor T3 is connected to both the second pole T22 of the charging transistor T2 and the gate T10 of the driving transistor T1, and the gate T30 of the discharging transistor T3 is connected to the present-stage signal output terminal of the second-stage shift register unit through the cascade trace 11;
for the next to last stage shift register cell: a first pole T21 of the charging transistor T2 is connected to the first driving signal line DR1 for receiving the first driving signal, a second pole T22 of the charging transistor T2 is connected to the gate T10 of the driving transistor T1, and the gate T20 of the charging transistor T2 is connected to the present-stage signal output terminal of the shift register unit of the second last stage through the cascade wiring 11; the first pole T31 of the discharging transistor T3 is connected to the second driving signal line DR2 for receiving the second driving signal, the second pole T32 of the discharging transistor T3 is connected to both the second pole T22 of the charging transistor T2 and the gate T10 of the driving transistor T1, and the gate T30 of the discharging transistor T3 receives the reset signal.
The driving transistor, the charging transistor, and the discharging transistor are, for example, thin film transistors, and include a gate electrode, a semiconductor active layer, and a source drain, wherein the material of the semiconductor active layer may be, for example, amorphous silicon, low temperature polysilicon, and the like.
Specifically, the nth stage shift register unit is taken as an example for explanation: the plurality of cascaded shift register units comprise an (N-1) th-stage shift register unit, an Nth-stage shift register unit and an (N +1) th-stage shift register unit, wherein N is a positive integer and is more than or equal to 2.
For the Nth stage shift register unit: the gate T20 of the charging transistor T2 is connected to the second pole T12 of the driving transistor T1 of the (N-1) th stage shift register unit, or to the scan line GL connected to the (N-1) th stage shift register unit, through the cascade wiring 11; the gate T30 of the discharge transistor T3 is connected to the second pole T12 of the driving transistor T1 of the (N +1) th stage shift register unit, or to the scan line GL connected to the (N-1) th stage shift register unit, through the cascade wiring 11;
the bootstrap capacitor Cs includes a first plate Cs1 connected to the gate T10 of the driving transistor T1, the first plate Cs1 is overlapped with the cascade trace 11, or at least a portion of the cascade trace 11 is overlapped with the first plate Cs1, and the cascade trace 11 is connected to the signal output end Gout of the shift register unit, wherein a portion of the cascade trace 11 overlapped with the first plate Cs1 is reused as a second plate Cs2 of the bootstrap capacitor Cs. Therefore, the second polar plate of the bootstrap capacitor does not need to be additionally and independently arranged, the layout area occupied by the bootstrap capacitor on the array substrate can be reduced, the layout area of the whole gate drive circuit can be reduced, and the narrow frame design of the display device is facilitated.
Further, in the present embodiment, the logic module 12 further includes a pull-down transistor T4, specifically, the gate T40 of the pull-down transistor T4 is connected to the second clock signal line CK2 for receiving the second clock signal, the first pole T41 of the pull-down transistor T4 is connected to the second driving signal line DR2, and the second pole T42 of the pull-down transistor T4 is connected to the second pole T22 of the driving transistor T1 or the present-stage signal output terminal of the shift register unit for keeping the low potential of the present-stage scanning line.
In the embodiment, for example, the first plate Cs1 of the bootstrap capacitor Cs and the second plate T22 of the charging transistor T2 may be formed at the same layer, and the cascade trace 11 and the gate T20 of the charging transistor T2 may be formed at the same layer.
Further, in this embodiment, for example, the following may be used: the array substrate comprises a first metal layer and a second metal layer, and the first metal layer and the second metal layer can be arranged at an interval in an insulating mode through an insulating layer or a passivation layer. The first metal layer comprises a scanning line positioned in the display area, a grid electrode of the display driving switch, a driving signal bus (such as CK1, CK2, DR1, DR2 and the like) positioned in the non-display area, a cascade wiring, a grid electrode of the driving transistor, a grid electrode of the charging transistor, a grid electrode of the discharging transistor and a grid electrode of the pull-down transistor; the second metal layer comprises a data line positioned in the display area, a source drain electrode of the display driving switch, a first polar plate of the bootstrap capacitor positioned in the non-display area, a first pole of the driving transistor, a second pole of the driving transistor, a first pole of the charging transistor, a second pole of the charging transistor, a first pole of the discharging transistor, a second pole of the discharging transistor, a first pole of the pull-down transistor and a second pole of the pull-down transistor. At this time, the first electrodes of the driving transistor, the charging transistor, and the discharging transistor may be connected to the first clock signal line CK1, the first driving signal line DR1, and the second driving signal line DR2, respectively, for example, through vias; the second poles of the charge transistor and the discharge transistor may be connected to the gate of the drive transistor, for example, by vias; the gate of the pull-down transistor may be connected to the second clock signal line CK2 through a jumper structure, for example, and the first pole of the pull-down transistor may be connected to the second driving signal line DR2 through a via hole, for example.
Of course, in other embodiments, the following may be possible: the second metal layer includes a scan line located in the display region and a gate of the display driving switch, and the first metal layer includes a data line located in the display region and a source/drain of the display driving switch.
Fig. 5 is a schematic diagram of another gate driving circuit according to an embodiment of the present invention, fig. 6 is a cross-sectional view taken along a-a' in fig. 5, the gate driving circuit provided in fig. 5 and fig. 6 has a structure similar to that of the gate driving circuit provided in fig. 3, the bootstrap capacitor Cs includes a first plate Cs1 connected to the gate of the driving transistor, at least a portion of the cascade trace 11 is overlapped with the first plate Cs1, and the cascade trace 11 is connected to the present-stage signal output end of the shift register unit, wherein a portion of the cascade trace 11 overlapped with the first plate Cs1 is reused as a second plate Cs2 of the bootstrap capacitor Cs. The difference lies in that: the bootstrap capacitor Cs further includes a third plate Cs3, the third plate Cs3 is overlapped with the first plate Cs1, the first plate Cs1, the second plate Cs2, and the third plate Cs3 are disposed at an insulation interval through an insulation layer or a passivation layer, and the third plate Cs3 is located on one side of the first plate Cs1 away from the cascade trace 11, the third plate Cs3 is connected to the present-stage signal output end of the shift register unit through a first via hole H1, or connected to the scan line GL connected to the present-stage signal output end, so that the bootstrap capacitor Cs is set as a capacitor of a sandwich structure formed by the first plate Cs1, the second plate Cs2, and the third plate Cs3 and the insulation layer therebetween, and the coupling capability and the bootstrap capability of the bootstrap capacitor Cs can be improved without changing the area of the bootstrap capacitor Cs, loss of the driving transistor is further reduced, and the driving capability of the gate driving circuit is improved.
Further, in this embodiment, for example, the following may be used: the array substrate further comprises a common electrode, an electric field can be formed between the common electrode and the pixel electrode, and the third polar plate Cs3 and the pixel electrode or the common electrode of the display area of the array substrate are formed in the same layer, so that the manufacturing steps of the array substrate are not increased when the third polar plate Cs3 is added, and the cost is reduced.
Fig. 7 is a cross-sectional view of a partial structure of another gate driving circuit provided in an embodiment of the present invention, the gate driving circuit provided in fig. 7 is similar to the gate driving circuit provided in fig. 5, the bootstrap capacitor Cs includes a first plate Cs1, a second plate Cs2, and a third plate Cs3, the third plate Cs3 is located on a side of the first plate Cs1 away from the second plate Cs2, and the third plate Cs3 is connected to the present-stage signal output terminal of the shift register unit through a via or to the scan line GL connected to the present-stage signal output terminal, so as to form a capacitor in a sandwich structure, which can improve the coupling capability and bootstrap capability of the bootstrap capacitor Cs without changing the area of the bootstrap capacitor Cs, further reduce the loss of the driving transistor, and improve the driving capability of the gate driving circuit. The difference lies in that: the third polar plate Cs3 is connected to the signal output terminal of the shift register unit at the current stage through a first via H1, or connected to the scan line GL connected to the signal output terminal at the current stage, and the first via H1 penetrates through the insulating layer or the passivation layer between the third polar plate Cs3 and the layer where the scan line GL is located; the third polar plate Cs3 is connected to the cascade trace 11 of the shift register unit through the second via H2, or is connected to the second polar plate Cs2, the second via H2 penetrates through at least two layers of insulating layers or passivation layers between the first polar plate Cs1 and the layer where the cascade trace 11 is located, and the cascade trace 11 and the signal output end of the shift register unit are connected to each other, so the cascade trace 11 has the same potential as the signal output end of the shift register unit. Two or more through holes are adopted to connect the third polar plate with the signal output end of the shift register unit, so that equivalent resistance can be reduced, and meanwhile, the risk of open circuit caused by bad through holes can be reduced.
Fig. 8 is a schematic diagram of another gate driving circuit according to an embodiment of the present invention, fig. 9 is a cross-sectional view taken along B-B' in fig. 8, the gate driving circuit provided in fig. 8 and 9 has a structure similar to that of the gate driving circuit provided in fig. 5, a first plate Cs1, a second plate Cs2 and a third plate Cs3, the third plate Cs3 is located on a side of the first plate Cs1 away from the second plate Cs2, and the third plate Cs3 is connected to the present-stage signal output terminal of the shift register unit through a via or connected to the scan line GL connected to the present-stage signal output terminal, so as to form a capacitor with a sandwich structure. The difference lies in that: the first plate Cs1 of the bootstrap capacitor Cs includes a first conductive layer Cs11 and a second conductive layer Cs12 connected to each other, wherein the first conductive layer Cs11 is a light-shielding metal layer, the second conductive layer Cs12 and the third plate Cs2 are transparent conductive layers, and an overlapping area of the second conductive layer Cs12 and the third plate Cs3 is larger than an overlapping area of the first conductive layer Cs11 and the third plate Cs 3.
Specifically, in the embodiment, the array substrate includes a first metal layer M1 and a second metal layer M2, and the first metal layer M1 and the second metal layer M2 may be disposed at an insulating interval through a passivation layer, for example. The first metal layer M1 includes scan lines in the display area, gates of the display driving switches, and driving signal buses (e.g., CK1, CK2, DR1, DR2, etc.) in the non-display area, cascade wires, gates of the driving transistors, gates of the charging transistors, gates of the discharging transistors, and gates of the pull-down transistors; the second metal layer M2 includes a data line located in the display area, a source drain of the display driving switch, a first plate of the bootstrap capacitor located in the non-display area, a first electrode of the driving transistor, a second electrode of the driving transistor, a first electrode of the charging transistor, a second electrode of the charging transistor, a first electrode of the discharging transistor, a second electrode of the discharging transistor, a first electrode of the pull-down transistor, and a second electrode of the pull-down transistor. The first conductive layer Cs11 of the first polar plate Cs1 is formed in the same layer as the second metal layer M2.
Of course, in other embodiments, the following may be possible: the second metal layer M2 includes a scan line located in the display area and a gate of the display driving switch, and the first metal layer M1 includes a data line located in the display area and a source/drain of the display driving switch.
Further, in this embodiment, the array substrate further includes a first transparent conductive layer I1 and a second transparent conductive layer I2, the first transparent conductive layer I1 includes one of the pixel electrode and the common electrode, and a second conductive layer Cs12 of the first polar plate Cs1, the second conductive layer Cs12 is connected to the first conductive layer Cs11, or the second conductive layer Cs12 is in direct contact with the first conductive layer Cs11, that is, an insulating layer or a passivation layer with insulating property is no longer disposed between the second conductive layer Cs12 and the first conductive layer Cs 11; the second transparent conductive layer I2 includes the other of the pixel electrode and the common electrode, and a third plate Cs3, and an overlapping area of the second conductive layer Cs12 and the third plate Cs3 is larger than an overlapping area of the first conductive layer Cs11 and the third plate Cs 3.
For example, it may be: the width of the second conductive layer Cs12 in the extending direction perpendicular to the cascade trace 11 is larger than the width of the first conductive layer Cs11 in the extending direction perpendicular to the cascade trace 11, and the width of the third plate Cs3 in the extending direction perpendicular to the cascade trace 11 is larger than the width of the first conductive layer Cs11 in the extending direction perpendicular to the cascade trace 11; of course, in consideration of the layout problem of the traces and the transistors in the gate driving circuit, it may also be configured that at least a portion of the second conductive layer Cs12 has a width in the direction perpendicular to the extension direction of the cascade trace 11 that is greater than a width of the first conductive layer Cs11 in the direction perpendicular to the extension direction of the cascade trace 11, at least a portion of the third plate Cs3 has a width in the direction perpendicular to the extension direction of the cascade trace 11 that is greater than a width of the first conductive layer Cs11 in the direction perpendicular to the extension direction of the cascade trace 11, and the portion of the second conductive layer Cs12 with the greater width is disposed corresponding to the portion of the third plate Cs3 with the greater width, so as to increase the overlapping area between the second conductive layer Cs12 and the third plate Cs 3.
The first transparent conductive layer I1 is located on one side of the second transparent conductive layer I2 close to the second metal layer M2. In one embodiment of the present invention, the first transparent conductive layer I1 and the second transparent conductive layer may be formed of ITO (indium tin oxide) material or other transparent conductive materials, for example.
Since the first conductive layer Cs11 and the cascade trace are both formed by the light-shielding metal layer, and the position of the array substrate corresponding to the gate driving circuit is subsequently subjected to frame glue coating and ultraviolet light curing, a certain transmittance is required at this position to ensure the curing effect of the frame glue, so that the width of the first conductive layer or the area of the first conductive layer is not too large, and the cascade trace multiplexed as the second electrode plate is not too wide. In the embodiment of the invention, the coupling capacity of the bootstrap capacitor Cs is improved by increasing the overlapping area of the second conductive layer Cs12 and the third polar plate Cs3, and since the second conductive layer Cs12 and the third polar plate Cs3 are transparent conductive layers, even if the layout area of the second conductive layer Cs12 and the third polar plate Cs3 is enlarged, the transmittance of the non-display area is not affected, and after the non-display area of the array substrate is coated with the frame glue, the coupling capacity of the bootstrap capacitor Cs can be increased, and the frame glue curing effect can be ensured.
Moreover, the second conductive layer and one of the pixel circuit and the common electrode are formed in the same layer, and the third electrode plate and the other of the pixel circuit and the common electrode are formed in the same layer, so that the coupling capacity of the bootstrap capacitor is improved, the processing steps of the array substrate are not increased, and the cost is reduced.
In summary, in an embodiment of the present invention, a portion of the cascade trace overlapping with the first electrode plate is reused as the second electrode plate of the bootstrap capacitor, so that there is no need to separately set the second electrode plate of the bootstrap capacitor, and a layout area occupied by the bootstrap capacitor on the array substrate can be reduced, thereby reducing a layout area of the whole gate driving circuit, and facilitating a narrow frame design of the display device. In another embodiment of the present invention, the coupling capability of the bootstrap capacitor Cs is improved by providing a transparent third plate, or by increasing the overlapping area of the third plate and the second conductive layer.
In addition, an embodiment of the present invention further provides a display panel having the array substrate, where the display panel has the same structure and beneficial effects as the array substrate provided in the embodiment, and since the structure and beneficial effects of the array substrate have been described in detail in the foregoing embodiment, details are not repeated herein.
In addition, the embodiment of the invention also provides a display device which comprises the display panel. The structure and the advantageous effects of the array substrate provided in the above embodiments are the same, and since the structure and the advantageous effects of the array substrate have been described in detail in the foregoing embodiments, no further description is provided herein.
In the embodiment of the present invention, the display device may specifically include a liquid crystal display device, for example, the display device may be any product or component with a display function, such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.
The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
Claims (13)
1. The array substrate is characterized by comprising a grid driving circuit, wherein the grid driving circuit comprises a first clock signal line and a plurality of cascaded shift register units, each level of shift register unit is connected with a row of scanning lines, and the cascaded shift register units are electrically connected through cascaded routing lines;
each shift register unit comprises a logic module, a driving transistor and a bootstrap capacitor;
the grid electrode of the driving transistor is connected with the driving signal output end of the logic module, the first pole of the driving transistor is connected with the first clock signal line, and the second pole of the driving transistor is connected with the current-stage signal output end of the shift register unit;
the bootstrap capacitor comprises a first polar plate, the first polar plate is overlapped with the cascade wiring, the first polar plate of the bootstrap capacitor is connected with the grid electrode of the driving transistor, and the part of the cascade wiring, which is overlapped with the first polar plate, is reused as a second polar plate of the bootstrap capacitor.
2. The array substrate of claim 1, wherein the gate driving circuit further comprises a first driving signal line and a second driving signal line, the logic module comprises a charging transistor and a discharging transistor,
a first pole of the charging transistor is connected with the first driving signal line, and a second pole of the charging transistor is connected with a second pole of the discharging transistor and the grid electrode of the driving transistor; the first pole of the discharge transistor is connected with the second driving signal line;
from the second-stage shift register unit to the penultimate shift register unit, the grid electrode of the charging transistor is connected to the current-stage signal output end of the previous-stage shift register unit adjacent to the charging transistor through the cascade routing; and the grid electrode of the discharge transistor is connected to the current-stage signal output end of the next-stage shift register unit adjacent to the grid electrode of the discharge transistor through the cascade routing.
3. The array substrate of claim 2, wherein the first plate of the bootstrap capacitor and the second electrode of the charge transistor are formed at the same layer, and the cascade trace and the gate of the charge transistor are formed at the same layer.
4. The array substrate of claim 1, wherein the cascade trace is connected to the signal output terminal of the current stage of the shift register unit,
the bootstrap capacitor further comprises a third polar plate, the third polar plate is located on one side of the first polar plate, which is far away from the cascade wiring, and the third polar plate is connected with the current-stage signal output end of the shift register unit.
5. The array substrate of claim 4, wherein the third plate is connected to the signal output terminal of the current stage of the shift register unit through a first via hole, and the third plate is connected to the cascade trace of the shift register unit through a second via hole.
6. The array substrate of claim 4, wherein the first plate of the bootstrap capacitor comprises a first conductive layer and a second conductive layer connected to each other, and the second conductive layer and the third plate are transparent conductive layers;
the array substrate further comprises a first metal layer and a second metal layer, the first metal layer comprises cascade wiring and a grid electrode of the charging transistor, and the second metal layer comprises a first conductive layer;
the overlapping area of the second conducting layer and the third polar plate is larger than that of the first conducting layer and the third polar plate.
7. The array substrate of claim 6, wherein at least a portion of the second conductive layer has a width in a direction perpendicular to the extending direction of the cascade trace that is greater than a width of the first conductive layer in the direction perpendicular to the extending direction of the cascade trace, at least a portion of the third plate has a width in the direction perpendicular to the extending direction of the cascade trace that is greater than a width of the first conductive layer in the direction perpendicular to the extending direction of the cascade trace, and the portion of the second conductive layer having the greater width is disposed corresponding to the portion of the third plate having the greater width.
8. The array substrate of claim 6, further comprising a first transparent conductive layer and a second transparent conductive layer, wherein the first transparent conductive layer comprises one of a pixel electrode and a common electrode, the second transparent conductive layer comprises the other of the pixel electrode and the common electrode, and the first transparent conductive layer is located on a side of the second transparent conductive layer close to the second metal layer;
the first transparent conducting layer further comprises the second conducting layer, and the second transparent conducting layer further comprises the third polar plate.
9. The array substrate of claim 6, wherein the first metal layer further comprises scan lines and the second metal layer further comprises data lines.
10. The array substrate of claim 2,
for the first stage shift register unit: the grid electrode of the charging transistor receives an initial signal, and the grid electrode of the discharging transistor is connected to the current-stage signal output end of the second-stage shift register unit through the cascade routing;
for the next to last stage shift register cell: the grid electrode of the charging transistor is connected with the current-stage signal output end of the penultimate shift register unit through a cascade routing, and the grid electrode of the discharging transistor receives a reset signal.
11. The array substrate of claim 2, wherein the gate driver circuit further comprises a second clock signal line, the logic module further comprises a pull-down transistor,
the grid electrode of the pull-down transistor is connected with the second clock signal line, the first pole of the pull-down transistor is connected with the second driving signal line, and the second pole of the pull-down transistor is connected with the signal output end of the shift register unit.
12. A display panel comprising the array substrate according to any one of claims 1 to 11.
13. A display device comprising the display panel according to claim 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810005105.4A CN108182921B (en) | 2018-01-03 | 2018-01-03 | Array substrate, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810005105.4A CN108182921B (en) | 2018-01-03 | 2018-01-03 | Array substrate, display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108182921A CN108182921A (en) | 2018-06-19 |
| CN108182921B true CN108182921B (en) | 2020-05-22 |
Family
ID=62549666
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810005105.4A Active CN108182921B (en) | 2018-01-03 | 2018-01-03 | Array substrate, display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108182921B (en) |
Families Citing this family (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113325642B (en) * | 2018-06-29 | 2022-12-30 | 上海中航光电子有限公司 | Array substrate, display panel and display device |
| CN108962181A (en) * | 2018-09-21 | 2018-12-07 | 京东方科技集团股份有限公司 | Shift register, gate driving circuit and display device |
| CN109272921B (en) * | 2018-11-23 | 2022-02-22 | 合肥京东方显示技术有限公司 | Grid driving circuit and driving method thereof, display panel and display device |
| CN109545121B (en) * | 2018-12-30 | 2021-09-21 | 上海创功通讯技术有限公司 | Display screen and equipment |
| US11900884B2 (en) | 2019-08-21 | 2024-02-13 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate having a scan driving circuit with a plurality of shift registers and manufacturing method thereof, display device |
| CN112771601B (en) | 2019-08-21 | 2023-05-23 | 京东方科技集团股份有限公司 | Display substrate, display device and manufacturing method of display substrate |
| KR20220100790A (en) * | 2019-11-20 | 2022-07-18 | 보에 테크놀로지 그룹 컴퍼니 리미티드 | Display substrate, manufacturing method thereof, and display device |
| CN110910766A (en) * | 2019-11-27 | 2020-03-24 | 上海天马微电子有限公司 | Display module and display device |
| CN113939866B (en) * | 2020-03-16 | 2023-04-14 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method and display device |
| CN111384066B (en) * | 2020-03-19 | 2022-03-08 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN211669478U (en) * | 2020-03-25 | 2020-10-13 | 北京京东方光电科技有限公司 | Array substrate, display panel and display device |
| EP4134943A4 (en) * | 2020-04-10 | 2023-05-31 | BOE Technology Group Co., Ltd. | Display substrate, manufacturing method therefor, and display apparatus |
| WO2021217546A1 (en) * | 2020-04-30 | 2021-11-04 | 京东方科技集团股份有限公司 | Display substrate and manufacturing method therefor, and display device |
| CN111583793B (en) * | 2020-05-12 | 2021-09-24 | 武汉华星光电半导体显示技术有限公司 | Flexible display screen |
| CN113838404B (en) | 2020-06-24 | 2023-01-24 | 京东方科技集团股份有限公司 | Display substrate and display device |
| TWI735304B (en) * | 2020-08-05 | 2021-08-01 | 友達光電股份有限公司 | Pixel array substrate |
| CN112435629B (en) * | 2020-11-24 | 2023-04-18 | 京东方科技集团股份有限公司 | Display substrate and display device |
| US20230360579A1 (en) * | 2020-12-04 | 2023-11-09 | Hefei Boe Display Technology Co., Ltd. | Display panel and electronic device |
| CN115176302A (en) | 2020-12-23 | 2022-10-11 | 京东方科技集团股份有限公司 | Display panel and display device |
| TWI767701B (en) * | 2021-05-13 | 2022-06-11 | 友達光電股份有限公司 | Circuit substrate and verification method |
| WO2022246756A1 (en) * | 2021-05-27 | 2022-12-01 | 京东方科技集团股份有限公司 | Display substrate and manufacturing method therefor, and display device |
| CN113571021B (en) * | 2021-06-30 | 2023-03-14 | 上海中航光电子有限公司 | Display panel and display device |
| KR20240035937A (en) * | 2021-07-30 | 2024-03-19 | 보에 테크놀로지 그룹 컴퍼니 리미티드 | Pixel driving circuit, driving method, and display panel |
| CN114002885B (en) * | 2021-10-29 | 2023-08-08 | 合肥鑫晟光电科技有限公司 | Array substrate, display panel and display device |
| CN116189622A (en) * | 2021-11-29 | 2023-05-30 | 合肥京东方卓印科技有限公司 | Shift register, gate driving circuit and display substrate |
| CN114283746B (en) * | 2021-12-29 | 2023-05-23 | 上海中航光电子有限公司 | Display panel and display device |
| CN114330214B (en) * | 2022-03-14 | 2022-05-31 | 北京智芯仿真科技有限公司 | Method and device for fast and high-precision calculation of integrated circuit containing routing |
| CN115206997A (en) * | 2022-07-01 | 2022-10-18 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7237444B2 (en) * | 2005-06-29 | 2007-07-03 | Freudenberg-Nok General Partnership | Torque cell for determining a torque load on a rotary member |
| KR101077031B1 (en) * | 2009-08-19 | 2011-10-26 | 주식회사 실리콘웍스 | Data driving circuit and touch screen liquid crystal display device comprising the same |
| TWI442276B (en) * | 2010-11-26 | 2014-06-21 | Innolux Corp | Touch panel |
| CN105280648B (en) * | 2015-09-16 | 2018-06-15 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, display panel and display device |
| CN105807523B (en) * | 2016-05-27 | 2020-03-20 | 厦门天马微电子有限公司 | Array substrate, display panel comprising same and display device |
| CN106547127B (en) * | 2017-01-16 | 2019-10-25 | 上海天马微电子有限公司 | Array substrate, liquid crystal display panel and display device |
| CN106875890B (en) * | 2017-04-27 | 2021-01-12 | 京东方科技集团股份有限公司 | Array substrate, display panel, display device and driving method |
-
2018
- 2018-01-03 CN CN201810005105.4A patent/CN108182921B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN108182921A (en) | 2018-06-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108182921B (en) | Array substrate, display panel and display device | |
| US9653494B2 (en) | Array substrate, display panel and display apparatus | |
| US9478567B1 (en) | Thin-film transistor, array substrate and display apparatus | |
| KR101404542B1 (en) | Liquid crystal display | |
| US20190064256A1 (en) | Test circuit, array substrate and manufacturing method thereof, and display device | |
| US20170316730A1 (en) | Display panels with a gate driver circuit disposed in the active area thereof | |
| US11308834B2 (en) | GOA display panel | |
| US11687193B2 (en) | Display substrate and display device | |
| US10902809B2 (en) | Scan driver circuit, array substrate and display panel | |
| KR20050117057A (en) | Driving apparatus for display device and display panel | |
| US20230154383A1 (en) | Display panel and display device | |
| US9401122B2 (en) | Display panel | |
| CN111624827A (en) | Array substrate, display panel and display device | |
| CN110045881B (en) | Touch control display panel | |
| US20160335975A1 (en) | Array Substrate and Driving Method Thereof, Display Panel, and Display Apparatus | |
| CN108873521B (en) | Array substrate, display panel and display device | |
| EP3696855A1 (en) | Testing circuit, array substrate, display panel and display device | |
| US11705048B2 (en) | Shift register unit, circuit structure, gate drive circuit, drive circuit and display device | |
| CN111610676B (en) | Display panel, driving method thereof and display device | |
| US11594184B2 (en) | Display substrate and manufacturing method thereof, display device | |
| CN109983528B (en) | Shift register circuit, driving circuit, display device and driving method | |
| CN100543534C (en) | Shift register and liquid crystal indicator | |
| CN110476199B (en) | Display panel and display device | |
| US11133334B2 (en) | Array substrate with stacked gate lines, manufacturing method thereof, and display device with stacked gate lines | |
| CN108594552B (en) | Display substrate, display panel, display device and driving method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |