TWI767701B - Circuit substrate and verification method - Google Patents

Abstract

The circuit substrate is provided with multiple mounting regions, and the multiple mounting regions are utilized to mount light-emitting elements. The circuit substrate includes a trace layer and a wire layer. The trace layer includes multiple traces respectively corresponding to the multiple mounting regions and a common electrode. The wire layer includes multiple wires which are disposed in the multiple mounting regions respectively, and the light-emitting elements are electrically coupled in series through the multiple wires in the same mounting region. The circuit substrate is provided with wires arranged in specific sites to determine whether the abnormal short circuit is between the wires and the traces during a detection stage.

Description

Circuit board and detection method

The present application relates to a circuit board and a detection method, and in particular, to a circuit board and a detection method that can detect whether there is an abnormal short circuit.

A backlight panel of a current display usually includes a plurality of light-emitting elements and a circuit substrate on which the light-emitting elements are mounted. In the manufacturing process of the backlight panel, before installing the light-emitting element on the circuit substrate, the array of the circuit substrate can be inspected, so as to improve the quality of the circuit substrate and reduce the overall process cost of the display.

The present disclosure provides a circuit substrate. The circuit substrate has a plurality of installation areas, which are suitable for installation of a plurality of light-emitting elements. The circuit substrate includes a wiring layer and a wire layer. The wiring layer includes a plurality of wires and a common electrode, wherein the wires and the common electrodes extend along the first direction, and the wires include a plurality of first wires, a plurality of second wires and a plurality of third wires Traces. The first wirings are arranged adjacent to the common electrodes. The third wires are arranged between the first wires and the third wires. The wire layer includes a plurality of wires, wherein the wires are respectively disposed in the installation areas, and each of the installation areas includes a first wire, a plurality of second wires separated from each other, at least one third wire wire and a fourth wire. The first wire extends along the second direction and is electrically coupled to the common electrode, wherein the first wire spans the first wires. A plurality of second wires separated from each other extend along the second direction, wherein the second wires span the second wirings. At least one third wire extends along the first direction. The fourth wire extends along the second direction, and the fourth wire is electrically coupled to a corresponding one of the wires.

The present disclosure provides another circuit substrate. The circuit substrate has a plurality of installation areas, which are suitable for installation of a plurality of light-emitting elements, and the circuit substrate includes a wiring layer and a wire layer. The wiring layer includes a plurality of wirings and common electrodes, wherein the wirings and the common electrodes extend along the first direction. The traces include a plurality of first traces, a plurality of second traces and a plurality of third traces. A plurality of first traces are arranged adjacent to the common electrode. A plurality of third wirings, wherein the second wirings are arranged between the first wirings and the third wirings. The wire layer includes a plurality of wires, wherein the wires are respectively disposed in the installation areas, and each of the installation areas includes a first wire, a plurality of second wires separated from each other, a third wire, and Fourth wire. The first wire extends along the second direction and is electrically coupled to the common electrode, wherein the first wire spans the first wires and the second wires. A plurality of second wires separated from each other extend along the first direction. The third wires extend along the second direction and cross the second wires. The fourth wire extends along the second direction, and the fourth wire is electrically coupled to a corresponding one of the wires.

To sum up, the circuit substrate provided by the present disclosure has specific arrangement positions of the wires, so that it can be determined whether there is an abnormal short circuit between the wires and the wires in the detection stage.

The following examples are described in detail in conjunction with the accompanying drawings, but the provided examples are not intended to limit the scope of the present disclosure, and the description of the structure and operation is not intended to limit its execution order. The structure and the resulting device with equal efficacy are all within the scope of the present disclosure. In addition, the drawings are for illustrative purposes only, and are not drawn according to the original size. For ease of understanding, the same or similar elements in the following description will be described with the same symbols.

The terms used throughout the specification and the scope of the patent application, unless otherwise specified, generally have the ordinary meaning of each term used in the field, in the content disclosed herein and in the specific content.

In addition, the terms "comprising", "including", "having", "containing" and the like used in this document are all open-ended terms, ie, meaning "including but not limited to". In addition, the term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

In this document, when an element is referred to as being "coupled" or "coupled," it may be referred to as "electrically coupled" or "electrically coupled." "Coupled" or "coupled" may also be used to indicate the cooperative operation or interaction between two or more elements. In addition, although terms such as "first", "second", . . . are used herein to describe different elements, the terms are only used to distinguish elements or operations described by the same technical terms.

In some embodiments, in order to make the picture displayed on the display closer to the real world observed by human eyes, the High Dynamic Range (HDR) technology makes the display picture brighter through the local dimming of the local backlight module. Case contrast is more obvious and dark state details are clearer. The local backlight module can be realized by one glass substrate, or by a few (for example, two) glass substrates, so as to reduce splicing dark lines. The regional dimming of the local backlight module needs to control the light-emitting elements in zones, so as to achieve the regional dimming of the local backlight module. For example, if a circuit substrate has 1152 light-emitting elements, the 1152 light-emitting elements are divided and arranged in 288 installation areas respectively. One installation area is used for arranging 4 light-emitting elements, and the light-emitting elements in the 288 installation areas are respectively driven through 288 driving circuits, so as to control the brightness of the light-emitting elements in the 288 installation areas respectively. However, in order to control the brightness of the light-emitting elements in each installation area, each row of the circuit substrate will be provided with wires corresponding to the number of installation areas in one row, so as to provide the respective potentials of each installation area, so as to achieve local adjustment. Light. Therefore, the installation area adjacent to the installation position of the driving circuit will contain a large number of wires, and some wires used to connect the light-emitting elements in the installation area will cross these wires. Therefore, the present disclosure provides specific wires. The circuit substrate and the detection method are configured to detect whether the above-mentioned wirings and wires are short-circuited.

Please refer to FIG. 1A . FIG. 1A is a schematic diagram of a top view of a circuit substrate 100 a according to the present disclosure. The circuit substrate 100a includes a plurality of traces NL, a common electrode Pc, and an installation area IA. The wires WP, W1, W2 and W3 included in the mounting area IA are used to electrically connect the four light-emitting elements 10 in series and electrically couple the four light-emitting elements 10 to the common electrode Pc. After the light-emitting element 10 is installed, each of the plurality of wires NL is used to transmit the corresponding data voltage to the corresponding installation area, so that the light-emitting element 10 in each installation area IA can be displayed at the corresponding brightness, Thereby, the regional dimming of the local backlight module is achieved. In the following embodiments, how the arrangement of the plurality of wires NL transmits the corresponding data voltage to the corresponding installation area IA will be described in detail.

In the embodiment shown in FIG. 1A , the circuit substrate 100 a is used for mounting 1152 light-emitting elements 10 , and each mounting area IA in the circuit substrate 100 a is used for mounting four light-emitting elements 10 . That is, the circuit board 100a has 288 mounting areas IA. The 288 mounting areas IA in the circuit board 100a are arranged in a matrix of 18×16. The four light-emitting elements arranged in each mounting area IA are arranged in a matrix of 2 rows×2 columns. FIG. 1A only shows the mounting area IA in the first row to the fourth row and two columns in the circuit substrate 100a. The light-emitting element 10 may be implemented by a light-emitting diode. For example, the light emitting element 10 may be a micro light emitting diode (micro-LED), a sub-millimeter light emitting diode (mini-LED), or a general light emitting diode larger in size than a sub-millimeter light emitting diode.

In other embodiments, the light-emitting elements 10 arranged in the same installation area IA may be implemented by other numbers. For example, two light-emitting elements 10 are arranged in a matrix of 1 row×2 columns. Alternatively, the six light-emitting elements 10 are arranged in a matrix of 3 rows by 2 columns. Therefore, at least two of the light-emitting elements 10 can be disposed in the installation area IA. In addition, the mounting area IA and the light-emitting elements 10 included in the circuit board 100a may also be implemented in other numbers and arrangements. Therefore, FIG. 1A is for illustration only, and the number and arrangement of the mounting areas IA and the light-emitting elements 10 are not limited.

Please also refer to FIG. 1B. FIG. 1B is a schematic diagram of the mounting area IA in the first row and the first column of the circuit board 100a in FIG. 1A. As shown in FIG. 1B , the installation area IA includes wires WP, W1 , W2 , W3 , and WN, a plurality of wires NL, and a common electrode Pc. A plurality of wires NL and a common electrode Pc are arranged on the wire layer, and a plurality of wires WP, W1, W2, W3 and WN are arranged on the wire layer. The wire layer is different from the wire layer, and the wire layer is arranged between the wire layers. superior. In addition, each mounting area IA of the circuit substrate 100a includes wires WP, W1, W2, W3, WN and a common electrode Pc. The plurality of traces NL and the common electrode Pc extend along the first direction D1. The plurality of traces NL include traces N1 to N18, and the traces N1 to N18 are electrically isolated from each other. The plurality of traces NL are sequentially arranged as traces N1 to N18 from bottom to top.

It should be noted that, in the embodiment shown in FIG. 1A and FIG. 1B , the driving circuit for driving the light-emitting element 10 driven by each mounting area IA through the plurality of traces NL and the common electrode Pc is provided on the circuit substrate 100 a Therefore, the traces N1 to N18 of the 18 installation areas IA in the same column should be sequentially decreasing from left to right.

That is to say, the circuit substrate 100a has traces N1-N18 in each mounting area IA in the first row; the circuit substrate 100a has traces N2-N18 in each mounting area IA in the second row; The circuit substrate 100a has traces N3-N18 in each mounting area IA in the third row, and so on.

Please refer to FIG. 1C. FIG. 1C is a schematic diagram of the mounting area IA in the 17th row and the 1st column of the circuit board 100a in FIG. 1A. As shown in FIG. 1C , the wiring layer of the mounting area IA in the 17th row and the 1st column on the circuit substrate 100a only has the traces N17 and N18 and the common electrode Pc, but does not have the traces N1-N16.

In addition, in the mounting area IA in the same row of the circuit substrate 100a, the plurality of wires NL (the wires N1-N18) are respectively electrically connected to the wires WN of each of the 18 mounting areas IA. In this way, the wires WN of each of the 18 mounting areas IA in the same row of the circuit substrate 100a are electrically connected to the wires N1-N18, respectively.

In other words, the wires WN in the installation area IA in the first row are electrically connected to the wires N1 in the same column, the wires WN in the installation area IA in the second row are electrically connected to the wires N2 in the same row, and the installation area in the third row is electrically connected to the wires N2 in the same row. The wires WN in the area IA are electrically connected to the wires N3 in the same column, and so on, and the wires WN in the installation area IA of the eighteenth row are electrically connected to the wires N18 in the same row.

Therefore, in the 18 installation areas in the same row of the circuit substrate 100a, the wires N1-N18 are respectively electrically connected to the respective wires WN in the 18 installation areas IA. In addition, the wires WP of each installation area IA are electrically connected to the common electrode Pc. In this way, after the light-emitting elements 10 are mounted on the circuit substrate 100a, the light-emitting elements 10 in the same mounting area IA will be electrically connected in series with each other through the wires WP, W1, W2, W3 and WN and can pass through the circuit substrate 100a receives current and emits light.

Moreover, after the light-emitting element 10 is installed, each of the traces N1 to N18 is used to transmit the corresponding data voltage to the corresponding one of the 18 installation areas, so that the light-emitting element 10 in each installation area IA can be Display at the corresponding brightness, thereby achieving regional dimming of the local backlight module.

In some embodiments, when the wires N1-N18 are electrically connected to the negative poles of the external power supply and the common electrode Pc is electrically connected to the positive poles of the external power supply, the electrical properties of the wires WN are negative and the electrical properties of the wires WP are positive. On the other hand, when the wires N1 to N18 are electrically connected to the positive pole of the external power supply, and the common electrode Pc is electrically connected to the negative pole of the external power supply, the electrical property of the wire WN is positive, and the electrical property of the wire WP is negative.

It is worth noting that the wiring layer is different from the wiring layer so that the plurality of wires WP, W1, W2 and W3 are electrically isolated from the plurality of wires N1~N18; the common electrode Pc is electrically isolated from the plurality of wires N1~N18 Isolation: the wire WN is electrically isolated from the traces N1~N18 other than one of the traces N1~N18 to which it is electrically connected. However, in some cases, one of the wires WP, W1, W2, W3, and WN in the wire layer is generated by short-circuiting one of the wires N1-N18 with tiny particles (eg, particles of 6μ or 10μ) and one of the wires N1-N18. abnormal. At this time, if the abnormality of the circuit board 100a is detected before the light-emitting element 10 is installed, the circuit board 100a can be replaced before the light-emitting element 10 is installed, or the circuit board 100a can be adjusted to eliminate the abnormality, thereby reducing the overall display panel. Process cost. In the present disclosure, how to detect the abnormality of short circuit between one of the wires WP, W1, W2, W3 and WN and one of the wires N6-N16 and the execution of the detection method will be described in the following embodiments.

As shown in FIG. 1B , on the projection plane, the zone Z1 is between the plurality of wires Na and Nb, the zone Z2 is between the plurality of wires Nb and Nc, and the zone Z3 is between the zones Z1 and Z2. In addition, the plurality of wires Na include wires N1 to N5; the plurality of wires Nb include wires N6 to N16; and the plurality of wires Nc include wires N17 to N18. In other words, the zone Z1 is between the traces N5 and N6, the zone Z2 is between the traces N16 and the traces N17, and the zone Z3 includes the traces N6 to N16. The wires WP1, WP2, and WP3 each have two pads P1 and two pads P2. The wire WP has two pads P1. The wire WN has two pads P2. All the above-mentioned pads P1 and P2 are arranged in the zones Z1 and Z2. After the light-emitting element 10 is mounted on the circuit substrate 100a, the anode of the light-emitting element 10 can be electrically connected to the pads P1 of the wires WP, W3, W2 and W1, respectively, and the cathode of the light-emitting element 10 can be electrically connected to the wires W3, W2, respectively. , W1 and WN pads P2.

As shown in FIG. 1A and FIG. 1B , the pads P1 and P2 connected to the light-emitting element 10 are arranged horizontally (eg, along the first direction D1 ) respectively and are arranged at different positions in the zones Z1 and Z2 . Between the zones Z1 and Z2 where the pads P1 and P2 are arranged, there is another zone Z3 extending horizontally (eg, along the first direction D1 ), and the zone Z3 is used to set the horizontal direction (eg, along the first direction D1 ) For the signal traces N6-N16, in some embodiments, the zones Z1 and Z2 are pad setting areas (used to connect the light-emitting element 10 in FIG. 1A ), and the zone Z3 is used as a jumper area.

Specifically, four light-emitting elements 10 are arranged in one installation area IA, and the anode and the cathode of the first light-emitting element 10 are electrically connected to the pads P1 of the wire WP and the pads P2 of the wire W1, respectively. The anode and the cathode of the second light-emitting element 10 are respectively electrically connected to the pad P1 of the wire W1 and the pad P2 of the wire W2. The anode and the cathode of the third light-emitting element 10 are electrically connected to the pad P1 of the wire W2 and the pad P2 of the wire W3, respectively. The anode and the cathode of the fourth light-emitting element 10 are respectively electrically connected to the pad P1 of the wire W3 and the pad P2 of the wire WN. Therefore, the anodes and cathodes of each light-emitting element 10 are electrically connected to the adjacent pads P1 and P2 respectively, so that the light-emitting elements 10 in the same mounting area IA can be connected via the wires WP, W3, W2, W1 and WN. and are electrically connected in series with each other.

It should be noted that since the wires W1, W2 and W3 each have two pads P1 and two pads P2, the wire WP has two pads P1, and the wire WN has two pads P2, so the same installation area Eight light-emitting elements 10 can be installed in the IA. In some embodiments, only four light-emitting elements 10 are installed in each mounting area IA, so part of the pads P1 and part of the pads P22 are not electrically connected to any light-emitting elements 10 .

It can be seen from this that each of the wires W1, W2 and W3 has at least one pad P1 and one pad P2. The wire WP has at least one pad P1. Conductor WN has at least one pad P2. Therefore, the number of the pads P1 and P2 shown in FIG. 1B is reduced, and the above number of the pads P1 and the number of the pads P2 are not limited.

In detail, the first end of the wire WP is electrically connected to the common electrode Pc, and the pad P1 of the wire WP is disposed in the zone Z1, so that the wire WP extends along the second direction D2 and spans the traces N1-N5. The first end of the wire WN is electrically connected to the wire N1, and the pad P2 of the wire WN is disposed in the zone Z1, so that the wire WN extends along the second direction D2 and spans the wires N2-N5.

The pads P2 of the wire W1 are arranged in the zone Z1, and the pads P1 of the wires W1 are arranged in the zone Z2, so that the wires W1 extend along the second direction D2 and span the traces N6-N16. The pads P1 and P2 of the wire W2 are both disposed in the zone Z2, so that the wire W2 extends along the first direction D1. The pad P1 of the wire W3 is set in the zone Z1, and the pad P2 of the wire W3 is set in the zone Z2, so that the wire W3 extends along the second direction D2 and spans the traces N6-N16.

It should be noted that, before the light-emitting element 10 is installed, the wires W1 , W2 and W3 are all floating wirings. That is, even if a detection voltage is applied to the traces N1-N18 and the common electrode Pc, in an ideal situation, the potentials of the wires W1, W2 and W3 should not change substantially, and the wires W1, W2 and W3 are floating. state. In other words, in an ideal situation, before installing the light-emitting element 10 , the wires W1 , W2 and W3 are floating wires.

It should be noted that, in the installation area IA of the circuit board 100a shown in FIG. 1C in the 17th row and the 1st column, the wiring layer only has the wirings N17-N18, but does not have the wirings N1-N16 . In other words, in the installation area IA of the 17th row and the 1st column of the circuit board 100a, there are no traces N1-N16 in the zone Z3. Therefore, in the mounting area IA of the 17th row and the 1st column of the circuit substrate 100a, the wires WN in the wire layer are electrically coupled to the traces N17 without crossing the traces N1-N16.

In this way, when the wires WP, WN, W1, W2 and W3 are arranged at specific positions, all the wires WN in each mounting area IA of the circuit substrate 100a will not cross the wires N6-N16.

Before installing the light-emitting element 10, in order to detect whether one of the wires WP, W1, W2, and W3 in the wire layer is abnormally short-circuited with one of the wires N6-N16, a detection process S200 is performed. See Figure 2. FIG. 2 is a schematic diagram of a detection process S200 according to an embodiment of the present disclosure. FIG. 2 includes steps S210, S220, S230, S240, S241, S242, and S243. In some embodiments, steps S210-S240 may be implemented by electron beam inspection (Electrons Beam inspection; EBI) or by a voltage imaging optical system (Voltage Imaging optical subsystem; VIOS) of PDI Corporation.

In step S210, a first detection voltage is applied to the common electrode Pc. And, in step S220, the second detection voltage is applied to the wires N1-N18. The first detection voltage is different from the second detection voltage, and the absolute value of the first detection voltage is greater than the absolute value of the second detection voltage.

In step S230, the brightness of the pads P1 and P2 of the wires WP, W1, W2, W3 and WN, respectively, is detected by the liquid crystal detection cell. In this step, continuing the operation of step S210, maintaining the application of the first detection voltage to the common electrode Pc and the application of the second detection voltage to the traces N1-N18, and disposing the liquid crystal detection cell on the circuit substrate 100a. In this way, the liquid crystal in each pixel of the liquid crystal detection cell is deflected according to the potential/electric field on the circuit substrate 100a (for example, the wire WP receiving the first detection voltage and the wire WN receiving the second detection voltage), so the liquid crystal detection cell The detection screen will be displayed corresponding to the magnitude of the potential/electric field at each position in the circuit substrate 100a. In other words, the detection screen displayed by the liquid crystal detection box will show different brightness according to the magnitude of the potential/electric field at each position in the circuit substrate 100a. /grayscale.

For example, in the detection screen displayed by the liquid crystal detection box, the pad P1 of the wire WP is at the first expected value, and the pad P2 of the wire WN is at the second expected value. Since the absolute value of the second detection voltage is greater than the absolute value of the first detection voltage, the first expected value is greater than the second expected value. In addition, in the following embodiments, the brightness presented by the pad P1 of the wire WP receiving the first detection voltage through the liquid crystal detection cell is regarded as the first expected value (for example, white), and the wire WN receiving the second detection voltage is regarded as the first expected value. The brightness presented by the pad P2 through the liquid crystal detection cell is regarded as the second expected value (eg, gray), and the brightness presented by the pads P1 and P2 of the wires W1 and W3 that theoretically do not receive voltage through the liquid crystal detection cell Treated as the third expected value (eg, black).

In step S240, it is determined whether the brightness of the respective pads P1 and P2 of the wires W1 and W3 in the detection screen is at a third expected value. In this step, since the first detection voltage and the second detection voltage are respectively applied to the common electrode Pc and the wires N1-N18 in the steps S210 and S220, if the wire W1 and the wire W3 in one installation area IA are among the One is abnormally short-circuited with one of the traces N6-N16, and the second detection voltage is transmitted to one of the wire W1 and the wire W3 through one of the above-mentioned traces N6-N16, so that the wire W1 and the wire W3 are among the The potential of one rises. At this time, the brightness of the pads P1 and P2 of one of the wire W1 and the wire W3 in the detection screen will be different from the third expected value (eg, black).

In other words, if the circuit substrate 100a is not abnormally short-circuited but is in an ideal state, the brightness of the pad P1 of the wire WP in the detection screen should be the first expected value (eg, white), and the pad P2 of the wire WN in the detection screen. should be the second expected value (eg, gray), and the brightness of the pads P1 and P2 of the wires W1, W2 and W3 in the detection screen should be the third expected value (eg, black).

Therefore, assuming that the wire W3 and the wire N15 are abnormally short-circuited, the second detection voltage is transmitted to the wire W3 through the wire N15. At this time, in the detection screen displayed by the liquid crystal detection cell, the brightness of the pads P1 and P2 of the wire W3 will be different from the third expected value (for example, black), and may display the second expected value (for example, gray) or less than a second expected value (eg, dark gray).

In other embodiments, the brightness of the pads P1 and P2 of one of the wire W1 and the wire W3 in the detection screen will be different from that of the pads P1 and P2 of the IA wire W1 and the wire W3 in the other installation areas during the detection The brightness of the screen is used to determine whether one of the wires W1 and W3 is abnormally short-circuited with one of the wires N6 to N16.

For example, if the brightness of the pads P1 and P2 of the wire W1 in one installation area IA in the detection screen is different from the brightness of the pads P1 and P2 of the wire W1 in the other installation area IA in the detection screen, then It is judged that there is an abnormal short circuit between the wire W1 and one of the traces N6~N16. In this way, the circuit substrate 100a can be replaced before the light-emitting element 10 is installed, thereby reducing the cost of the overall process. In addition, qualified circuit substrates 100a can be screened out, thereby improving the yield of the backlight panel and the display.

In other embodiments, the wire W1 and the wire W3 are each formed by a plurality of metal wires in parallel. In the embodiment of the present disclosure, the line width of the metal lines is about 10-30 μm, the distance between two adjacent ones of the metal lines is about 5-15 μm, and the wires W1 and W3 are each formed by about Consists of 10 metal wires. In this way, if it is determined in step S240 that one of the wires W1 and W3 is abnormally short-circuited with one of the wires N6-N16, step S242 can be performed to determine the wires W1 and the wires W1 that are abnormally short-circuited with the wires N6-N16. One of the metal wires of W3.

For example, in step S240, it is determined that one of the wires W1 and the wires N6-N16 in one installation area IA is abnormally short-circuited. Then, use an optical microscope to detect the wire W1 and the wires N6-N16 in the installation area IA through a high-resolution optical image, so as to determine the metal wire in the wire W1 that is abnormally short-circuited with one of the wires N6-N16 . In addition, following step S243, the metal wire in the wire W1 that is abnormally short-circuited with one of the wires N6 to N16 is cut off. The cutting of the metal wire may be implemented by laser cutting.

In this way, even if the wires W1 or W3 pass through tiny particles (for example, particles of 6µm~10µm) and one of the wires N6~N16 is abnormally short-circuited during the process, the steps S210, S220, S230, S240, S242 and S243 can Determine and cut off the metal wire in the wire W1 or W3 that has an abnormal short circuit. Further, since the width of a single metal line can be set to be 10-30 μm, the influence on the resistance of the wire W1 or W3 after cutting the single metal line is less than the change of 0.2 ohms, so it can be ignored. In this way, the circuit substrate 100a can be repaired before installing the light-emitting element 10, thereby reducing the cost of the overall process.

It is worth noting that since the size of each installation area IA in the circuit substrate 100a is much larger than the size of the pixel of the liquid crystal display circuit substrate, it is difficult for an optical microscope to detect the multiple installation areas IA in the circuit substrate 100a at the same time. However, it may only be possible to detect a part of the position of one installation area in the circuit substrate 100a at one time. Therefore, the present disclosure needs to simultaneously detect the wires W1 and W3 and the trace N6 of each installation area IA in the circuit substrate 100a through steps S210-S240. Whether ~N16 is abnormally short-circuited.

In some embodiments, it can also be determined whether the wire WP and the wires N1-N5 are abnormally short-circuited. For example, if the wire WP and the wire N4 are abnormally short-circuited, the first detection voltage is transmitted to the wire N4 through the wire WP. At this time, in the detection screen displayed by the liquid crystal detection box, the brightness of the trace N4 will be different from the second expected value (eg, gray), and may be displayed as the first expected value (eg, white) or less than Brightness/grayscale (eg, light gray) of the first expected value and greater than the second expected value.

In step S230, the liquid crystal detection cell is used to detect the brightness of the screen on the respective pads P1 of all the wires WP on the circuit substrate 100a. If the brightness of the pads P1 of the wires WP in one installation area IA in the detection screen is lower than the brightness of the pads P1 of the wires WP in the other installation areas IA in the detection screen, it is determined that the brightness of the pads P1 in the installation area IA is The wire WP is short-circuited with one of the traces N1 to N5. In this way, qualified circuit substrates 100a can be screened out, thereby improving the yield of the backlight panel and the display.

Please refer to FIG. 3A. FIG. 3A is a schematic diagram of a top view of the circuit substrate 100b according to the present disclosure. FIG. 3A only shows the mounting area IA in the first row to the fourth row and two columns in the circuit substrate 100b. The circuit substrate 100b is used for mounting 1152 light-emitting elements 10 , and each mounting area IA in the circuit substrate 100b is used for mounting four light-emitting elements 10 . The 288 mounting areas IA in the circuit substrate 100b are arranged in a matrix of 18 rows×16 columns, and the four light-emitting elements arranged in each mounting area IA are arranged in a matrix of 2 rows×2 columns. The arrangement of the mounting area IA of the circuit substrate 100b is similar to that of the circuit substrate 100a, and the light-emitting elements 10 to be mounted in the circuit substrate 100b are also similar to the light-emitting elements 10 to be mounted in the circuit substrate 100a, which are not repeated here. Repeat.

Please also refer to FIG. 3B. FIG. 3B is a schematic diagram of the mounting area IA of the circuit board 100b in the first row and the first column. As shown in FIG. 3B, the installation area IA includes wires WP, W1, W2, W3, and WN, a plurality of wires NL, and a common electrode Pc. The multiple wirings NL and the common electrode Pc are disposed on the wiring layer, and the multiple wirings WL include the wirings N1 to N18. A plurality of wires WP, W1, W2, W3 and WN are arranged on the wire layer, and the wire layer is different from the wiring layer. The arrangement of the wires WP, W1, W2, W3, and WN in Fig. 3B is mirror-symmetrical to the arrangement of the wires WP, W1, W2, W3, and WN in Fig. 1B. In other words, the wires WP, W1, W2, W3 and WN in FIG. 1B are sequentially arranged in the counterclockwise direction from the common electrode Pc to the wiring N1. In FIG. 3B, the wires WP, W1, W2, W3 and WN are sequentially arranged in a clockwise direction from the common electrode Pc to the wiring N1.

In the embodiment shown in FIG. 3A and FIG. 3B, the wires W1 and W3 are also set to cross the wires N6-N16, so it is also possible to determine the difference between the wires W1 and W3 and the wires N6-N16 through steps S210-S230. Whether an abnormal short circuit occurs between them. In addition, the wires W1 and W3 can also each be composed of a plurality of metal wires, so that when an abnormal short circuit occurs between the wires W1 and W3 and the traces N6-N16, the steps S242 and 243 are used to determine and cut off the abnormal short circuit metal wire. , the abnormal short circuit substrate 100b can be repaired before the light-emitting element 10 is installed, thereby improving the yield rate of the backlight panel and the display.

Please refer to FIG. 4A. FIG. 4A is a schematic diagram of a top view of the circuit substrate 100c according to the present disclosure. FIG. 4A only shows the mounting area IA in the first row to the fourth row and two columns in the circuit substrate 100c. The circuit substrate 100c is used for mounting 1152 light-emitting elements 10 , and each mounting area IA in the circuit substrate 100b is used for mounting four light-emitting elements 10 . The 288 mounting areas IA in the circuit substrate 100c are arranged in a matrix of 18 rows×16 columns, and the four light-emitting elements arranged in each mounting area IA are arranged in a matrix of 2 rows×2 columns. The arrangement of the mounting area IA of the circuit substrate 100c is similar to that of the circuit substrate 100a, and the light-emitting element 10 to be mounted in the circuit substrate 100c is also similar to the light-emitting element 10 to be mounted in the circuit substrate 100a, which is not repeated here. Repeat.

Please also refer to FIG. 4B. FIG. 4B is a schematic diagram of the mounting area IA of the circuit board 100c in the first row and the first column. As shown in FIG. 4B , the installation area IA includes wires WP, W1 , W2 , W3 and WN, a plurality of wires NL and a common electrode Pc. The multiple wirings NL and the common electrode Pc are disposed on the wiring layer, and the multiple wirings NL include the wirings N1 to N18. A plurality of wires WP, W1, W2, W3 and WN are arranged on the wire layer, and the wire layer is different from the wiring layer. Moreover, on the projection plane, the interval Z1 is between the route N5 and the route N6, and the interval Z2 is between the route N16 and the route N17. Zone Z3 is between zones Z1 and Z2.

Compared with the circuit substrate 100a of the embodiment of FIG. 1B, the circuit substrate 100c of the embodiment of FIG. 4B is different in the arrangement of the wires WP, WN, W1, W2 and W3.

In detail, in the circuit substrate 100c shown in FIG. 4B, the first end of the wire WP is electrically connected to the common electrode Pc, and the pad P1 of the wire WP is arranged in the zone Z2, so that the wire WP extends along the second direction D2 And it crosses the traces N1~N5 and the traces N6~N16. The first end of the wire WN is electrically connected to the wire N1, and the pad P2 of the wire WN is disposed in the zone Z1, so that the wire WN extends along the second direction D2 and spans the wires N2-N5. The pads P1 and P2 of the wire W1 are arranged in the zone Z2, so that the wire W1 extends along the first direction D1. The pad P2 of the wire W2 is set in the zone Z2, and the pad P1 of the wire W2 is set in the zone Z1, so that the wire W1 extends along the second direction D2 and spans the traces N6-N16. The pads P1 and P2 of the wire W3 are arranged in the zone Z2, so that the wire W3 extends along the second direction D2.

Before installing the light-emitting element 10, in order to detect whether one of the wires WP, W1, W2, W3 and WN in the wire layer of the circuit substrate 100c is abnormally short-circuited with one of the plurality of wires N6-N16, the The detection flow S200 shown in FIG. 2 is performed. The detection flow S200 in FIG. 2 includes steps S210 , S220 , S230 , S240 , S241 , S242 and S243 .

In step S210, a first detection voltage is applied to the common electrode Pc. And, in step S220, the second detection voltage is applied to the wires N1-N18. The first detection voltage is different from the second detection voltage, and the absolute value of the first detection voltage is greater than the absolute value of the second detection voltage.

In step S230, the brightness of the pads P1 and P2 of the wires WP, W1, W2, W3 and WN, respectively, is detected by the liquid crystal detection cell. In this step, continuing the operation of step S210, maintaining the application of the first detection voltage to the common electrode Pc and the application of the second detection voltage to the traces N1-N18, and disposing the liquid crystal detection cell on the circuit substrate 100c. In this way, the liquid crystal in each pixel of the liquid crystal detection cell is deflected according to the potential/electric field on the circuit substrate 100c (for example, the wire WP receiving the first detection voltage and the wire WN receiving the second detection voltage), so the liquid crystal detection cell The detection screen is displayed corresponding to the potential/electric field at each position in the circuit substrate 100c. In other words, the detection screen presents different brightness/gray scales according to the potential/electric field at each position in the circuit substrate 100c.

For example, in the detection screen displayed by the liquid crystal detection box, the pad P1 of the wire WP receiving the first detection voltage is at the first expected value, and the pad P2 of the wire WN receiving the second detection voltage is at the second expected value . Since the absolute value of the second detection voltage is greater than the absolute value of the first detection voltage, the first expected value is greater than the second expected value. Moreover, in subsequent embodiments, the brightness displayed by the pad P1 of the wire WP receiving the first detection voltage through the sensing of the liquid crystal detection cell is regarded as the first expected value (eg, white), and the second detection voltage will be received. The brightness displayed by the pad P2 of the wire WN through the sensing of the liquid crystal detection cell is regarded as the second expected value (eg, gray), and the pads P1 and P2 of the wires W1 and W3, which theoretically do not receive voltage, pass through The brightness displayed by the sensing of the liquid crystal cell is regarded as the third expected value (eg, black).

In step S240, it is determined whether the brightness of the pads P1 of the wire WP and the pads P1 and P2 of the wire W2 in the detection screen is at their respective expected values. In this step, since the first detection voltage and the second detection voltage are respectively applied to the common electrode Pc and the wires N1-N18 in the steps S210 and S220, if the wires WP and the wires N6 in one installation area IA are One of the ~N16 is abnormally short-circuited, and the first detection voltage is transmitted to one of the traces N6 to N16 through the wire WP, so that the potential of one of the traces N6 to N16 rises. At this time, the brightness of the pad P1 of the wire WP in the detection screen may be different from the first expected value (eg, white), and may be displayed as the first expected value (eg, gray).

For example, if the wire WP and the wire N12 are abnormally short-circuited, the first detection voltage is transmitted to the wire N12 through the wire WP. At this time, the brightness of the pad P1 of the wire WP may be displayed at a brightness/gray scale (eg, gray) lower than the first expected value in the detection screen.

On the other hand, if the wire W2 and one of the wires N6-N16 in one installation area IA are abnormally short-circuited, the second detection voltage will be transmitted to the wire W2 through one of the wires N6-N16, so that the wire The potential of W2 rises. At this time, the brightness of the pads P1 and P2 of the wire W2 in the detection screen will be different from the second expected value (eg, gray), and may be displayed as the first expected value (eg, white) or less than the first value Brightness/grayscale (eg, light gray) of the expected value and greater than the second expected value.

For example, if the wire W2 and the wire N12 are abnormally short-circuited, the second detection voltage is transmitted to the wire WP through the wire N12. At this time, the brightness of the pad P1 of the wire WP in the detection screen may be displayed as a brightness/gray scale (eg, light gray) that is less than the first expected value and greater than the second expected value.

In other embodiments, the wire WP and the wire W2 are each formed by a plurality of metal wires in parallel. In the embodiment of the present disclosure, the line width of the metal lines is about 10-30 μm, the distance between two adjacent ones of the metal lines is about 5-15 μm, and the wire WP and the wire W2 are each formed by about Consists of 10 metal wires. In this way, if it is determined in step S240 that one of the wires W1 and W3 is abnormally short-circuited with one of the wires N6-N16, step S242 can be performed to determine the wires WP and the wires N6-N16 that are abnormally short-circuited. One of the metal wires of W2.

For example, in step S240, it is determined that the wire WP in one installation area IA is abnormally short-circuited with one of the wires N6-N16. Then, the wire WP and the wires N6-N16 in the installation area IA are detected by an optical microscope to determine the metal wire in the wire WP that is abnormally short-circuited with one of the wires N6-N16. And, following step S243, the metal wire in the wire WP that is abnormally short-circuited with one of the wires N6-N16 is cut off.

In some embodiments, the detection picture can be captured by an electronic computer, and an algorithm can be run to extract from the detection picture the respective pads P1 and P2 of each wire WP, W1, W2, W3 and WN in the detection picture. screen block, so that the electronic computer is used to run the detection process S200 to automatically determine whether the wires WP, W1, W2, W3 are abnormally short-circuited with the wires N6-N16.

Please refer to FIG. 5A, which is a schematic diagram of a top view of a circuit substrate 100d according to the present disclosure. FIG. 5A only shows the mounting area IA in the first row to the fourth row and two columns in the circuit substrate 100d. The circuit substrate 100 d is used for mounting 1152 light-emitting elements 10 , and each mounting area IA in the circuit substrate 100 d is used for mounting four light-emitting elements 10 . The 288 mounting areas IA in the circuit substrate 100d are arranged in a matrix of 18 rows×16 columns, and the four light-emitting elements arranged in each mounting area IA are arranged in a matrix of 2 rows×2 columns. The arrangement of the mounting area IA of the circuit substrate 100d is similar to that of the circuit substrate 100a, and the light-emitting element 10 to be mounted in the circuit substrate 100d is also similar to the light-emitting element 10 to be mounted in the circuit substrate 100a, which is not repeated here. Repeat.

Please also refer to FIG. 5B. FIG. 5B is a schematic diagram of the mounting area IA of the circuit board 100d in the first row and the first column. As shown in FIG. 5B , the installation area IA includes wires WP, W1 , W2 , W3 and WN, a plurality of wires NL and a common electrode Pc. The multiple wirings NL and the common electrode Pc are disposed on the wiring layer, and the multiple wirings NL include the wirings N1 to N18. A plurality of wires WP, W1, W2, W3 and WN are arranged on the wire layer, and the wire layer is different from the wiring layer. The arrangement of the wires WP, W1, W2, W3 and WN in Fig. 5B is mirror-symmetrical to the arrangement of the wires WP, W1, W2, W3 and WN in Fig. 4B. In other words, the wires WP, W1, W2, W3 and WN in Fig. 5B are sequentially arranged in the counterclockwise direction from the common electrode Pc to the wiring N1. In FIG. 4B, the wires WP, W1, W2, W3 and WN are sequentially arranged in a clockwise direction from the common electrode Pc to the wiring N1.

In the circuit board 100d shown in FIG. 5A and FIG. 5B, the wires WP and W2 still cross the wires N6-N16, so it is also possible to determine the relationship between the wires WP and W2 and the wires N6-N16 through steps S210-S230. Whether an abnormal short circuit occurs between them. In addition, the wires WP and W2 can also be composed of a plurality of metal wires, so that when an abnormal short circuit occurs between WP and W2 and the wires N6-N16, through steps S242 and 243, it is determined and cut off the metal wire with the abnormal short circuit. The abnormally short circuited circuit substrate 100d can be repaired before the light-emitting element 10 is installed, thereby improving the yield of the backlight panel and the display.

It should be noted that, in other embodiments, it is assumed that the wire WN used for receiving the second detection voltage crosses the traces N6-N16 used for receiving the second detection voltage in the zone Z3 (cross-wire zone), no matter Whether an abnormal short circuit occurs between the wire WN and the traces N6 to N16 it crosses, the pad P2 of the wire WN will still meet the second expected value (eg, gray) in the detection screen. That is to say, the pad P2 of the wire WN cannot be set in the zone Z2, but can only be set in the zone Z1, so that the wire WN will not cross the traces N6~N16. In this way, in steps S210~S240, it can be detected for receiving the first Whether a wire WP for detecting the voltage, the floating wire W1, W2 or W3 is abnormally short-circuited with the wires N6-N16 for receiving the second detecting voltage.

In other words, it is assumed that the wire WN in the circuit substrate and the wires N6-N16 in the cross-line area (ie, the zone Z3) are staggered and overlapped at the projected position, and then the wire WN and the wires N6-N16 may be abnormally short-circuited. In addition, since the wire WN and the wires N1-N18 both receive the second detection voltage in step S220, even if the pad P2 of the wire WN and the wires N6-N16 are abnormally short-circuited, the detection screen displayed through the liquid crystal detection box will not be detected. The pad P2 of the wire WN will still meet the second expected value (eg, gray) and pass the test, and it is impossible to distinguish whether the pad P2 of the wire WN receives the correct second detection voltage on the trace N1 or abnormally receives the wire. The second detection voltage on lines N6~N16.

At this time, if the circuit board in which the abnormal short-circuit has occurred is shipped normally, the light-emitting element 10 may receive an erroneous driving voltage. Therefore, as shown in Figures 1B, 3B, 4B and 5B in the above-mentioned embodiments of the present disclosure, the wire WN and the plurality of wires Nb (for example, wires N6-N16) located in the jumper region (ie, the zone Z3) ) do not overlap in the projected position, so that the wires WN and the wires N6-N16 do not have abnormal short circuits that cannot be detected by steps S210-S240, and the wires for receiving the first detection signal can be detected by steps S210-S240 Whether the WP or the floating wires W1, W2, W3 are abnormally short-circuited with the traces Nb (such as traces N6-N16) in the cross-line area (ie, the zone Z3), so that the light-emitting element 10 can be filtered out before installing the light-emitting element 10. A circuit board with an abnormal short circuit between wires.

To sum up, the circuit substrates 100a, 100b, 100c and 100d provided by the present disclosure have specific arrangement positions of the wires WP, WN, W1, W2 and W3. Since the wire WN receives the same second detection signal as that received by the wires N1~N18 in the detection stage, if the wire WN is set to cross the wires N6~N16, it is impossible to judge the wire WN and the wires N6~N16 in the detection stage. Whether there is an abnormal short circuit between them. Therefore, the specific arrangement positions of the wires WP, WN, W1, W2 and W3 in the circuit substrates 100a, 100b, 100c and 100d make the arrangement of the wires WN not overlap the wires N6 to N16 in the zone Z3 (cross-wire zone), so that the In the detection stage, it can be judged whether there is an abnormal short circuit between the wires WP, W1, W2 or W3 and the traces N6~N16.

Although the present disclosure has been disclosed as above in embodiments, it is not intended to limit the present disclosure. Anyone with ordinary knowledge in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. The scope of protection disclosed shall be determined by the scope of the appended patent application.

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more clearly understood, the descriptions of the appended symbols are as follows: 100a, 100b, 100c, 100d: circuit board 10: Light-emitting elements IA: Installation area WP,WN,W1,W2,W3: Wire NL,Na,Nb,Nc: Multiple traces N1~N18: wiring Pc: common electrode P1, P2: pads Z1~Z3: interval D1: first direction D2: Second direction S200: Detection process S210, S220, S230, S240, S241, S242, S243: Steps

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more clearly understood, the accompanying drawings are described as follows: FIG. 1A is a schematic diagram of a top view of a circuit substrate according to the present disclosure. FIG. 1B is a schematic diagram of the installation area of the circuit board in the first row and the first column in FIG. 1A . FIG. 1C is a schematic diagram of the mounting area IA of the circuit board in the 17th row and the 1st column of the circuit board in FIG. 1A . FIG. 2 is a schematic diagram of a detection process according to an embodiment of the present disclosure. FIG. 3A is a schematic diagram of a top view of a circuit substrate according to the present disclosure. FIG. 3B is a schematic diagram of the installation area of the circuit board in the first row and the first column in FIG. 3A . FIG. 4A is a schematic diagram of a top view of a circuit substrate according to the present disclosure. FIG. 4B is a schematic diagram of the installation area of the circuit board in the first row and the first column in FIG. 4A . FIG. 5A is a schematic diagram of a top view of a circuit substrate according to the present disclosure. FIG. 5B is a schematic diagram of the installation area of the circuit board in the first row and the first column in FIG. 5A .

Domestic storage information (please note in the order of storage institution, date and number) none Foreign deposit information (please note in the order of deposit country, institution, date and number) none

100a: circuit substrate

10: Light-emitting elements

WP,WN,W1,W2,W3: Wire

NL,Na,Nb,Nc: Multiple traces

N1~N18: wiring

Pc: common electrode

P1, P2: pads

Z1~Z3: interval

D1: first direction

D2: Second direction

Claims (11)

A circuit substrate, which has a plurality of installation areas, is suitable for installation of a plurality of light-emitting elements, and the circuit substrate comprises: A wiring layer includes a plurality of wirings and a common electrode, wherein the wirings and the common electrode extend along a first direction, and the wirings include: a plurality of first traces arranged adjacent to the common electrode; a plurality of second wires, wherein the first wires are arranged between the second wires and the common electrode; and a plurality of third wires, wherein the second wires are arranged between the first wires and the third wires; A conductor layer includes a plurality of conductors, wherein the conductors are respectively arranged in the installation areas, and one of the installation areas includes: a first wire extending along a second direction and electrically coupled to the common electrode, wherein the first wire spans the first wires; a plurality of second wires separated from each other extending along the second direction, wherein the second wires span the second wirings; at least one third wire extending along the first direction; and A fourth wire extends along the second direction, and the fourth wire is electrically coupled to a corresponding one of the wires. The circuit substrate according to item 1, wherein one of the mounting areas is used for mounting a first light-emitting element, a second light-emitting element, a third light-emitting element and a fourth light-emitting element, the first light-emitting element The light-emitting element, the second light-emitting element, the third light-emitting element and the fourth light-emitting element are connected in series with each other through the first wire, the second wires and the third wire. The circuit substrate of item 1, wherein the fourth wire does not overlap the second wires. The circuit substrate of item 1, wherein when the common electrode receives a first detection voltage and the traces receive a second detection voltage, the second wires are in a floating state, wherein the first The detection voltage is different from the second detection voltage. The circuit substrate according to item 1, wherein each of the second wires is formed of a plurality of metal wires in parallel. A detection method for detecting the circuit substrate as claimed in claim 5, the detection method comprising: applying a first detection voltage to the common electrode; applying a second detection voltage to the traces, wherein the second detection voltage is different from the first detection voltage; A detection screen is displayed by a liquid crystal detection box according to the potentials of the respective pads of the wires; judging whether the brightness of the respective pads of the second wires in the detection screen is at the expected value; if the brightness of the pad of one of the second wires in the detection screen is different from the expected value; Determining one of the metal wires among the second wires that are short-circuited with one of the wires; and The one of the metal wires of the one of the second wires that is shorted to the one of the traces is cut off. A detection method for detecting the circuit substrate as claimed in claim 1, the detection method comprising: applying a first detection voltage to the common electrode; applying a second detection voltage to the traces, wherein the second detection voltage is different from the first detection voltage; Displaying a detection screen according to the potentials of the respective pads of the wires through a liquid crystal detection box; and It is judged whether the brightness of the respective pads of the wires in the detection screen is at the expected value. A circuit substrate, which has a plurality of installation areas, is suitable for installation of a plurality of light-emitting elements, and the circuit substrate comprises: A wiring layer includes a plurality of wirings and a common electrode, wherein the wirings and the common electrode extend along a first direction, and the wirings include: a plurality of first traces arranged adjacent to the common electrode; a plurality of second wires, wherein the first wires are arranged between the second wires and the common electrode; and a plurality of third wires, wherein the second wires are arranged between the first wires and the third wires; A conductor layer includes a plurality of conductors, wherein the conductors are respectively arranged in the installation areas, and one of the installation areas includes: a first wire extending along a second direction and electrically coupled to the common electrode, wherein the first wire spans the first wires and the second wires; a plurality of second wires separated from each other, extending along the first direction; a third wire extending along the second direction and crossing the second wires; and A fourth wire extends along the second direction, and the fourth wire is electrically coupled to a corresponding one of the wires. The circuit substrate according to item 8, wherein one of the mounting areas is used for mounting a first light-emitting element, a second light-emitting element, a third light-emitting element and a fourth light-emitting element, the first light-emitting element The light-emitting element, the second light-emitting element, the third light-emitting element and the fourth light-emitting element are connected in series with each other through the first wire, the second wires and the third wire. The circuit substrate of item 8, wherein the fourth wire does not overlap the second wires. The circuit substrate according to item 8, wherein the first wire and the third wire are each formed of a plurality of metal wires in parallel.

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