CN108182921A - A kind of array substrate, display panel and display device - Google Patents
A kind of array substrate, display panel and display device Download PDFInfo
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- CN108182921A CN108182921A CN201810005105.4A CN201810005105A CN108182921A CN 108182921 A CN108182921 A CN 108182921A CN 201810005105 A CN201810005105 A CN 201810005105A CN 108182921 A CN108182921 A CN 108182921A
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- shift register
- pole plate
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- register cell
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Liquid Crystal Display Device Control (AREA)
- Shift Register Type Memory (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a kind of array substrate, display panel and display devices, the array substrate includes gate driving circuit, the gate driving circuit includes multiple cascade shift register cells, it is connect per level-one shift register cell with a horizontal scanning line, wherein, the multiple cascade shift register cell is electrically connected by cascading cabling；Each shift register cell includes bootstrap capacitor；The bootstrap capacitor includes the first pole plate, and the first pole plate overlaps setting with cascade cabling, and the fractional reuse overlapped with the first pole plate of the cascade cabling is the second pole plate of bootstrap capacitor.Without the second pole plate of bootstrap capacitor is still further separately provided, bootstrap capacitor chip area shared in array substrate can be reduced, so as to reduce the chip area of entire gate driving circuit, be conducive to the narrow frame design of display device.
Description
Technical field
The present invention relates to display technology fields, more specifically, are related to a kind of array substrate, display panel and display and fill
It puts.
Background technology
Display device such as liquid crystal display device (liquid crystal display, LCD) or Organic Light Emitting Diode
(Organic Light-Emitting Diode, OLED) display device has many advantages, such as Low emissivity, small and low power consuming, quilt
It is widely used in laptop, personal digital assistant (Personal Digital Assistant, PDA), flat-surface television
In the information products such as mobile phone.
The driving circuit of display device includes：For showing the pel array of image；Data-signal is carried by data line
Supply the data drive circuit of pel array；The grid impulse (or scanning pulse) synchronous with data-signal is pressed by scan line
It is sequentially presented to gate driving circuit of pel array etc..
At present, GOA technologies are a kind of common gate driving circuit technologies of display device, by TFT (Thin Film
Transistor, thin film field effect transistor) gate switch circuit is integrated in the array substrate of display panel to be formed to aobvious
Show the turntable driving of panel, so as to save the binding region of gate driving circuit and peripheral wiring space.GOA circuits
Function mainly includes：Using the high level signal of lastrow scan line output to the capacitor charging in shift register cell, with
This horizontal scanning line is made to export high level signal, the high level signal of next horizontal scanning line output is recycled to realize and is resetted.When due to
When the increase of the resolution ratio of display panel leads to the number increase of scan line, the size of gate driving circuit increases, and causes to show
The increase of the frame region of panel is unfavorable for the narrow frame design of display device.
Invention content
An embodiment of the present invention provides a kind of array substrate for the size that can reduce gate driving circuit, including the battle array
The display panel and display device of row substrate are conducive to the narrow frame design of display device.
First, an embodiment of the present invention provides a kind of array substrates, including gate driving circuit, the gate driving circuit
Including the first clock cable and multiple cascade shift register cells, per level-one shift register cell and a horizontal scanning line
Connection, wherein, multiple cascade shift register cells are electrically connected by cascading cabling；Each shift register cell includes
Logic module, driving transistor and bootstrap capacitor；Wherein, the drive signal output of the grid connection logic module of driving transistor
End, the first pole of driving transistor are connected to the first clock cable, the second pole connection shift register list of driving transistor
This grade of signal output end of member；Bootstrap capacitor includes the first pole plate, and the first pole plate is overlapped with cascade cabling, and the first of bootstrap capacitor
Pole plate and the grid of driving transistor connect, and the fractional reuse overlapped with first pole plate for cascading cabling is bootstrapping electricity
The second pole plate held.
In an embodiment of the invention, above-mentioned gate driving circuit further includes the first drive signal line and second and drives
Dynamic signal wire, logic module include charging transistor and discharge transistor, wherein, the first pole of charging transistor is connected to first
Drive signal line, the second pole of charging transistor are connected to the second pole of discharge transistor and the grid of driving transistor；Electric discharge
First pole of transistor is connected to the second drive signal line；From second level shift register cell to penultimate stage shift LD
Device unit, the grid of charging transistor are connected to the sheet of upper level shift register cell adjacent thereto by cascading cabling
Grade signal output end；The grid of its discharge transistor is connected to next stage shift register list adjacent thereto by cascading cabling
This grade of signal output end of member.
In an embodiment of the invention, the second of the first pole plate of above-mentioned bootstrap capacitor and charging transistor is extremely same
Layer is formed, and the grid same layer for cascading cabling and charging transistor is formed.
In an embodiment of the invention, this grade of signal output end of above-mentioned cascade cabling and shift register cell
Connection；Its bootstrap capacitor further includes third pole plate, and third pole plate is located at the side of the separate cascade cabling of the first pole plate, and
This of tri-electrode and shift register cell grade signal output end connects.
In an embodiment of the invention, above-mentioned third pole plate passes through the first via and the shift register cell
The connection of this grade of signal output end, and the third pole plate passes through the cascade cabling of the second via and the shift register cell
Connection.
In an embodiment of the invention, it is conductive to include be connected with each other first for the first pole plate of above-mentioned bootstrap capacitor
Layer and the second conductive layer, and the second conductive layer and third pole plate are transparency conducting layer；And array substrate further includes the first metal layer
With second metal layer, the first metal layer includes the grid of cascade cabling and charging transistor, and it is conductive that second metal layer includes first
Layer；The overlapping area of second conductive layer and third pole plate is more than the overlapping area of the first conductive layer and third pole plate.
In an embodiment of the invention, at least the second conductive layer of part is perpendicular to the extension side of cascade cabling
Upward width is more than width of first conductive layer on the extending direction perpendicular to cascade cabling, at least part third pole plate
Width on the extending direction perpendicular to cascade cabling is more than the first conductive layer in the extending direction perpendicular to cascade cabling
On width, and the larger part part larger with the width of third pole plate of width of the second conductive layer is correspondingly arranged.
In an embodiment of the invention, array substrate further includes the first transparency conducting layer and the second electrically conducting transparent
Layer, wherein, the first transparency conducting layer includes one of pixel electrode and public electrode, and the second transparency conducting layer includes pixel electricity
The other of pole and public electrode, and the first transparency conducting layer is located at the one of the close second metal layer of the second transparency conducting layer
Side；First transparency conducting layer further includes the second conductive layer, and the second transparency conducting layer further includes third pole plate.
In an embodiment of the invention, above-mentioned the first metal layer further includes scan line, and above-mentioned second metal layer is also
Including data line.
In an embodiment of the invention, for first order shift register cell：The grid of its charging transistor
Initial signal is received, the grid of discharge transistor is connected to the sheet of second level shift register cell by the cascade cabling
Grade signal output end；For grade shift register cell last (namely afterbody shift register cell)：It charges
The grid of transistor is connected to this grade of signal output end of penultimate stage shift register cell by cascading cabling, electric discharge
The grid of transistor receives reset signal.
In an embodiment of the invention, gate driving circuit further includes second clock signal wire, and logic module is also
Including pull-down transistor, wherein, the grid of pull-down transistor is connected to second clock signal wire, and the first pole of pull-down transistor connects
The second drive signal line is connected to, the second pole of pull-down transistor is connected to this grade of signal output end of shift register cell.
In addition, the present invention also provides a kind of display panel, including above-mentioned array substrate.
In addition, the present invention also provides a kind of display device, including above-mentioned display panel.
Array substrate provided in an embodiment of the present invention, display panel and display device, including gate driving circuit, cascade
The fractional reuse overlapped with the first pole plate of bootstrap capacitor of cabling is the second pole plate of the bootstrap capacitor, without
The second pole plate of bootstrap capacitor is still further separately provided, bootstrap capacitor chip area shared in array substrate can be reduced,
So as to reduce the chip area of entire gate driving circuit, be conducive to the narrow frame design of display device.
Description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention, for those of ordinary skill in the art, without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of schematic diagram of array substrate provided in an embodiment of the present invention；
Fig. 2 is a kind of schematic diagram of gate driving circuit provided in an embodiment of the present invention；
Fig. 3 is a kind of schematic diagram of shift register provided in an embodiment of the present invention；
Fig. 4 is a kind of schematic diagram of gate driving circuit provided in an embodiment of the present invention；
Fig. 5 is the schematic diagram of another gate driving circuit provided in an embodiment of the present invention；
Fig. 6 is the sectional view of the A-A' along Fig. 5；
Fig. 7 is the sectional view of the part-structure of another gate driving circuit provided in an embodiment of the present invention；
Fig. 8 is the schematic diagram of another gate driving circuit provided in an embodiment of the present invention；
Fig. 9 is the sectional view of the B-B' along Fig. 8.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without making creative work
Embodiment shall fall within the protection scope of the present invention.
Carry out the various exemplary embodiments of detailed description of the present invention now with reference to attached drawing.It should be noted that：Unless in addition have
Body illustrates that the unlimited system of component and the positioned opposite of step, numerical expression and the numerical value otherwise illustrated in these embodiments is originally
The range of invention.
It is illustrative to the description only actually of at least one exemplary embodiment below, is never used as to the present invention
And its application or any restrictions that use.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of, the technology, method and apparatus should be considered as part of specification.
In shown here and discussion all examples, any occurrence should be construed as merely illustrative, without
It is as limitation.Therefore, other examples of exemplary embodiment can have different values.
It should be noted that：Similar label and letter represents similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, then in subsequent attached drawing does not need to that it is further discussed.
First, the present invention provides a kind of array substrate, and as shown in FIG. 1, FIG. 1 is a kind of arrays provided in an embodiment of the present invention
The schematic diagram of substrate.Specifically, array substrate 100 includes viewing area 101 and the non-display area 102 around viewing area setting, with
And the pel array positioned at viewing area 101, the data line DL of the pel array including a plurality of configured in parallel parallel match with a plurality of
The scan line GL put, multiple data lines DL and the multi-strip scanning line GL multiple sub-pixel P of definition arranged in a crossed manner, each sub-pixel P packets
The display structures such as driving switch and pixel electrode are included, wherein display driving switch for example can be with grid, source electrode, drain electrode three
Source electrode (or drain electrode) connection of the thin film transistor (TFT) of a terminal, pixel electrode and thin film transistor (TFT).The pel array is for example
It can include multiple lines and multiple rows sub-pixel P, the drain electrode (or source electrode) of the thin film transistor (TFT) in each column sub-pixel P can for example connect
To same data line DL, data-signal is provided for the sub-pixel P of respective column by data line DL, often in row sub-pixel P
The grid of thin film transistor (TFT) can for example be connected to same scan line GL, by the sub-pixel P that this scan line GL is corresponding row
Scanning signal is provided, for BRIEF DESCRIPTION OF THE DRAWINGS, present disclosure is protruded, illustrates the knot of each sub-pixel with schematic diagram in Fig. 1
Structure.
Array substrate 100 further includes data drive circuit 02 and gate driving circuit 01, positioned at non-display area 102, grid
Driving circuit 01 includes at least two-stage shift register cell, is connected per level-one shift register cell with a horizontal scanning line,
So as to input scanning signal to scan line successively, to realize the progressive scan of scan line.Data drive circuit 02 for example may be used
To include multiple data pins, be correspondingly connected with multiple data lines DL, can successively to data line DL input data signals, and
The display of predetermined image is realized under the control of scanning signal.
In schematic diagram shown in Fig. 1, gate driving circuit 01 is located at the non-display area 102 of 101 side of viewing area, all sweeps
Retouch line GL shift register cell connections all corresponding in the gate driving circuit 01.Or：Gate driving circuit 01
Including two parts, the shift register cell in the both sides of viewing area 101, a portion gate driving circuit 01 respectively
It is connect with odd number horizontal scanning line, the shift register cell in another part gate driving circuit 01 connects with even number horizontal scanning line
It connects；Alternatively, the both ends per horizontal scanning line are connected to the corresponding shift register cell in both sides simultaneously respectively, driving force is improved,
And reduce signal delay.
It is please referred to shown in Fig. 2 about gate driving circuit, Fig. 2 is a kind of gate driving circuit provided in an embodiment of the present invention
Schematic diagram, in the present embodiment, gate driving circuit 01 includes multiple cascade shift register cells 10 and a plurality of driving
Signal bus (DR1, DR2, CK1, CK2 in such as figure), the quantity of the quantity of shift register cell 10 and the scan line of viewing area
Equal, multiple cascade shift register cell 10 is electrically connected by cascading cabling 11, per level-one shift register cell
10 connect with a horizontal scanning line of viewing area, so as to be moved by multi-stage shift register unit to the scanning signal of input
Position, to realize the progressive scan to each horizontal scanning line.Signal bus can for example include：First drive signal line DR1 is at different levels
Shift register cell 10 provides the first drive signal, can be that high level signal also may be used according to the needs of scanning line driving
Think low level signal；Second drive signal line DR2 provides the second drive signal, equally for shift register cells 10 at different levels
, can may be low level signal for high level signal according to the needs of scanning line driving；First clock cable
CK1 provides the first clock signal and second clock signal wire CK2 for shift register cells 10 at different levels, is posted for displacements at different levels
Storage unit 10 provides second clock signal, etc..
In above-mentioned gate driving circuit 01, in addition to first order shift register cell, remaining is per level-one shift register
First signal input part Input of unit is believed by cascading this grade of the upper level shift register cell adjacent thereto of cabling 11
Number output terminal Gout (or the scan line being connect with upper level shift register cell) is connected, defeated using lastrow scan line
The high level signal gone out is to the capacitor charging in shift register cell, so that this horizontal scanning line exports high level signal.First
First signal input part Input of grade shift register cell receives initial signal STP, in first order shift register cell
Capacitor charging so that this horizontal scanning line export high level signal.
In addition to afterbody (grade last) shift register cell, remaining is per the second of level-one shift register cell
Signal input part Reset is by cascading this grade of signal output end of the next stage shift register cell adjacent thereto of cabling 11
Gout (or the scan line being connect with next stage shift register cell) is connected, and utilizes the height electricity of next horizontal scanning line output
Ordinary mail number, which is realized, to be resetted.The second signal input terminal Reset of afterbody shift register cell can input reset signal.
Above-mentioned gate driving circuit can step by step be scanned since first order shift register cell, it is, of course, also possible to root
According to the different scannings for realizing different directions of initial signal STP input positions.
Specifically, when the first order shift register cell in the shift register cells at different levels of above-mentioned gate driving circuit
The first signal input part Input receive initial signal STP, the second signal input terminal of afterbody shift register cell
When Reset inputs reset signal, this grade of signal output end Gout of shift register cells at different levels will sequentially be swept from top to bottom
It retouches signal and is output to scan line corresponding thereto, when last in the shift register cells at different levels of above-mentioned gate driving circuit
The second signal input terminal Reset of level-one shift register list receives initial signal STV, and the first of first order shift register list
When signal input part Input inputs reset signal, this grade of signal output end Output at different levels from bottom to up sequentially will scanning
Signal is output to scan line corresponding thereto.
It is please referred to shown in Fig. 3 about shift register cell, Fig. 3 is a kind of shift register provided in an embodiment of the present invention
The schematic diagram of unit, in the present embodiment, each shift register cell include logic module 12, driving transistor T1 and bootstrapping
Capacitance Cs.Wherein, the driving signal output end Output, driving transistor T1 of the grid connection logic module of driving transistor T1
The first pole connection gate driving circuit the first clock cable CK1, the second pole of driving transistor T1 is connected to displacement and posts
This grade of signal output end Gout of storage unit, is connected to the scan line GL being connect with this grade of shift register cell in other words.
The first end of bootstrap capacitor Cs is connected to the grid of driving transistor T1, and the second end of bootstrap capacitor Cs is connected to driving transistor
The second pole of T1 is connected to this grade of signal output end Gout of shift register cell, is connected to and this grade in other words in other words
The scan line GL of shift register cell connection.The drive signal of logic module will be received in the grid of driving transistor T1
When output terminal Output is transmitted to the drive signal of grid, the second end of bootstrap capacitor Cs is in vacant state, as driving is brilliant
The grid potential of body pipe T1 rises, and the current potential of the second end of bootstrap capacitor Cs rises, the voltage of the first end of bootstrap capacitor Cs with
Can be coupled rising, the voltage of the usual first end can be coupled grid that is very high, and then having raised driving transistor T1
Current potential, the equivalent resistance for making driving transistor T1 is very small, reduces the loss of driving transistor, so as to keep scan line
Voltage be as closely as possible to the first clock cable CK1 to signal voltage, improve the driving force of gate driving circuit.
About the structure of bootstrap capacitor Cs, please refer to Fig.4 shown in, Fig. 4 is another grid provided in an embodiment of the present invention
The schematic diagram of driving circuit, certainly, in order to clearly show the connection mode of bootstrap capacitor Cs in the embodiment of the present invention, Fig. 4
It is the part-structure for showing gate driving circuit, the composition of gate driving circuit provided in an embodiment of the present invention is not limited to figure
Shown in part.
In the present embodiment, it please also refer to shown in Fig. 2,3,4, gate driving circuit 01 includes drive signal bus (such as
CK1, CK2, DR1, DR2 etc.) with multiple cascade shift register cells 10, drive signal bus include the first clock cable
CK1, second clock signal wire CK2, the first drive signal line DR1 and the second drive signal line DR2, shift register cell 10 wrap
Driving transistor T1, bootstrap capacitor Cs and logic module 12 are included, logic module 12 includes at least charging transistor T2 and electric discharge is brilliant
Body pipe T3.
Wherein, the first pole T11 of driving transistor T1 is connected to the first clock cable CK1, for receiving the first clock
Signal；The second pole T12 of driving transistor T1 is connected to this grade of signal output end Gout of shift register cell, connects in other words
It is connected to the scan line GL being connect with this grade of shift register cell.
For second level shift register cell to penultimate stage shift register cell：
The first pole T21 of charging transistor T2 is connected to the first drive signal line DR1, for receiving the first drive signal,
The second pole T22 of charging transistor T2 is connected to the grid T10 of driving transistor T1, and the grid T20 of charging transistor T2 passes through
Cascade cabling 11 is connected to this grade of signal output end Gout of upper level shift register cell adjacent thereto.
The first pole T31 of discharge transistor T3 is connected to the second drive signal line DR2, for receiving the second drive signal,
The second pole T32 of discharge transistor T3 is connected to the grid of the second pole T22 and driving transistor T1 of charging transistor T2 simultaneously
The grid T30 of T10, discharge transistor T3 are connected to next stage shift register cell adjacent thereto by cascading cabling 11
This grade of signal output end Gout.
In addition, for first order shift register cell：The first pole T21 of charging transistor T2 is connected to the first driving letter
Number line DR1, for receiving the first drive signal, the second pole T22 of charging transistor T2 is connected to the grid of driving transistor T1
The grid T20 of T10, charging transistor T2 receive initial signal；The first pole T31 of discharge transistor T3 is connected to the second driving letter
Number line DR2, for receiving the second drive signal, the second pole T32 of discharge transistor T3 is connected to charging transistor T2's simultaneously
The grid T30 of the grid T10 of second pole T22 and driving transistor T1, discharge transistor T3 are connected to the by cascading cabling 11
This grade of signal output end of two level shift register cell；
For grade shift register cell last：The first pole T21 of charging transistor T2 is connected to the first driving letter
Number line DR1, for receiving the first drive signal, the second pole T22 of charging transistor T2 is connected to the grid of driving transistor T1
The grid T20 of T10, charging transistor T2 are connected to this grade of letter of penultimate stage shift register cell by cascading cabling 11
Number output terminal；The first pole T31 of discharge transistor T3 is connected to the second drive signal line DR2, for receiving the second drive signal,
The second pole T32 of discharge transistor T3 is connected to the grid of the second pole T22 and driving transistor T1 of charging transistor T2 simultaneously
The grid T30 of T10, discharge transistor T3 receive reset signal.
Wherein, driving transistor, charging transistor, discharge transistor are, for example, thin film transistor (TFT), including grid, semiconductor
The material of active layer, source-drain electrode, wherein semiconductor active layer is such as can be non-crystalline silicon, low temperature polycrystalline silicon.
Specifically, existing illustrate by taking N grades of shift register cells as an example：Multiple cascade shift register cell packets
(N-1) grade shift register cell, N grades of shift register cells and (N+1) grade shift register cell are included, wherein, N
For positive integer, and N >=2.
For N grades of shift register cells：The grid T20 of its charging transistor T2 is connected to by cascading cabling 11
(N-1) the second pole T12 of the driving transistor T1 of grade shift register cell is connected to is posted with the displacement of (N-1) grade in other words
The scan line GL of storage unit connection；The grid T30 of its discharge transistor T3 is connected to the shifting of (N+1) grade by cascading cabling 11
The second pole T12 of the driving transistor T1 of bit register unit is connected to connects with (N-1) grade shift register cell in other words
The scan line GL connect；
Bootstrap capacitor Cs includes the first pole plate Cs1, is connect with the grid T10 of driving transistor T1, the first pole plate Cs1 and grade
Join the overlapping setting of cabling 11, at least cascade cabling 11 and the first pole plate Cs1 in part is overlapped in other words, and cascades cabling 11
This grade of signal output end Gout of shift register cell is connected to, wherein, cascade the Chong Die with the first pole plate Cs1 of cabling 11 sets
The fractional reuse put is the second pole plate Cs2 of bootstrap capacitor Cs.Without the second pole of bootstrap capacitor is still further separately provided
Plate can reduce bootstrap capacitor chip area shared in array substrate, so as to reduce entire gate driving circuit
Chip area is conducive to the narrow frame design of display device.
Further, in the present embodiment, logic module 12 further includes pull-down transistor T4, specifically, pull-down transistor
The grid T40 connection second clock signal wire CK2 of T4, for receiving second clock signal, the first pole T41 of pull-down transistor T4
The second drive signal line DR2 is connected to, the second pole T42 of pull-down transistor T4 is connected to the second pole T22 of driving transistor T1,
It is connected to this grade of signal output end of shift register cell in other words, for keeping the low potential of this horizontal scanning line.
In the present embodiment, such as can be:The second pole of the first pole plate Cs1 and charging transistor T2 of bootstrap capacitor Cs
T22 same layers are formed, and the grid T20 same layers of cascade cabling 11 and charging transistor T2 are formed.
Further, in the present embodiment, such as can be：Array substrate includes the first metal layer and second metal layer,
The first metal layer can for example be set with second metal layer by insulating layer or passivation layer insulation gap.Wherein, the first metal layer
Including be located at viewing area scan line, show driving switch grid and positioned at non-display area drive signal bus (such as
CK1, CK2, DR1, DR2 etc.), cascade cabling, the grid of driving transistor, the grid of charging transistor, discharge transistor grid
Pole and the grid of pull-down transistor；Second metal layer includes the data line positioned at viewing area, the source-drain electrode for showing driving switch, with
And the first pole plate of bootstrap capacitor positioned at non-display area, the first pole of driving transistor, the second pole of driving transistor, charging
First pole of transistor, the second pole of charging transistor, the first pole of discharge transistor, the second pole of discharge transistor, drop-down
First pole of transistor and the second pole of pull-down transistor.At this point, the of driving transistor, charging transistor, discharge transistor
One pole for example can by via respectively with the first clock cable CK1, the first drive signal line DR1 and the second drive signal line
DR2 connections；Second pole of charging transistor and discharge transistor can for example be connected by via and the grid of driving transistor；
The grid of pull-down transistor can for example be connect by overline structure with second clock signal wire CK2, and the first of pull-down transistor
Pole can for example be connect by via with the second drive signal line DR2.
Certainly, in other embodiments, or：Second metal layer includes the scan line positioned at viewing area, display
The grid of driving switch, the first metal layer include the data line positioned at viewing area, the source-drain electrode for showing driving switch, and the present invention is real
It applies example and particular determination is done not to this.
Fig. 5 is the schematic diagram of another gate driving circuit provided in an embodiment of the present invention, and Fig. 6 is the A-A' along Fig. 5
Sectional view, Fig. 5 is similar with the structure of Fig. 3 gate driving circuits provided with the gate driving circuit that Fig. 6 is provided, bootstrap capacitor
Cs includes the first pole plate Cs1, is connect with the grid of driving transistor, at least 11 and first pole plate Cs1 of part cascade cabling weights
Folded setting, and cascade this grade of signal output end that cabling 11 is connected to shift register cell, wherein, cascade cabling 11 with the
The fractional reuse that one pole plate Cs1 is overlapped is the second pole plate Cs2 of bootstrap capacitor Cs.The difference lies in：Bootstrap capacitor Cs
It further includes third pole plate Cs3, third pole plate Cs3 and the first pole plate Cs1 overlaps setting, the first pole plate Cs1, the second pole plate Cs2,
Tri-electrode Cs3 is set by insulating layer or passivation layer insulation gap, and third pole plate Cs3 is located at the separate grade of the first pole plate Cs1
Joining the side of cabling 11, third pole plate Cs3 is connected to this grade of signal output end of shift register cell by the first via H1,
It is connected to the scan line GL being connect with this grade of signal output end in other words, in this way, being set as bootstrap capacitor Cs by the first pole plate
The capacitance of sandwich structure that Cs1, the second pole plate Cs2, third pole plate Cs3 are formed with insulating layer therebetween, can not change
In the case of the area of bootstrap capacitor Cs, the coupling ability of bootstrap capacitor Cs and bootstrapping ability are improved, it is brilliant to be further reduced driving
The loss of body pipe improves the driving force of gate driving circuit.
Further, in the present embodiment, such as can be：Array substrate further includes public electrode, public electrode and picture
Electric field, third pole plate Cs3 and the pixel electrode of array substrate viewing area or public electrode same layer can be formed between plain electrode
It is formed, will not so increase the fabrication steps of array substrate when increasing third pole plate Cs3, reduce cost.
Fig. 7 is the sectional view of the part-structure of another gate driving circuit provided in an embodiment of the present invention, and Fig. 7 is provided
Gate driving circuit it is similar with the structure of Fig. 5 gate driving circuits provided, bootstrap capacitor Cs includes the first pole plate Cs1, the
Two pole plate Cs2 and third pole plate Cs3, third pole plate Cs3 are located at the side far from the second pole plate Cs2 of the first pole plate Cs1, third
Pole plate Cs3 is connected to this grade of signal output end of shift register cell by via, is connected in other words defeated with this grade of signal
The scan line GL of outlet connection, forms the capacitance of sandwich structure, can in the case of the area for not changing bootstrap capacitor Cs,
The coupling ability of bootstrap capacitor Cs and bootstrapping ability are improved, the loss of driving transistor is further reduced, improves gate driving electricity
The driving force on road.The difference lies in：Third pole plate Cs3 is connected to this grade of shift register cell by the first via H1
Signal output end is connected to the scan line GL, the first via H1 being connect with this grade of signal output end and runs through third pole plate in other words
Cs3 and scan line GL insulating layer or passivation layer between layers；Third pole plate Cs3 is connected to displacement by the second via H2
The cascade cabling 11 of register cell is connected with each other in other words with the second pole plate Cs2, and the second via H2 runs through the first pole plate Cs1
With cascade cabling 11 institute's at least dielectric layers between layers or passivation layer, due to cascade cabling 11 and shift register list
Member this grade of signal output end be connected with each other, so cascade cabling 11 in fact with this grade of signal output end of shift register cell
With identical current potential.Using two or more vias by third pole plate and this grade of signal output end of shift register cell
Connection, can reduce equivalent resistance, while can reduce the risk of the bad caused open circuit of via.
Fig. 8 is the schematic diagram of another gate driving circuit provided in an embodiment of the present invention, and Fig. 9 is the B-B' along Fig. 8
Sectional view, Fig. 8 is similar with the structure of Fig. 5 gate driving circuits provided with the gate driving circuit that Fig. 9 is provided, the first pole plate
Cs1, the second pole plate Cs2 and third pole plate Cs3, third pole plate Cs3 are located at one far from the second pole plate Cs2 of the first pole plate Cs1
Side, third pole plate Cs3 are connected to this grade of signal output end of shift register cell by via, are connected to and this grade in other words
The scan line GL of signal output end connection forms the capacitance of sandwich structure.The difference lies in：The first pole of bootstrap capacitor Cs
Plate Cs1 includes the first conductive layer Cs11 and the second conductive layer Cs12 that are connected with each other, wherein, the first conductive layer Cs11 is shading gold
Belong to layer, the second conductive layer Cs12 and the third pole plate Cs2 for transparency conducting layer, and the second conductive layer Cs12 and third pole plate
The overlapping area of Cs3 is more than the overlapping area of the first conductive layer Cs11 and third pole plate Cs3.
Specifically, in the present embodiment, array substrate includes the first metal layer M1 and second metal layer M2, the first metal layer
M1 and second metal layer M2 can for example be set by passivation layer insulation gap.Wherein, the first metal layer M1 includes being located at display
The scan line in area, the grid for showing driving switch and positioned at non-display area drive signal bus (such as CK1, CK2, DR1,
DR2 etc.), cascade cabling, the grid of driving transistor, the grid of charging transistor, discharge transistor grid and lower crystal pulling
The grid of pipe；Second metal layer M2 includes the data line positioned at viewing area, the source-drain electrode for showing driving switch and positioned at non-aobvious
Show the first pole plate of the bootstrap capacitor in area, the first pole of driving transistor, the second pole of driving transistor, charging transistor
One pole, the second pole of charging transistor, the first pole of discharge transistor, the second pole of discharge transistor, pull-down transistor
One pole and the second pole of pull-down transistor.Wherein, the first conductive layer Cs11 of the first pole plate Cs1 and second metal layer M2 same layer shapes
Into.
Certainly, in other embodiments, or：Second metal layer M2 includes the scan line positioned at viewing area, shows
Show the grid of driving switch, the first metal layer M1 includes the data line positioned at viewing area, the source-drain electrode for showing driving switch, this hair
Bright embodiment does particular determination not to this.
Further, in the present embodiment, array substrate further includes the first transparency conducting layer I1 and the second transparency conducting layer
I2, the first transparency conducting layer I1 include one of pixel electrode and public electrode and the second conductive layer of the first pole plate Cs1
Cs12, the second conductive layer Cs12 and the first conductive layer Cs11 are connected with each other, or the second conductive layer Cs12 and first is conductive
Layer Cs11 is in direct contact, that is to say, that no longer setting has insulation characterisitic between the second conductive layer Cs12 and the first conductive layer Cs11
Insulating layer or passivation layer；Second transparency conducting layer I2 includes the other of pixel electrode and public electrode and third
The overlapping area of pole plate Cs3, the second conductive layer Cs12 and third pole plate Cs3 are more than the first conductive layer Cs11 and third pole plate Cs3
Overlapping area.
Such as can be：The width on the extending direction perpendicular to cascade cabling 11 of second conductive layer Cs12 is more than the
One conductive layer Cs11 perpendicular to cascade cabling 11 extending direction on width, third pole plate Cs3 perpendicular to cascade
Width on the extending direction of cabling 11 is more than the first conductive layer Cs11 on the extending direction perpendicular to cascade cabling 11
Width；Certainly, it is contemplated that the domain of gate driving circuit interior cabling and transistor arrangement problem may be set to be, at least
Width of part the second conductive layer Cs12 on the extending direction perpendicular to cascade cabling 11 exists more than the first conductive layer Cs11
Width on the extending direction of cascade cabling 11, at least part third pole plate Cs3 is perpendicular to cascade cabling 11
Width on extending direction perpendicular to cascade cabling 11 of the width more than the first conductive layer Cs11 on extending direction, and the
The larger part of the width of the two conductive layer Cs12 part larger with the width of third pole plate Cs3 is correspondingly arranged, with
Increase the overlapping area of the second conductive layer Cs12 and third pole plate Cs3.
Wherein, the first transparency conducting layer I1 is located at the side of the close second metal layer M2 of the second transparency conducting layer I2.
In one embodiment of the present of invention, the first transparency conducting layer I1 and the second transparency conducting layer for example can be by ITO (tin indium oxides)
Material or other transparent conductive materials are formed.
Due to the first conductive layer Cs11 and cascade cabling be all to be formed by shading metal layer, and array substrate correspond to grid
The position of pole driving circuit subsequently carries out frame glue coating and cures with ultraviolet light afterwards, in order to ensure the solidification effect of frame glue, needs herein
There is certain light transmittance, thus the area of the width of the first conductive layer the first conductive layer in other words be unfit to do it is excessive, it is multiple
It is also unfit to do with the cascade cabling for the second pole plate wide.The embodiment of the present invention is by increasing the second conductive layer Cs12 and third
The overlapping area of pole plate Cs3 improves the coupling ability of bootstrap capacitor Cs, since the second conductive layer Cs12 and third pole plate Cs3 are
Transparency conducting layer, therefore even if the chip area of the second conductive layer Cs12 and third pole plate Cs3 are done greatly, also to non-display area
Light transmittance does not influence, when after the non-display area of array substrate coats frame glue, can both increasing the coupling energy of bootstrap capacitor Cs
Power, and can ensure its frame glue solidification effect.
Moreover, the second conductive layer is formed with one of pixel circuit and public electrode same layer, third pole plate and pixel electricity
The other of road and public electrode same layer are formed, and while the coupling ability for increasing bootstrap capacitor, will not increase array base
The fabrication steps of plate, reduce cost.
To sum up, in one embodiment of the invention, the fractional reuse overlapped with the first pole plate that cabling will be cascaded
For the second pole plate of bootstrap capacitor, without the second pole plate of bootstrap capacitor is still further separately provided, bootstrapping electricity can be reduced
Hold shared chip area in array substrate, so as to reduce the chip area of entire gate driving circuit, be conducive to show
The narrow frame design of showing device.In another embodiment of the present invention, by setting transparent third pole plate or passing through increasing
The overlapping area of third pole plate and the second conductive layer is added to improve the coupling ability of bootstrap capacitor Cs.
In addition, the embodiment of the present invention also provides a kind of display panel with above-mentioned array substrate, which has
The identical structure and advantageous effect of array substrate provided with above-described embodiment, due in previous embodiment by array substrate
Structure and advantageous effect be described in detail, details are not described herein again.
In addition, the embodiment of the present invention also provides a kind of display device, including display panel as described above.With with it is above-mentioned
The identical structure and advantageous effect of array substrate that embodiment provides, due in previous embodiment by the structure of array substrate
It is described in detail with advantageous effect, details are not described herein again.
In embodiments of the present invention, display device can specifically include liquid crystal display device, such as the display device can be with
For any product or portion with display function such as liquid crystal display, LCD TV, Digital Frame, mobile phone or tablet computer
Part.
The preferred embodiment and the explanation to institute's application technology principle that above description is only the application.People in the art
Member should be appreciated that invention scope involved in the application, however it is not limited to the technology that the specific combination of above-mentioned technical characteristic forms
Scheme, while should also cover in the case where not departing from the inventive concept, it is carried out by above-mentioned technical characteristic or its equivalent feature
The other technical solutions for arbitrarily combining and being formed.Such as features described above has similar work(with (but not limited to) disclosed herein
The technical solution that the technical characteristic of energy is replaced mutually and formed.
Claims (13)
1. a kind of array substrate, which is characterized in that including gate driving circuit, the gate driving circuit is believed including the first clock
Number line and multiple cascade shift register cells, connect per level-one shift register cell with a horizontal scanning line, wherein, it is described
Multiple cascade shift register cells are electrically connected by cascading cabling；
Each shift register cell includes logic module, driving transistor and bootstrap capacitor；
The driving signal output end of the grid connection logic module of the driving transistor, the first of the driving transistor
Pole is connected to first clock cable, and the second pole of the driving transistor connects this grade of the shift register cell
Signal output end；
The bootstrap capacitor includes the first pole plate, and first pole plate is overlapped with the cabling that cascades, and the of the bootstrap capacitor
One pole plate is connect with the grid of the driving transistor, and the part overlapped with first pole plate of the cascade cabling is answered
With the second pole plate for the bootstrap capacitor.
2. array substrate according to claim 1, which is characterized in that the gate driving circuit further includes the first driving letter
Number line and the second drive signal line, the logic module include charging transistor and discharge transistor,
First pole of the charging transistor connects first drive signal line, the second pole connection institute of the charging transistor
State the second pole of discharge transistor and the grid of the driving transistor；The first pole connection described second of the discharge transistor
Drive signal line；
From second level shift register cell to penultimate stage shift register cell, the grid of the charging transistor passes through
The cascade cabling is connected to this grade of signal output end of upper level shift register cell adjacent thereto；The electric discharge crystal
The grid of pipe is connected to this grade of signal output end of next stage shift register cell adjacent thereto by the cascade cabling.
3. array substrate according to claim 2, which is characterized in that the first pole plate of the bootstrap capacitor and the charging
Second pole same layer of transistor is formed, and the grid same layer of the cascade cabling and the charging transistor is formed.
4. array substrate according to claim 1, which is characterized in that the cascade cabling and the shift register cell
This grade of signal output end connection,
The bootstrap capacitor further includes third pole plate, and the third pole plate is located at the separate cascade cabling of first pole plate
Side, the third pole plate connect with this grade of signal output end of the shift register cell.
5. array substrate according to claim 4, which is characterized in that the third pole plate passes through the first via and the shifting
This grade of signal output end connection of bit register unit, and the third pole plate passes through the second via and the shift register list
The cascade cabling connection of member.
6. array substrate according to claim 4, which is characterized in that the first pole plate of the bootstrap capacitor includes mutually interconnecting
The first conductive layer and the second conductive layer connect, second conductive layer are transparency conducting layer with the third pole plate；
The array substrate further includes the first metal layer and second metal layer, the first metal layer include cascade cabling with it is described
The grid of charging transistor, the second metal layer include the first conductive layer；
The overlapping area of second conductive layer and the third pole plate is more than first conductive layer and the third pole plate
Overlapping area.
7. array substrate according to claim 6, which is characterized in that at least part second conductive layer perpendicular to
It cascades the width on the extending direction of cabling and is more than width of first conductive layer on the extending direction perpendicular to cascade cabling
The width of degree, at least the part third pole plate on the extending direction perpendicular to cascade cabling is more than first conductive layer
The width on the extending direction perpendicular to cascade cabling, and the larger part of width of second conductive layer and described the
The part that the width of tri-electrode is larger is correspondingly arranged.
8. array substrate according to claim 6, which is characterized in that the array substrate further includes the first transparency conducting layer
With the second transparency conducting layer, first transparency conducting layer includes one of pixel electrode and public electrode, and described second thoroughly
Bright conductive layer includes the other of pixel electrode and public electrode, and first transparency conducting layer is transparent positioned at described second
The side of the close second metal layer of conductive layer；
First transparency conducting layer further includes second conductive layer, and second transparency conducting layer further includes the third pole
Plate.
9. array substrate according to claim 6, which is characterized in that the first metal layer further includes scan line, described
Second metal layer further includes data line.
10. array substrate according to claim 2, which is characterized in that
For first order shift register cell：The grid of the charging transistor receives initial signal, the discharge transistor
Grid pass through the cascade cabling and be connected to this grade of signal output end of second level shift register cell；
For grade shift register cell last：The grid of the charging transistor is second from the bottom by cascading cabling connection
This grade of signal output end of grade shift register cell, the grid of the discharge transistor receive reset signal.
11. array substrate according to claim 2, which is characterized in that the gate driving circuit further includes second clock
Signal wire, the logic module further include pull-down transistor,
The grid of the pull-down transistor connects the second clock signal wire, described in the first pole connection of the pull-down transistor
Second drive signal line, the second pole of the pull-down transistor are connected to this grade of signal output of the shift register cell
End.
12. a kind of display panel, including such as claim 1-11 any one of them array substrate.
13. a kind of display device, including display panel as claimed in claim 12.
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| CN201810005105.4A CN108182921B (en) | 2018-01-03 | 2018-01-03 | Array substrate, display panel and display device |
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| CN201810005105.4A CN108182921B (en) | 2018-01-03 | 2018-01-03 | Array substrate, display panel and display device |
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