CN112435629A

CN112435629A - Display substrate and display device

Info

Publication number: CN112435629A
Application number: CN202011329916.3A
Authority: CN
Inventors: 王洪润; 徐攀; 李昌峰; 张慧; 张舜航; 侯凯; 刘立伟; 林允植
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2020-11-24
Filing date: 2020-11-24
Publication date: 2021-03-02
Anticipated expiration: 2040-11-24
Also published as: US20240046859A1; CN112435629B; WO2022110650A1

Abstract

The invention provides a display substrate and a display device, relates to the technical field of display, and aims to solve the problem that the prior art cannot realize an OLED display device with high resolution. The display substrate comprises a plurality of sub-pixels, a compensation driving sub-circuit, a plurality of pixel groups and a plurality of compensation driving sub-circuits, wherein the plurality of sub-pixels are divided into a plurality of sub-pixel groups, each sub-pixel group comprises at least two sub-pixels, the at least two sub-pixels multiplex the same pixel driving circuit, at least two light-emitting control sub-circuits in the pixel driving circuit correspond to at least two light-emitting elements in the at least two sub-pixels, the at least two light-emitting control sub-circuits correspond to at least two light-emitting control signal lines, and each light-emitting control sub-circuit is respectively coupled with an output end of the compensation driving sub-circuit; each light-emitting control sub-circuit is used for controlling the connection between the output end of the compensation driving sub-circuit and the corresponding light-emitting element to be switched on or off under the control of the corresponding light-emitting control signal line. The display substrate provided by the invention is used for displaying.

Description

Display substrate and display device

Technical Field

The invention relates to the technical field of display, in particular to a display substrate and a display device.

Background

Organic Light-Emitting Diode (OLED) display devices are widely used in various fields due to their advantages of high brightness, low power consumption, fast response, high definition, good flexibility, high Light-Emitting efficiency, and the like.

The OLED display device includes a plurality of sub-pixels, each of which includes a pixel driving circuit for driving a light emitting element to emit light and the light emitting element. Since all the pixel driving circuits in the OLED display device are distributed on the substrate in an array, the number of the pixel driving circuits to be arranged is limited in a certain area due to factors such as line width, line distance and via hole size, so that it is difficult to realize the OLED display device with high resolution.

Disclosure of Invention

The invention aims to provide a display substrate and a display device, which are used for solving the problem that the prior art cannot realize an OLED display device with high resolution.

In order to achieve the above purpose, the invention provides the following technical scheme:

a first aspect of the present invention provides a display substrate, including a base and a plurality of sub-pixels disposed on the base, each sub-pixel including a light emitting element;

the plurality of sub-pixels are divided into a plurality of sub-pixel groups, each sub-pixel group comprises at least two sub-pixels, the at least two sub-pixels multiplex the same pixel driving circuit, and the pixel driving circuit comprises:

at least two light emission control signal lines, at least a portion of each of the light emission control signal lines extending in a first direction, the at least two light emission control signal lines being arranged in a second direction, the second direction intersecting the first direction;

the output end of the compensation driving sub-circuit is used for outputting a driving signal;

at least two light emission control sub-circuits corresponding to at least two light emitting elements included in the at least two sub-pixels, the at least two light emission control sub-circuits corresponding to the at least two light emission control signal lines, each of the light emission control sub-circuits being coupled to an output terminal of the compensation driving sub-circuit, a corresponding light emitting element, and a corresponding light emission control signal line, respectively; each light-emitting control sub-circuit is used for controlling the connection between the output end of the compensation driving sub-circuit and the corresponding light-emitting element to be switched on or off under the control of the corresponding light-emitting control signal line.

Optionally, the pixel driving circuit further includes:

a reference signal line at least a portion of which extends in a first direction;

a first reset signal line at least a portion of which extends in a first direction;

a gate line, at least a portion of the gate line extending in the first direction;

a power line, at least a portion of which extends in a second direction; and the number of the first and second groups,

a data line, at least a portion of the data line extending in the second direction;

the compensation driving sub-circuit includes:

a driving sub-circuit, a first terminal of the driving sub-circuit being coupled to the power line, and a second terminal of the driving sub-circuit being an output terminal of the compensation driving sub-circuit;

a memory sub-circuit, a first terminal of the memory sub-circuit coupled to the control terminal of the driving sub-circuit, and a second terminal of the memory sub-circuit coupled to the second terminal of the driving sub-circuit;

the first reset sub-circuit is respectively coupled with the first reset signal line, the reference signal line and the control end of the driving sub-circuit;

and the data writing sub-circuit is respectively coupled with the grid line, the data line and the control end of the driving sub-circuit.

Optionally, the at least two light-emitting control signal lines include a first light-emitting control signal line and a second light-emitting control signal line; the at least two light emission control sub-circuits include a first light emission control sub-circuit and a second light emission control sub-circuit; the at least two light emitting elements include a first light emitting element and a second light emitting element;

the first light-emitting control sub-circuit is respectively coupled with the second end of the driving sub-circuit, the first light-emitting control signal line and the first light-emitting element; the second light-emitting control sub-circuit is respectively coupled to the second end of the driving sub-circuit, the second light-emitting control signal line and the second light-emitting element.

Optionally, the first light emission control sub-circuit includes a first transistor, the second light emission control sub-circuit includes a second transistor, and the driving sub-circuit includes a driving transistor; the storage sub-circuit comprises a storage capacitor;

the grid electrode of the driving transistor is multiplexed as a first polar plate of the storage capacitor;

the second plate of the storage capacitor is positioned on one side of the first plate, which faces away from the substrate, and the second plate is coupled with the second pole of the driving transistor;

a first pole of the first transistor is coupled with a second pole of the driving transistor, and the second pole of the first transistor is coupled with a first light-emitting element;

a first pole of the second transistor is coupled to the second plate, and a second pole of the second transistor is coupled to the second light emitting element.

Optionally, the first transistor includes a first active pattern, and the first active pattern extends along the second direction; a first end of the first active pattern is coupled with a second pole of the driving transistor; a second end of the first active pattern is coupled with the first light emitting element;

an orthographic projection of a second end of the first active pattern on the substrate is positioned between the orthographic projection of the first light emission control signal line on the substrate and the orthographic projection of the second light emission control signal line on the substrate.

Optionally, the second plate includes a main body portion and an extension portion;

the orthographic projection of the main body part on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the driving transistor on the substrate;

the extension part extends along the second direction, and the orthographic projection of the extension part on the substrate is overlapped with the orthographic projection of the first light-emitting control signal line on the substrate and the orthographic projection of the second light-emitting control signal line on the substrate respectively.

Optionally, the second transistor includes a second active pattern, at least a portion of the second active pattern extends along the second direction, a first end of the second active pattern is coupled to the extension portion, and a second end of the second active pattern is coupled to the second light emitting element;

an orthographic projection of a first end of the second active pattern on the substrate is positioned between the orthographic projection of the first light emission control signal line on the substrate and the orthographic projection of the second light emission control signal line on the substrate.

Optionally, the pixel driving circuit further includes:

an initialization signal line at least a portion of which extends in the first direction;

a second reset signal line at least a portion of which extends in the first direction; the first reset signal line, the gate line, the first light emission control signal line, the second light emission control signal line, and the second reset signal line are sequentially arranged along the second direction;

and the second reset sub-circuit is respectively coupled with the second reset signal wire, the initialization signal wire and the extension part.

Optionally, the second reset sub-circuit includes a fifth transistor, the fifth transistor includes a fifth active pattern, and the fifth active pattern extends along the second direction;

the first end of the fifth active pattern is coupled to the extension portion, and an orthographic projection of the first end of the fifth active pattern on the substrate is located between an orthographic projection of the second light-emitting control signal line on the substrate and an orthographic projection of the second reset signal line on the substrate.

Optionally, the fifth active pattern and the initialization signal line form an integrated structure.

Optionally, an orthographic projection of the first reset signal line on the substrate is located between an orthographic projection of the reference signal line on the substrate and an orthographic projection of the gate line on the substrate;

the first reset sub-circuit includes a third transistor including a third active pattern extending in the second direction, a first end of the third active pattern being coupled to the reference signal line, and an orthogonal projection of a second end of the third active pattern on the substrate between an orthogonal projection of the first reset signal line on the substrate and an orthogonal projection of the gate line on the substrate.

Optionally, the gate line includes a gate main portion and two gate protruding portions, the gate main portion extends along the first direction, the two gate protruding portions are disposed at intervals along the first direction, and the two gate protruding portions are located between the gate main portion and the first reset signal line;

the data writing sub-circuit comprises a fourth transistor, the fourth transistor comprises a fourth active pattern, the fourth active pattern extends along the first direction, and orthographic projections of the fourth active pattern on the substrate are respectively overlapped with orthographic projections of the two gate protruding parts on the substrate;

a first terminal of the fourth active pattern is coupled to the data line, and a second terminal of the fourth active pattern is coupled to a second terminal of the third active pattern.

Optionally, the pixel driving circuit includes a conductive connection part, at least a portion of the conductive connection part extends along the second direction, and an orthogonal projection of the conductive connection part on the substrate overlaps an orthogonal projection of the gate line on the substrate;

a first end of the conductive connection portion is coupled to a second end of the third active pattern, and a second end of the conductive connection portion is coupled to a control end of the driving sub-circuit.

Based on the technical solution of the display substrate, a second aspect of the invention provides a display device, which includes the display substrate.

Optionally, the at least two light-emitting control signal lines in the display substrate include a first light-emitting control signal line and a second light-emitting control signal line; the at least two light emission control sub-circuits include a first light emission control sub-circuit and a second light emission control sub-circuit; the at least two light emitting elements include a first light emitting element and a second light emitting element;

a plurality of pixel driving circuits included in a plurality of sub-pixel groups in the display substrate are distributed in an array, the plurality of pixel driving circuits are divided into a plurality of rows of pixel driving circuits arranged along the second direction, first light-emitting control signal lines in each row of pixel driving circuits are sequentially coupled, and second light-emitting control signal lines in each row of pixel driving circuits are sequentially coupled;

the display device further includes: the gate driving circuit is positioned in the peripheral area of the display substrate and comprises a plurality of first shift register units and a plurality of second shift register units; the plurality of first shift register units correspond to the plurality of rows of pixel driving circuits one to one, and the plurality of second shift register units correspond to the plurality of rows of pixel driving circuits one to one;

the output end of the first shift register unit is coupled with a first light-emitting control signal line in a corresponding row of pixel driving circuits, and the output end of the second shift register unit is coupled with a second light-emitting control signal line in a corresponding row of pixel driving circuits.

In the technical scheme provided by the invention, at least two sub-pixels can multiplex one pixel driving circuit, and the pixel driving circuit can independently control the light-emitting elements of each sub-pixel in the at least two sub-pixels to independently emit light or simultaneously emit light, so that the technical scheme provided by the invention can realize high-resolution display under the condition of laying out a limited number of pixel driving circuits.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:

fig. 1 is a layout diagram of a pixel driving circuit according to an embodiment of the invention;

FIG. 2 is a schematic view of the active layer of FIG. 1;

FIG. 3 is a schematic diagram of the first gate metal layer of FIG. 1;

FIG. 4 is a schematic diagram of a second gate metal layer of FIG. 1;

FIG. 5 is a schematic view of the first source drain metal layer in FIG. 1;

fig. 6 is a first basic structure diagram of a pixel driving circuit according to an embodiment of the present invention;

fig. 7 is a first specific structural diagram of a pixel driving circuit according to an embodiment of the invention;

fig. 8 is a second basic structure diagram of a pixel driving circuit according to an embodiment of the invention;

fig. 9 is a second specific structural diagram of a pixel driving circuit according to an embodiment of the invention;

FIG. 10 is a timing diagram illustrating operation of the pixel driving circuit during a frame display period according to an embodiment of the present invention;

FIG. 11 is a timing diagram illustrating operation of a signal writing period according to an embodiment of the present invention;

fig. 12 is a schematic diagram of a gate driving circuit according to an embodiment of the invention.

Detailed Description

In order to further explain the display substrate and the display device provided by the embodiment of the invention, the following detailed description is made with reference to the drawings of the specification.

The embodiment of the invention provides a display substrate, which comprises a substrate and a plurality of sub-pixels arranged on the substrate, wherein each sub-pixel comprises a light-emitting element;

Illustratively, the at least two light emission control sub-circuits correspond to at least two light emitting elements included in the at least two sub-pixels one to one, and the at least two light emission control sub-circuits correspond to the at least two light emission control signal lines one to one.

Illustratively, the light-emitting element includes an anode and a cathode disposed opposite each other, and an organic light-emitting material layer between the anode and the cathode.

Illustratively, each sub-pixel group includes at least two sub-pixels adjacent to each other along the first direction.

Illustratively, each sub-pixel group includes at least two sub-pixels adjacent to each other along the second direction.

Illustratively, each sub-pixel group includes a plurality of sub-pixels including sub-pixels adjacent in the first direction and sub-pixels adjacent in the second direction.

Illustratively, each sub-pixel included in the sub-pixel group multiplexes the same pixel driving circuit.

Illustratively, the first direction includes a horizontal direction and the second direction includes a vertical direction.

Illustratively, the compensation driving sub-circuit is used for generating a current signal for driving the light emitting element to emit light.

For example, in the same time period, under the control of the at least two light emission control signal lines, only one of the at least two light emission control sub-circuits can control to turn on the connection between the output terminal of the compensation driving sub-circuit and the corresponding light emitting element, and the remaining light emission control sub-circuits all control to turn off the connection between the output terminal of the compensation driving sub-circuit and the corresponding light emitting element.

Illustratively, in the same period, under the control of the at least two light emission control signal lines, of the at least two light emission control sub-circuits, there are a plurality of light emission control sub-circuits capable of controlling to turn on the connection between the output terminal of the compensation driving sub-circuit and the corresponding light emitting element.

As can be seen from the specific structure of the display substrate, in the display substrate provided in the embodiment of the present invention, one pixel driving circuit can be multiplexed by at least two sub-pixels, and the pixel driving circuit can independently control the light emitting elements included in each of the at least two sub-pixels to independently emit light or to emit light simultaneously.

As shown in fig. 1 to 6 and 8, in some embodiments, the pixel driving circuit further includes:

a reference signal line 31, at least a part of the reference signal line 31 extending in a first direction;

a first reset signal line 32, at least a portion of the first reset signal line 32 extending in a first direction;

a gate line 33, at least a portion of the gate line 33 extending in the first direction;

a power supply line 38, at least a portion of the power supply line 38 extending in a second direction; and the number of the first and second groups,

a data line 39, at least a portion of the data line 39 extending in the second direction;

the compensation driving sub-circuit includes:

a driving sub-circuit 10, a first terminal of the driving sub-circuit 10 is coupled to the power line 38, and a second terminal of the driving sub-circuit 10 is used as an output terminal of the compensation driving sub-circuit;

a memory sub-circuit 11, a first terminal of the memory sub-circuit 11 being coupled to the control terminal of the driving sub-circuit 10, and a second terminal of the memory sub-circuit 11 being coupled to the second terminal of the driving sub-circuit 10;

a first reset sub-circuit 12 coupled to a first reset signal line 32, a reference signal line 31 and a control terminal of the driving sub-circuit 10, respectively;

the data writing sub-circuit 13 is coupled to the gate line 33, the data line 39 and the control terminal of the driving sub-circuit 10.

Illustratively, the reference signal line 31 is used for providing a reference signal Vref, and the reference signal Vref is a direct current signal.

Illustratively, the orthographic projection of the reference signal line 31 on the substrate, the orthographic projection of the first reset signal line 32 on the substrate and the orthographic projection of the gate line 33 on the substrate are sequentially arranged along the second direction.

Illustratively, the power line 38 and the data line 39 are arranged along the first direction.

Illustratively, the power line 38 and the data line 39 are disposed in the same layer and material.

Illustratively, the power supply line 38 is shown providing a positive power supply signal ELVDD and the cathode of the light emitting element receives a negative power supply signal ELVSS.

Illustratively, the first reset sub-circuit 12 and the driving sub-circuit 10 are aligned along the second direction.

Illustratively, the orthographic projection of the driving sub-circuit 10 on the substrate, the orthographic projection of the storage sub-circuit 11 on the substrate, and the orthographic projection of the first resetting sub-circuit 12 on the substrate are located between the orthographic projection of the power line 38 on the substrate and the orthographic projection of the data line 39 on the substrate.

As shown in fig. 1 to 6 and 8, in some embodiments, the at least two light emission control signal lines include a first light emission control signal line 34 and a second light emission control signal line 35; the at least two light emission control sub-circuits comprise a first light emission control sub-circuit 15 and a second light emission control sub-circuit 16; the at least two light-emitting elements include a first light-emitting element EL1 and a second light-emitting element EL 2;

the first light-emitting control sub-circuit 15 is respectively coupled to the second terminal of the driving sub-circuit 10, the first light-emitting control signal line 34 and the first light-emitting element EL 1; the second light-emitting control sub-circuit 16 is coupled to the second terminal of the driving sub-circuit 10, the second light-emitting control signal line 35 and the second light-emitting element EL2, respectively.

Illustratively, the first light emission control signal line 34 and the second light emission control signal line 35 each extend in the first direction, and the first light emission control signal line 34 and the second light emission control signal line 35 are aligned in the second direction.

Illustratively, the organic light emitting material layer of the first light emitting element EL1 and the organic light emitting material layer of the second light emitting element EL2 are aligned in the first direction; or the organic light emitting material layer of the first light emitting element EL1 and the organic light emitting material layer of the second light emitting element EL2 are aligned in the second direction.

The first light emission control sub-circuit 15 is capable of controlling to turn on or off the connection between the second terminal of the driving sub-circuit 10 and the first light emitting element EL1 under the control of the first light emission control signal line 34. The second light-emission control sub-circuit 16 is capable of controlling to turn on or off the connection between the second terminal of the driving sub-circuit 10 and the second light-emitting element EL2 under the control of the second light-emission control signal line 35.

For example, in the same display period, the first light-emitting control sub-circuit 15 controls to turn on the connection between the second terminal of the driving sub-circuit 10 and the corresponding first light-emitting element EL1, and the second light-emitting control sub-circuit 16 controls to turn on the connection between the second terminal of the driving sub-circuit 10 and the corresponding first light-emitting element EL 1.

Illustratively, as shown in fig. 10, one frame display time is divided into a first half frame and a second half frame, each of which includes a signal writing period P11 and a light emitting period P12. In the signal writing period in the first half frame, the compensation driving sub-circuit completes the process of gray-scale writing and compensation corresponding to the first light emitting element EL 1. In the light emission period in the first half frame, the first light emission control sub-circuit 15 controls to turn on the connection between the output terminal of the compensation driving sub-circuit and the corresponding first light emitting element EL1 under the control of the first light emission control signal line 34, causing the first light emitting element EL1 to emit light; under the control of the second light-emission control signal line 35, the second light-emission control sub-circuit 16 controls to disconnect the output terminal of the compensation driving sub-circuit from the corresponding second light-emitting element EL2, so that the second light-emitting element EL2 does not emit light.

In the signal writing period in the second half frame, the compensation driving sub-circuit completes the process of gray-scale writing and compensation corresponding to the second light emitting element EL 2. In the light emission period in the second half frame, the first light emission control sub-circuit 15 controls to disconnect the output terminal of the compensation driving sub-circuit from the corresponding first light emitting element EL1 under the control of the first light emission control signal line 34 so that the first light emitting element EL1 does not emit light; under the control of the second light-emission control signal line 35, the second light-emission control sub-circuit 16 controls to turn on the connection between the output terminal of the compensation driving sub-circuit and the corresponding second light-emitting element EL2, so that the second light-emitting element EL2 emits light.

It should be noted that, when each sub-pixel group includes N sub-pixels, where N is an integer greater than or equal to 2, each frame of display time may be divided into N sub-frames, and gray scale writing, compensation, and display may be performed on the corresponding light emitting elements in each sub-frame. When each frame of display time is divided into N sub-frames, the gray scale writing and signal compensation through holes corresponding to each sub-frame can be realized without mutual interference, so that the N light-emitting elements can be independently controlled.

In the display substrate provided by the above embodiment, N sub-pixels may share one pixel driving circuit, so that time-sharing display or simultaneous display of each sub-pixel is realized, and an independent pixel driving circuit is not provided for each pixel, thereby well improving the layout space utilization rate of the pixel driving circuit in the display substrate.

As shown in fig. 1 to 5, 7 and 9, in some embodiments, the first light emission control sub-circuit 15 includes a first transistor T1, the second light emission control sub-circuit 16 includes a second transistor T2, and the driving sub-circuit 10 includes a driving transistor DTFT; the storage sub-circuit 11 includes a storage capacitor Cst;

the gate g of the driving transistor DTFT is multiplexed as the first plate Cst1 of the storage capacitor Cst;

the second plate Cst2 of the storage capacitor Cst is located at a side of the first plate Cst1 facing away from the substrate, and the second plate Cst2 is coupled to the second pole of the driving transistor DTFT;

a first pole of the first transistor T1 is coupled to a second pole of the driving transistor DTFT, and a second pole of the first transistor T1 is coupled to a first light emitting element EL 1;

a first pole of the second transistor T2 is coupled to the second pole Cst2, and a second pole of the second transistor T2 is coupled to the second light emitting element EL 2.

Illustratively, as shown in fig. 2, the driving transistor DTFT includes a driving active pattern 56, the driving active pattern 56 includes a portion extending in the first direction and a portion extending in the second direction, an orthogonal projection of the driving active pattern 56 on the substrate partially overlaps an orthogonal projection of the gate electrode of the driving transistor DTFT on the substrate, a first terminal of the driving active pattern 56 serves as a first pole of the driving transistor DTFT, a second terminal of the driving active pattern 56 serves as a second pole of the driving transistor DTFT, an orthogonal projection of the first terminal of the driving active pattern 56 on the substrate overlaps an orthogonal projection of the power line 38 on the substrate, at this overlap, a first terminal of the driving active pattern 56 is coupled to the power line 38 through a first via 21, a second terminal of the driving active pattern 56 is coupled to a first pole of the first transistor T1.

Illustratively, the orthographic projection of the second end of the driving active pattern 56 on the substrate overlaps with the orthographic projection of the second plate Cst2 on the substrate, and at the overlap, the second end of the driving active pattern 56 is coupled with the second plate Cst2 through the second via 22.

As shown in fig. 1, 2, 7 and 9, in some embodiments, the first transistor T1 includes a first active pattern 51, the first active pattern 51 extending in the second direction; a first terminal of the first active pattern 51 is coupled to a second terminal of the driving transistor DTFT; a second end of the first active pattern 51 is coupled with the first light emitting element EL 1;

an orthogonal projection of a second end of the first active pattern 51 on the substrate is located between an orthogonal projection of the first emission control signal line 34 on the substrate and an orthogonal projection of the second emission control signal line 35 on the substrate.

Illustratively, the first active pattern 51 extends along the second direction, an orthographic projection of the first active pattern 51 on the substrate partially overlaps an orthographic projection of the first emission control signal line 34 on the substrate, the first emission control signal line 34 is multiplexed as a gate of the first transistor T1, a first end of the first active pattern 51 serves as a first pole of the first transistor T1, and a second end of the first active pattern 51 serves as a second pole of the first transistor T1.

Illustratively, neither the first end nor the second end of the first active pattern 51 overlaps the first light emission control signal 34 line.

Illustratively, the first end of the first active pattern 51 and the second end of the driving active pattern 56 are formed as a unitary structure.

Illustratively, the second end of the first active pattern 51 is coupled to the anode of the first light emitting element EL1 through a third via 23.

As shown in fig. 1, 3, and 4, in some embodiments, the second plate Cst2 includes a main portion Cst21 and an extension portion Cst 22;

an orthographic projection of the main body portion Cst21 on the substrate at least partially overlaps with an orthographic projection of the gate electrode of the driving transistor DTFT on the substrate;

the extension Cst22 extends in the second direction, and an orthogonal projection of the extension Cst22 on the substrate overlaps with an orthogonal projection of the first light emission control signal line 34 and an orthogonal projection of the second light emission control signal line 35 on the substrate, respectively.

Illustratively, the main body portion and the extension Cst22 are formed as an integral structure.

Illustratively, the main body portion is a block shape, and the extension Cst22 is a bar shape.

Illustratively, an orthographic projection of the second end of the driving active pattern 56 on the substrate overlaps with an orthographic projection of the main body portion Cst21 on the substrate, where the second end of the driving active pattern 56 is coupled with the main body portion Cst21 through the second via 22.

Illustratively, an orthographic projection of one end of the extension Cst22, which is far away from the main body portion, on the substrate is located between an orthographic projection of the second light emission control signal line 35 on the substrate and an orthographic projection of the second reset signal line 36 on the substrate.

As shown in fig. 1, 2 and 4, in some embodiments, the second transistor T2 includes a second active pattern 52, at least a portion of the second active pattern 52 extends along the second direction, a first end of the second active pattern 52 is coupled to the extension Cst22, and a second end of the second active pattern 52 is coupled to the second light emitting element EL 2;

an orthographic projection of a first end of the second active pattern 52 on the substrate is positioned between an orthographic projection of the first emission control signal line 34 on the substrate and an orthographic projection of the second emission control signal line 35 on the substrate.

Illustratively, the second active pattern 52 is in the shape of a "l".

Illustratively, the second active pattern 52 includes a first portion and a second portion of a unitary structure, the first portion extending along the second direction, the second portion extending along the first direction, and an orthographic projection of the first portion on the substrate overlaps with an orthographic projection of the second emission control signal line 35 on the substrate.

Illustratively, a first terminal of the second active pattern 52 serves as a first pole of the second transistor T2, and a second terminal of the second active pattern 52 serves as a second pole of the second transistor T2. An orthographic projection of the first end of the second active pattern 52 on the substrate overlaps with an orthographic projection of the extension Cst22 on the substrate, where the first end of the second active pattern 52 and the extension Cst22 are coupled through the fourth via 24. A second end of the second active pattern 52 is coupled to the anode of the second light emitting element EL2 through a fifth via 25.

Illustratively, the orthographic projection of the second end of the second active pattern 52 on the substrate is located between the orthographic projection of the second emission control signal line 35 on the substrate and the orthographic projection of the second reset signal line 36 on the substrate.

As shown in fig. 1-3, 6 and 8, in some embodiments, the pixel driving circuit further includes:

an initialization signal line 37, at least a part of the initialization signal line 37 extending in the first direction;

a second reset signal line 36, at least a part of the second reset signal line 36 extending in the first direction; the first reset signal line 32, the gate line 33, the first light emission control signal line 34, the second light emission control signal line 35, and the second reset signal line 36 are sequentially arranged along the second direction;

the second reset sub-circuit 14 is coupled to the second reset signal line 36, the initialization signal line 37 and the extension Cst22, respectively.

Illustratively, the initialization signal line 37 is used to provide a reference signal Vref having a fixed potential.

Illustratively, the initialization signal line 37 is provided in the same material as the active pattern in each transistor.

Illustratively, the initialization signal line 37 is disposed in the same material in the same layer as the gate line 33.

Illustratively, the initialization signal line 37 and the second plate Cst2 of the storage capacitor Cst are disposed in the same layer and material.

Illustratively, the orthographic projection of the second reset signal line 36 on the substrate is located between the orthographic projection of the second emission control signal line 35 on the substrate and the orthographic projection of the initialization signal line 37 on the substrate.

The second reset sub-circuit 14 can control to turn on or off the connection between the initialization signal line 37 and the extension Cst22 under the control of the second reset signal line 36.

As shown in fig. 1 to 3, 7 and 9, in some embodiments, the second reset sub-circuit 14 includes a fifth transistor T5, the fifth transistor T5 includes a fifth active pattern 55, and the fifth active pattern 55 extends in the second direction;

a first end of the fifth active pattern 55 is coupled to the extension Cst22, and an orthogonal projection of the first end of the fifth active pattern 55 on the substrate is located between an orthogonal projection of the second emission control signal line 35 on the substrate and an orthogonal projection of the second reset signal line 36 on the substrate.

Illustratively, an orthogonal projection of the fifth active pattern 55 on the substrate overlaps an orthogonal projection of the second reset signal line 36 on the substrate, a first terminal of the fifth active pattern 55 serves as the second pole of the fifth transistor T5, and a second terminal of the fifth active pattern 55 serves as the first pole of the fifth transistor T5.

Illustratively, an orthographic projection of the first end of the fifth active pattern 55 on the substrate overlaps with an orthographic projection of the extension Cst22 on the substrate, where the first end of the fifth active pattern 55 and the extension Cst22 are coupled through the sixth via 26.

As shown in fig. 2, in some embodiments, the fifth active pattern 55 is provided to be formed as a unitary structure with the initialization signal line 37.

The above arrangement enables the fifth active pattern 55 and the initialization signal line 37 to be formed in the same patterning process, thereby effectively simplifying the manufacturing process of the display substrate and reducing the manufacturing cost.

As shown in fig. 1 to 3, 7 and 9, in some embodiments, an orthogonal projection of the first reset signal line 32 on the substrate is located between an orthogonal projection of the reference signal line 31 on the substrate and an orthogonal projection of the gate line 33 on the substrate;

the first reset sub-circuit 12 includes a third transistor T3, the third transistor T3 includes a third active pattern 53, the third active pattern 53 extends in the second direction, a first end of the third active pattern 53 is coupled to the reference signal line 31, and an orthogonal projection of a second end of the third active pattern 53 on the substrate is located between an orthogonal projection of the first reset signal line 32 on the substrate and an orthogonal projection of the gate line 33 on the substrate.

Illustratively, the orthographic projection of the third active pattern 53 on the substrate partially overlaps the orthographic projection of the first reset signal line 32 on the substrate. A first end of the third active pattern 53 serves as a first pole of the third transistor T3, a second end of the third active pattern 53 serves as a second pole of the third transistor T3, an orthogonal projection of the first end of the third active pattern 53 on the substrate overlaps an orthogonal projection of the reference signal line 31 on the substrate, and at the overlap, the first end of the third active pattern 53 is coupled to the reference signal line 31 through a seventh via 27.

As shown in fig. 1 to 3, 7 and 9, in some embodiments, the gate line 33 includes a gate main portion 331 and two gate protrusions 332, the gate main portion 331 extends along the first direction, the two gate protrusions 332 are spaced apart along the first direction, and the two gate protrusions 332 are located between the gate main portion 331 and the first reset signal line 32;

the data writing sub-circuit 13 includes a fourth transistor T4, the fourth transistor T4 includes a fourth active pattern 54, the fourth active pattern 54 extends along a first direction, orthographic projections of the fourth active pattern 54 on the substrate overlap with orthographic projections of the two gate protrusions 332 on the substrate, respectively;

a first terminal of the fourth active pattern 54 is coupled to the data line 39 and a second terminal of the fourth active pattern 54 is coupled to a second terminal of the third active pattern 53.

Illustratively, the gate main body portion 331 and the two gate protrusions 332 are formed as an integral structure.

Illustratively, the gate protrusion 332 extends in the second direction.

Illustratively, the orthographic projections of the two grating protrusions 332 on the substrate are located between the orthographic projection of the grating main body portion 331 on the substrate and the orthographic projection of the first reset signal line 32 on the substrate.

Illustratively, the two gate protrusions 332 are multiplexed as the gate of the fourth transistor T4, and the fourth transistor T4 has a double gate structure.

For example, the fourth transistor T4 may be formed in a common structure having only one gate.

Illustratively, a first terminal of the fourth active pattern 54 serves as a first pole of the fourth transistor T4, and a second terminal of the fourth active pattern 54 serves as a second pole of the fourth transistor T4.

Illustratively, the orthographic projection of the first end of the fourth active pattern 54 on the substrate overlaps the orthographic projection of the data line 39 on the substrate, and at the overlap, the first end of the fourth active pattern 54 is coupled to the data line 39 through the eighth via 28.

Illustratively, the second end of the fourth active pattern 54 is formed as a unitary structure with the second end of the third active pattern 53.

Illustratively, the third active pattern 53 and the fourth active pattern 54 are collectively formed in an L shape.

It should be noted that the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the driving transistor DTFT are various in specific types, and for example, NMOS transistors are used.

When the pixel driving circuit includes: when the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the driving transistor DTFT are used, as shown in fig. 11, the operation of the pixel driving circuit in the signal writing period is as follows:

in the P111 phase of the signal writing period, the third transistor T3 is turned on under the control of the first reset signal G1 written in the first reset signal line 32, and the reference signal Vref is written to the gate (i.e., G point) of the driving transistor DTFT; under the control of the second reset signal G2 written on the second reset signal line 36, the fifth transistor T5 is turned on, and the initialization signal Vint is written to the source (i.e., point s) of the driving transistor DTFT.

In the P112 phase of the signal writing period, the voltage of the reference signal Vref is higher than that of the initialization signal Vint, the driving transistor DTFT is turned on, the s-point voltage rises, when the s-point voltage rises to Vref-Vth, Vth is equal to the threshold voltage of the driving transistor DTFT, Vgs-Vth of the driving transistor DTFT is equal to 0, Vgs is the voltage difference between the gate and the source of the driving transistor DTFT, and thus the driving transistor DTFT is turned off.

In the phase P113 of the signal writing period, under the control of the scanning signal G3 written by the gate line 33, the fourth transistor T4 is turned on, and the data signal DA transmitted by the data line 39 is written into the G point, and due to the coupling effect of the storage capacitor Cst and the inherent capacitance Coled of the OLED itself, the s point voltage is changed to Vref-Vth + a (Vdata-Vref), where a is C1/(C1+ Coled), C1 is the capacitance value of the storage capacitor Cst, and Vdata is the voltage value of the data signal DA. The final driving current flowing through the driving transistor DTFT is I ═ k × (Vgs-Vth) ^2 ═ k [ (1-a) × (Vdata-Vref) ] ^2, and the magnitude of the driving current is independent of Vth, thereby compensating for Vth.

As shown in fig. 1 and 5, in some embodiments, the pixel driving circuit includes a conductive connection portion 40, at least a portion of the conductive connection portion 40 extends along the second direction, and an orthogonal projection of the conductive connection portion 40 on the substrate overlaps with an orthogonal projection of the gate line 33 on the substrate;

a first terminal of the conductive connection portion 40 is coupled to a second terminal of the third active pattern 53, and a second terminal of the conductive connection portion 40 is coupled to a control terminal of the driving sub-circuit 10.

Illustratively, an orthographic projection of the first end of the conductive connection portion 40 on the substrate overlaps with an orthographic projection of the second end of the third active pattern 53 on the substrate, and at the overlap, the first end of the conductive connection portion 40 and the second end of the third active pattern 53 are coupled through the ninth via 29. An orthogonal projection of the second end of the conductive connection portion 40 on the substrate overlaps an orthogonal projection of the gate electrode of the driving transistor DTFT on the substrate, and the second end of the conductive connection portion 40 is coupled to the gate electrode of the driving transistor DTFT through a tenth via 20.

Illustratively, an orthographic projection of the conductive connection part 40 on the substrate does not overlap with an orthographic projection of the second plate Cst2 on the substrate.

It should be noted that the display substrate includes an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer insulating layer, a first source drain metal layer, a planarization layer, and the like, which are sequentially stacked along a direction away from the substrate.

Illustratively, the active layer is used to form an active pattern included in each transistor, initializing the signal line 37; the first gate metal layer is used for forming the first reset signal line 32, the gate, the first light-emitting control signal line 34, the second light-emitting control signal line 35 and the second reset signal line 36; the second gate metal layer is used to form the reference signal line 31, the second plate Cst2, and some conductive connections 40; the first source-drain metal layer is used to form the power line 38, the data line 39 and some conductive connections 40.

It should be noted that the first through fourth vias 21 through 20 can penetrate through one or more film layers.

The second pole of the first transistor T1 and the second pole of the second transistor T2 may be coupled to the anode of the corresponding light emitting element through a connection portion (e.g., marks 41 and 42) formed by the second gate metal layer and the first source-drain metal layer, and a corresponding via hole.

In the display substrate provided by the embodiment, when the layout mode is adopted, the layout space can be effectively utilized, and the resolution of the display substrate is maximized.

The invention also provides a display device which comprises the display substrate provided by the embodiment.

In the display substrate provided in the above embodiment, one pixel driving circuit can be multiplexed by at least two sub-pixels, and the pixel driving circuit can independently control the light emitting elements included in each of the at least two sub-pixels to independently emit light or simultaneously emit light.

The display device provided by the embodiment of the invention has the beneficial effects when the display device comprises the display substrate, and the description is omitted.

The display device may be: any product or component with a display function, such as a television, a display, a digital photo frame, a mobile phone, a tablet computer and the like.

In some embodiments, the at least two light emission control signal lines in the display substrate include a first light emission control signal line 34 and a second light emission control signal line 35; the at least two light emission control sub-circuits include a first light emission control sub-circuit 15 and a second light emission control sub-circuit 16; the at least two light-emitting elements include a first light-emitting element EL1 and a second light-emitting element EL 2;

a plurality of pixel driving circuits included in a plurality of sub-pixel groups in the display substrate are distributed in an array, the plurality of pixel driving circuits are divided into a plurality of rows of pixel driving circuits arranged along the second direction, first light-emitting control signal lines 34 in each row of pixel driving circuits are sequentially coupled, and second light-emitting control signal lines 35 in each row of pixel driving circuits are sequentially coupled;

the output end of the first shift register unit is coupled to the first light emission control signal line 34 in the corresponding row of pixel driving circuits, and the output end of the second shift register unit is coupled to the second light emission control signal line 35 in the corresponding row of pixel driving circuits.

In an exemplary embodiment, in the display substrate, the plurality of sub-pixel groups include a plurality of pixel driving circuits distributed in an array, and the plurality of pixel driving circuits can be divided into a plurality of rows of pixel driving circuits and a plurality of columns of pixel driving circuits.

The plurality of rows of pixel driving circuits are sequentially arranged along the second direction, and each row of pixel driving circuits comprises a plurality of pixel driving circuits arranged along the first direction. The plurality of rows of pixel driving circuits are sequentially arranged along the first direction, and each row of pixel driving circuits comprises a plurality of pixel driving circuits arranged along the second direction.

In the same row of pixel driving circuits, the reference signal lines 31 are sequentially coupled to form an integral structure, the first reset signal lines 32 are sequentially coupled to form an integral structure, the gate lines 33 are sequentially coupled to form an integral structure, the first light-emitting control signal lines 34 are sequentially coupled to form an integral structure, the second light-emitting control signal lines 35 are sequentially coupled to form an integral structure, the second reset signal lines 36 are sequentially coupled to form an integral structure, and the initialization signal lines 37 are sequentially coupled to form an integral structure.

In the same column of pixel driving circuits, the power lines 38 are sequentially coupled to form an integral structure, and the data lines 39 are sequentially coupled to form an integral structure.

As shown in fig. 12, for example, the gate driving circuit includes a plurality of first shift register cells EM1 GOA and a plurality of second shift register cells EM2 GOA; the plurality of first shift register units correspond to the plurality of rows of pixel driving circuits one to one, and the plurality of second shift register units correspond to the plurality of rows of pixel driving circuits one to one; the output end of the first shift register unit is coupled to the first light emission control signal line 34 in the corresponding row of pixel driving circuits, and the output end of the second shift register unit is coupled to the second light emission control signal line 35 in the corresponding row of pixel driving circuits.

Illustratively, the gate driving circuit includes a plurality of third shift register cells G3 GOA, which are in one-to-one correspondence with the plurality of rows of pixel driving circuits, and the output terminals of the third shift register cells are coupled to the gate lines 33 in the corresponding row of pixel driving circuits.

Illustratively, the gate driving circuit includes a plurality of fourth shift register cells G1 GOA, which are in one-to-one correspondence with the plurality of rows of pixel driving circuits, and whose outputs are coupled to the first reset signal lines 32 in the corresponding row of pixel driving circuits.

Illustratively, the gate driving circuit includes a plurality of fifth shift register cells G2 GOA, which correspond to the plurality of rows of pixel driving circuits in a one-to-one manner, and whose output terminals are coupled to the second reset signal lines 36 in the corresponding row of pixel driving circuits.

For example, a shift register unit corresponding to a row of pixel driving circuits may be disposed on one side of the display substrate, i.e., single-side driving is realized; or a shift register unit corresponding to a row of pixel driving circuits may be disposed on two opposite sides of the display substrate, i.e., to implement double-sided driving.

Illustratively, the gate driving circuit includes N first shift register units EM1 GOA, the N first shift register units EM1 GOA are cascaded, that is, the output terminal of the N-1 st first shift register unit EM1 GOA is coupled to the first light emission control signal line 34 in the corresponding row of pixel driving circuits, the output terminal of the N-1 st first shift register unit EM1 GOA is also simultaneously coupled to the input signal terminal of the N first shift register unit EM1 GOA, the N-1 st first shift register unit EM1 GOA simultaneously writes the first light emission control signal line 34 in the corresponding row of pixel driving circuits, and the input signal terminal of the N first shift register unit EM1 GOA writes the first light emission control signal.

Similarly, the plurality of second shift register units EM2 GOA, the plurality of third shift register units G3 GOA, the plurality of fourth shift register units G1 GOA, and the plurality of fifth shift register units G2 GOA all satisfy the cascade relationship, and are not described herein again.

As shown in fig. 6, an embodiment of the present invention further provides a pixel driving circuit for driving at least two light emitting elements to emit light, the pixel driving circuit including:

a driving sub-circuit 10, a first terminal of the driving sub-circuit 10 being coupled to a first level signal input terminal;

a first reset sub-circuit 12 coupled to a first reset signal input terminal, a reference signal input terminal and a control terminal of the driving sub-circuit 10, respectively;

a data writing sub-circuit 13 coupled to the scan signal input terminal, the data signal input terminal and the control terminal of the driving sub-circuit 10, respectively; and the number of the first and second groups,

at least two light-emitting control sub-circuits, wherein the at least two light-emitting control sub-circuits correspond to the at least two light-emitting elements one by one, and the at least two light-emitting control sub-circuits correspond to the at least two control signal output ends one by one; each of the light-emitting control sub-circuits is coupled to the second terminal of the driving sub-circuit 10, the corresponding control signal output terminal and the corresponding light-emitting element; each of the light-emitting control sub-circuits is configured to control to turn on or off the connection between the second terminal of the driving sub-circuit 10 and the corresponding light-emitting element under the control of the corresponding control signal output terminal.

In some embodiments, the at least two light-emitting elements include a first light-emitting element EL1 and a second light-emitting element EL 2; the at least two control signal output ends comprise a first control signal output end and a second control signal output end; the at least two light emission control sub-circuits comprise a first light emission control sub-circuit 15 and a second light emission control sub-circuit 16;

the first light-emitting control sub-circuit 15 is respectively coupled to the second terminal of the driving sub-circuit 10, the first control signal output terminal and the first light-emitting element EL 1; for controlling to turn on or off the connection between the second terminal of the driving sub-circuit 10 and the first light-emitting element EL1 under the control of the first control signal output terminal;

the second light-emitting control sub-circuit 16 is respectively coupled to the second terminal of the driving sub-circuit 10, the second control signal output terminal and the second light-emitting element EL 2; for controlling to switch on or off the connection between the second terminal of the driving sub-circuit 10 and the second light emitting element EL2 under the control of the second control signal output terminal.

As shown in fig. 7, in some embodiments, the first light-emitting control sub-circuit 15 includes a first transistor T1, a gate of the first transistor T1 is coupled to the first control signal output terminal, a first pole of the first transistor T1 is coupled to the second terminal of the driving sub-circuit 10, and a second pole of the first transistor T1 is coupled to the first light-emitting element EL 1.

As shown in fig. 7, in some embodiments, the second light emitting control sub-circuit 16 includes a second transistor T2, a gate of the second transistor T2 is coupled to the second control signal output terminal, a first pole of the second transistor T2 is coupled to the second terminal of the driving sub-circuit 10, and a second pole of the second transistor T2 is coupled to the second light emitting element EL 2.

As shown in fig. 7, in some embodiments, the driving sub-circuit 10 includes a driving transistor DTFT, a first pole of the driving transistor DTFT is coupled to the first level signal input terminal;

the storage sub-circuit 11 includes a storage capacitor Cst, a first plate Cst1 of which is coupled to the gate electrode of the driving transistor DTFT, and a second plate Cst2 of which is coupled to the second electrode of the driving transistor DTFT;

the first reset sub-circuit 12 includes a third transistor T3, a gate of the third transistor T3 is coupled to the first reset signal input terminal, a first pole of the third transistor T3 is coupled to the reference signal input terminal, and a second pole of the third transistor T3 is coupled to the gate of the driving transistor DTFT;

the data writing sub-circuit 13 includes a fourth transistor T4, a gate of the fourth transistor T4 is coupled to the scan signal input terminal, a first pole of the fourth transistor T4 is coupled to the data signal input terminal, and a second pole of the fourth transistor T4 is coupled to the gate of the driving transistor DTFT.

As shown in fig. 8, in some embodiments, the pixel driving circuit further includes:

a second reset sub-circuit 14, coupled to a second reset signal input terminal, an initialization signal input terminal and a second terminal of the driving sub-circuit 10, respectively; for controlling to switch on or off the connection between the initialization signal input terminal and the second terminal of the driving sub-circuit 10 under the control of the second reset signal input terminal.

As shown in fig. 9, in some embodiments, the second reset sub-circuit 14 includes a fifth transistor T5, a gate of the fifth transistor T5 is coupled to the second reset signal input terminal, a first pole of the fifth transistor T5 is coupled to the initialization signal input terminal, and a second pole of the fifth transistor T5 is coupled to the second terminal of the driving sub-circuit 10.

An embodiment of the present invention further provides a driving method for a pixel driving circuit, which is used to drive the pixel driving circuit provided in the foregoing embodiment, and the driving method includes:

in the light emitting stage, the at least two control signal output terminals respectively control the corresponding at least two light emitting control sub-circuits, so that each light emitting control sub-circuit controls to turn on or off the connection between the second terminal of the driving sub-circuit 10 and the corresponding light emitting element.

in the first light-emitting phase, the first light-emitting control sub-circuit 15 controls to turn on the connection between the second terminal of the driving sub-circuit 10 and the first light-emitting element EL1 under the control of the first control signal output terminal; the second light-emitting control sub-circuit 16 controls to disconnect the second end of the driving sub-circuit 10 from the second light-emitting element EL2 under the control of the second control signal output terminal;

in the second light-emitting phase, the first light-emitting control sub-circuit 15 controls to disconnect the second terminal of the driving sub-circuit 10 from the first light-emitting element EL1 under the control of the first control signal output terminal; the second light-emitting control sub-circuit 16 controls to turn on the connection between the second terminal of the driving sub-circuit 10 and the second light-emitting element EL2 under the control of the second control signal output terminal.

It should be noted that, in the present specification, all the embodiments are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the method embodiments, since they are substantially similar to the product embodiments, they are described simply, and reference may be made to the partial description of the product embodiments for relevant points.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected," "coupled," or "connected," and the like, are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A display substrate is characterized by comprising a substrate and a plurality of sub-pixels arranged on the substrate, wherein each sub-pixel comprises a light-emitting element;

2. The display substrate of claim 1, wherein the pixel driving circuit further comprises:

the compensation driving sub-circuit includes:

3. The display substrate according to claim 2, wherein the at least two light emission control signal lines include a first light emission control signal line and a second light emission control signal line; the at least two light emission control sub-circuits include a first light emission control sub-circuit and a second light emission control sub-circuit; the at least two light emitting elements include a first light emitting element and a second light emitting element;

4. The display substrate of claim 3, wherein the first emission control sub-circuit comprises a first transistor, the second emission control sub-circuit comprises a second transistor, and the driving sub-circuit comprises a driving transistor; the storage sub-circuit comprises a storage capacitor;

5. The display substrate according to claim 4, wherein the first transistor comprises a first active pattern extending in the second direction; a first end of the first active pattern is coupled with a second pole of the driving transistor; a second end of the first active pattern is coupled with the first light emitting element;

6. The display substrate of claim 4, wherein the second plate comprises a main portion and an extension portion;

7. The display substrate according to claim 6, wherein the second transistor comprises a second active pattern, at least a portion of the second active pattern extending in the second direction, a first end of the second active pattern being coupled to the extension portion, a second end of the second active pattern being coupled to the second light emitting element;

8. The display substrate of claim 6, wherein the pixel driving circuit further comprises:

9. The display substrate according to claim 8, wherein the second reset sub-circuit comprises a fifth transistor including a fifth active pattern, the fifth active pattern extending in the second direction;

10. The display substrate of claim 9, wherein the fifth active pattern and the initialization signal line are formed as a single structure.

11. The display substrate according to claim 2, wherein an orthographic projection of the first reset signal line on the substrate is located between an orthographic projection of the reference signal line on the substrate and an orthographic projection of the gate line on the substrate;

12. The display substrate according to claim 11, wherein the gate line includes a gate main portion extending in the first direction and two gate protruding portions spaced apart in the first direction, the two gate protruding portions being located between the gate main portion and the first reset signal line;

13. The display substrate according to claim 12, wherein the pixel driving circuit comprises a conductive connection portion, at least a portion of the conductive connection portion extends in the second direction, and an orthogonal projection of the conductive connection portion on the substrate overlaps an orthogonal projection of the gate line on the substrate;

14. A display device comprising the display substrate according to any one of claims 1 to 13.

15. The display device according to claim 14, wherein the at least two light emission control signal lines in the display substrate include a first light emission control signal line and a second light emission control signal line; the at least two light emission control sub-circuits include a first light emission control sub-circuit and a second light emission control sub-circuit; the at least two light emitting elements include a first light emitting element and a second light emitting element;