CN114002885B

CN114002885B - Array substrate, display panel and display device

Info

Publication number: CN114002885B
Application number: CN202111280663.XA
Authority: CN
Inventors: 冯伟; 吴鹏; 钱勇
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2021-10-29
Filing date: 2021-10-29
Publication date: 2023-08-08
Anticipated expiration: 2041-10-29
Also published as: CN114002885A

Abstract

The embodiment of the application provides an array substrate, a display panel and a display device, wherein the array substrate comprises a unit area and a wiring area positioned at one side of the unit area, the unit area is provided with a plurality of cascaded shift register units, the wiring area is provided with a plurality of signal wires for controlling the shift register units, at least one signal wire is a first signal wire, the first signal wire is connected with the shift register units through a first connecting wire, and the shift register units comprise first connecting ends connected with the first connecting wire; the array substrate comprises a grid layer, a grid insulating layer, a source drain metal layer, a passivation layer and an electrode layer which are sequentially stacked; the first connecting end is positioned on the grid electrode layer, the first signal line is positioned on the grid electrode layer or the source-drain metal layer, and the first connecting line comprises part or all of the electrode layer and the electrode layer. Because the connection line is partially or completely manufactured in the electrode layer process, the signal line and the GOA unit are in a disconnected state in the passivation layer manufacturing process, and even if ESD occurs, the ESD does not enter the GOA unit.

Description

Array substrate, display panel and display device

Technical Field

The embodiment of the application relates to the technical field of display devices, in particular to an array substrate, a display panel and a display device.

Background

In the display panel, the Gate driving circuit adopts GOA (Gate Driver on Array, array substrate row driving) design, that is, the Gate driving circuit is integrated on the array substrate of the display panel, instead of a driving chip made of an external silicon chip, a Gate IC (GateIntegrated Circuit, gate driving integrated circuit) part and a Fanout (Fanout) wiring space can be omitted, so that the structure of the array substrate is simplified. The gate driving circuit integrated on the array substrate using the GOA technology is also called a GOA circuit.

The grid driving circuit comprises cascaded multistage shift register units, signal lines for driving the shift register units to work and connecting lines for connecting the signal lines and the shift register units. In the manufacturing process of the array substrate, the gate driving circuit is provided with a process of manufacturing the organic film layer and the passivation layer after the manufacturing is completed, however, in the manufacturing process of the organic film layer and the passivation layer, ESD (Electro-Static discharge) is easy to occur, the characteristics of a thin film transistor in a shift register unit are affected, breakdown failure is caused when the characteristics are serious, and then abnormal display is caused when the subsequent lighting is performed, so that the quality and the performance of a product are affected.

Disclosure of Invention

In view of the foregoing, an object of the embodiments of the present application is to provide an array substrate, a display panel and a display device.

In a first aspect, an embodiment of the present application provides an array substrate, including a unit area and a routing area located at one side of the unit area, where the unit area is provided with a plurality of cascaded shift register units, the routing area is provided with a plurality of signal lines for controlling the shift register units, at least one signal line is a first signal line, the first signal line is connected with the shift register units through a first connection line, and the shift register units include a first connection end connected with the first connection line;

the array substrate comprises a grid layer, a grid insulating layer, a source-drain metal layer, a passivation layer and an electrode layer which are sequentially stacked; the first connecting end is located on the grid electrode layer, the first signal line is located on the grid electrode layer or the source-drain metal layer, and the first connecting line comprises part or all of the electrode layer and the electrode layer.

In the array substrate provided by the embodiment of the application, the connecting line for connecting the signal line and the GOA unit is partially or completely manufactured in the electrode layer process, so that the signal line and the GOA unit are in a disconnected state when the array substrate is manufactured with the passivation layer, and even if ESD occurs, the ESD cannot enter the GOA unit, so that the characteristics of the thin film transistor in the GOA unit cannot be influenced and breakdown failure is avoided.

In one possible embodiment, the first connection line includes a first combination section, a second combination section, and a third combination section, the first signal line is located at one of the gate layer and the source-drain metal layer, and the first combination section and the second combination section are located at the other of the gate layer and the source-drain metal layer;

the first combined section is connected with the first signal line through a first via hole, the second combined section is connected with the first connecting end through a second via hole, the third combined section is positioned on the electrode layer and connected with the first combined section through a third via hole, and the third combined section is connected with the second combined section through a fourth via hole;

the third via hole, the fourth via hole and the third combined section are of a structure which is manufactured in the same layer as the electrode layer.

In one possible implementation manner, the array substrate comprises a data binding side and a data binding opposite side which are oppositely arranged, and the routing area and the unit area are positioned between the data binding side and the data binding opposite side; the first connection line is led out from one side of the wiring area close to the data binding opposite side and extends into the unit area at the data binding opposite side.

In one possible embodiment, the second combined section and the third combined section are located in the cell region.

In one possible embodiment, at least one of the first via, the second via, the third via, and the fourth via is a dual via structure.

In a possible embodiment, the first combined section extends from the corresponding first signal line in a direction between the unit region and the trace region, and the second combined section and the third combined section are located in the unit region.

In one possible implementation manner, the first signal line is located on the gate layer or the source drain metal layer;

the first connecting wire comprises a connecting wire body, the connecting wire body extends from the corresponding first signal wire along the direction between the unit area and the wiring area, one end of the connecting wire body is connected with the first signal wire through a first via hole, and the other end of the connecting wire body is connected with the first connecting end through a second via hole; the connecting wire body, the first via hole and the second via hole are of structures which are manufactured in the same layer as the electrode layer.

In one possible implementation manner, an intermediate transfer disc is arranged between the second via hole and the first connection end, and the intermediate transfer disc is located on the source drain metal layer and is connected with the first connection end through the via hole.

In one possible implementation, the first via or the second via is a dual via structure.

In one possible embodiment, the electrode layer is a transparent metal layer made of indium tin oxide or indium zinc oxide.

In one possible implementation manner, at least one signal line is a second signal line, and the second signal line includes a broken fourth combined section and a fifth combined section, and an intermediate combined section connecting the first combined section and the second combined section through a via hole, where the intermediate combined section is a structure manufactured in the same layer as the electrode layer.

In one possible implementation manner, a plurality of signal lines are arranged side by side in the wiring area along a direction away from the unit area, a frame start signal line is arranged on the outer side of the wiring area away from the unit area, and the first connection line comprises a frame start signal line.

In one possible implementation manner, the array substrate comprises an organic film layer, the passivation layer comprises a first passivation layer and a second passivation layer which are positioned on two sides of the organic film layer, the first passivation layer is arranged on one side of the source drain metal layer, and the electrode layer is arranged on one side of the second passivation layer.

In a second aspect, embodiments of the present application also provide a display panel, including the array substrate according to any one of the embodiments of the first aspect, further including a color film substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color film substrate.

In a third aspect, embodiments of the present application also provide a display device including the display panel described in the second aspect embodiment.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related art, the drawings that are required to be used in the embodiments or the related technical descriptions will be briefly described, and it is apparent that the drawings in the following description are only one or more embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

Fig. 1 is a schematic structural diagram of a liquid crystal display panel according to an embodiment of the present disclosure;

fig. 2 is a front view of an array substrate according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a GOA circuit according to an embodiment of the present disclosure;

fig. 4 is a schematic stacking diagram of an array substrate according to an embodiment of the present application

FIG. 5 is a schematic diagram showing the connection between the first segment and the STV signal line in FIG. 3;

FIG. 6 is a schematic diagram showing the connection of the first, second and third combined sections in FIG. 3;

fig. 7 is a schematic structural diagram of another first connection line according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of another first connection line according to an embodiment of the present disclosure;

FIG. 9 is a schematic diagram illustrating the connection between the connecting wire body and the first connecting terminal in FIG. 8;

fig. 10 is a schematic connection diagram of the connecting wire body and the first connecting end in the other embodiment of fig. 8;

fig. 11 is a schematic diagram of a portion of another GOA circuit according to an embodiment of the present application.

Reference numerals illustrate:

the liquid crystal display device comprises a 1-array substrate, a 2-liquid crystal layer, a 3-color film substrate, a 4-fourth side, a 5-first side, a 6-data driving circuit, a 7-grid driving circuit, an 8-third side, a 9-second side, a 10-display area, a 11-routing area, a 12-unit area, a 13-first via hole, a 14-first combined section, a 15-third combined section, a 16-second combined section, a 17-first connecting end, a 18-second via hole, a 19-fourth via hole, a 20-third via hole, a 21-grid layer, a 22-substrate, a 23-grid insulating layer, a 24-first passivation layer, a 25-organic film layer, a 26-electrode layer, a 27-second passivation layer, a 28-source drain metal layer, a 29-connecting wire body, a 30-intermediate switching disc, a 31-fourth combined section, a 32-fifth combined section and a 33-intermediate combined section.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

The embodiment of the application provides a display device, which can be a device which needs to display content, such as a mobile phone, a notebook computer, a tablet personal computer, a television, a display, a vehicle-mounted display device, a wearable device, a touch integrated machine or a conference large screen, and the like, wherein the display device comprises a liquid crystal display panel, and the liquid crystal display panel can be any type of display modes, such as a Twisted Nematic (TN) mode, an in-plane switching (IPS, in Plane Switching) mode, an advanced super-dimensional field switch (ADS, advanced Super Dimension Switch) mode, an ultra-high-level super-dimensional field switch (HADS, highAdvanced Super Dimension Switch) mode, and the like.

Fig. 1 is a schematic structural diagram of a liquid crystal display panel according to an embodiment of the present application, as shown in fig. 1, the liquid crystal display panel includes an Array substrate 1 (Array), a color film substrate 3 (CF) and a liquid crystal layer 2 (LC), and after the Array substrate 1 and the color film substrate 3 are aligned to a Cell (Cell), the liquid crystal layer 2 is filled between the Array substrate 1 and the color film substrate 3. The liquid crystal display panel comprises a pixel array formed by arranging a plurality of pixel units, wherein the pixel array comprises pixel rows extending along a first direction and pixel columns extending along a second direction. The peripheral area is disposed at the outer periphery of the display area 10. In addition, the box alignment direction of the array substrate 1 and the color film substrate 3 is defined as a third direction, the first direction, the second direction and the third direction are perpendicular to each other, and the third direction is also parallel to the light emitting direction of the liquid crystal display panel.

Fig. 2 is a front view of an array substrate provided in this embodiment, that is, a schematic structural diagram in a plane perpendicular to a light emitting direction, as shown in fig. 2, a display area 10 (Active aero, abbreviated as AA area) and a peripheral area of the array substrate 1, the display area 10 is an area corresponding to a pixel array, a pixel circuit for controlling display of pixel units is disposed in the display area 10, the pixel circuit includes a plurality of gate lines and a plurality of data lines which are disposed in a crossing manner, and further includes a thin film transistor connected between the gate lines and the data lines, the thin film transistor is disposed corresponding to the pixel units, so that the thin film transistor is referred to as a pixel transistor herein, the pixel transistors of the pixel units in the same row are connected to the same gate line, and the pixel transistors of the pixel units in the same column are connected to the same data line.

The array substrate 1 is provided with a gate driving circuit 7 connected to the gate lines and a data driving circuit 6 connected to the data lines in the peripheral region. In the display process of the liquid crystal display panel, outputting a gate scanning signal through the gate driving circuit 7 to scan and access each pixel unit in the pixel array line by line; the data driving circuit 6 may convert display data to be displayed into data voltage signals, and the data driving circuit 6 writes the data voltage signals into the pixel circuits of each row through each data line while each row of gate lines is scanned, so as to light the pixel units of the row, and finally display the whole display area 10.

The array substrate 1 and the display area 10 may have any shape, such as square, round, or rectangular, and in the embodiment shown in fig. 2, the first direction is a lateral direction extending from side to side, the second direction is a longitudinal direction extending up and down, and the array substrate 1 and the display area 10 are both rectangular, and both rectangles have sides parallel to the first direction and sides parallel to the second direction.

The peripheral zone comprises a first side 5 and a second side 9, which are arranged opposite in a first direction, and a third side 8 and a fourth side 4, which are arranged opposite in a second direction; the Data driving circuit 6 is bound to the third side 8 or the fourth side 4, and one side of the bound Data driving circuit 6 is often also referred to as DP (Data Pad, data bound side) side, and the side of the third side 8 and the fourth side 4 opposite to the DP side is often also referred to as DPO (Data Pad Opposite, data bound side) side. The gate driving circuit 7 may be disposed at the first side 5 or the second side 9, or may be disposed at a weight average of the first side 5 and the second side 9.

In the present embodiment, the first side 5 is located below the second side 9 and the third side 8 is located to the left of the fourth side 4. The DP side is the first side 5, the dpo side is the second side 9, and the gate driving circuit 7 is disposed on the third side 8.

The Gate driving circuit 7 adopts a GOA (Gate Driver on Array, array substrate 1 row driving) design, that is, the Gate driving circuit 7 is integrated on the array substrate 1 of the display panel, instead of a driving chip made of an external silicon chip, a Gate IC (GateIntegrated Circuit, gate driving integrated circuit) part and a fan-out (Fanout) wiring space can be omitted, so that the structure of the array substrate 1 is simplified. The gate driving circuit 7 integrated on the array substrate 1 using the GOA technique is also referred to as a GOA circuit.

The gate driving circuit 7 includes a cell region 12 and a track region 11 disposed adjacently in a first direction, and a plurality of stages of shift register units, which may be abbreviated as GOA units, cascaded in a second direction are disposed in the cell region 12, and the GOA units are connected to corresponding gate lines. The output signal of the current-stage GOA unit is output to the previous-stage GOA unit (if any) as a reset signal of the previous-stage GOA unit in addition to the pixel transistor for driving the pixel unit of the current row; and also to the next GOA unit, if any, as an input signal to the next GOA unit.

A plurality of signal lines for controlling the GOA units to operate are arranged side by side in the first direction in the routing area 11, and the signal lines extend in the second direction, and generally include a frame start signal line STV, a clock signal line CLK, power signal lines with different voltages, a Reset signal line Reset, and the like. The signal line is connected with the GOA unit through a connecting wire, and a connecting end connected with the connecting wire is arranged on the GOA unit.

Fig. 3 is a schematic diagram of a GOA circuit according to an embodiment of the present application, as shown in fig. 3, in the process of moving away from the cell area 12 relative to the second direction in the present embodiment, the signal lines include a frame start signal line STV, a clock signal line CLK, a first power signal line VDDE, a second power signal line VDDO, a third power signal line VGL, a fourth power signal line LVGL, and a RESET signal line RESET, wherein the clock signal line CLK further includes a fourth clock signal line CLK4, a third clock signal line CLK3, a second clock signal line CLK2, and a first clock signal line CLK1 between the frame start signal line STV and the first power signal line VDDE. The connecting wires connecting the signal lines and the GOA units are provided with a plurality of corresponding connecting wires.

As is apparent from the above description, the frame start signal line STV is located at the outermost side of the track area 11 far from the cell area 12, and is used as the INPUT signal INPUT of the GOA circuit which just starts one or several stages of GOA units. During operation of the gate driving circuit 7, a scanning signal is generally supplied from the DPO side, that is, the frame start signal line STV is connected only to one or several stages of GOA cells near the DPO side.

Fig. 4 is a schematic stacking diagram of an array substrate according to an embodiment of the present application, as shown in fig. 4, on a stacking structure, the array substrate 1 includes a substrate 22, a Gate layer (Gate) 21, a Gate insulating layer (GI) 23, a source drain metal layer (SD) 28, a passivation layer (PVX), and an electrode layer 26. The electrode layer 26 is a transparent metal layer made of a transparent metal oxide material such as ITO (Indium Tin Oxides, indium tin oxide), IZO (Indium Zin Oxides, indium zinc oxide), etc., and is used to manufacture an electrode in the array substrate 1.

Among them, in the array substrate 1 of some display panels, the array substrate 1 is provided with an organic film layer 25. Taking the product with the organic film layer 25 as an example, the passivation layer includes a first passivation layer 24 and a second passivation layer 27 on both sides of the organic film layer 25, where the first passivation layer 24 is disposed near the source drain metal layer 28, and the second passivation layer 27 is disposed near the electrode layer 26.

In the GOA circuit of the related art, the connection terminals and signal lines of the GOA units are disposed on the gate layer 21, and the connection lines are disposed on the source-drain metal layer 28 and extend from the corresponding signal lines along the second direction to the unit region 12 to be connected with the GOA units; when the signal line connected to the connection line has another signal line on the side close to the cell region 12, the connection line needs to be disposed across the other signal line. For example, in the product shown in fig. 3, the connection line connected to the frame start signal line STV in the related art needs to cross the fourth clock signal line CLK4, the third clock signal line CLK3, the second clock signal line CLK2, the first clock signal line CLK1, the first power signal line VDDO, the second power signal line VDDE, the third power signal line VGL, the fourth power signal line LVGL and the RESET signal line RESET, and then extend to the cell area 12 to be connected to the GOA unit.

In the manufacturing process of the array substrate 1, after the gate layer 21, the gate insulating layer 23 and the source drain metal layer 28 are manufactured, an organic film is manufactured through an organic film process, and a passivation layer is manufactured through a passivation layer process; electrode layer 26 is then fabricated.

However, ESD (electrostatic discharge) easily occurs in the process of manufacturing the organic film layer 25 and the passivation layer, and when the Static electricity is discharged, the signal line is connected to the GOA unit through the connection line, the Static electricity is introduced into the GOA unit through the connection line, which affects the characteristics of the thin film transistor in the GOA unit, and when the Static electricity is serious, the breakdown is invalid, and further the subsequent lighting is abnormal, which affects the quality and performance of the product.

In addition, static electricity can also cause short circuit between the connecting wire and the crossing signal wire, and in practical detection, it is found that ESD is more likely to occur at the bridging position between the frame start signal wire STV and other GOA wires, because the frame start signal wire STV extends longer and charges are likely to accumulate, and compared with other signal wires, the frame start signal wire STV is only connected with one or several GOA units, the number of connecting wires is less, the electrostatic discharge paths are relatively less, and ESD is likely to occur.

In view of this, the embodiment of the present application provides an array substrate 1, in which part or all of the connection lines connecting the frame start signal line STV and the GOA unit are fabricated during the electrode layer 26 process, so that the frame start signal line STV and the GOA unit are in a disconnected state when the array substrate 1 is fabricated with the organic film layer 25 and the passivation layer, and even if ESD occurs, ESD does not enter the GOA unit, so that the characteristics of the thin film transistor in the GOA unit are not affected and breakdown failure is avoided.

The connection line connecting the frame start signal line STV and the GOA unit is defined as a first connection line, and the end of the GOA unit connected to the first connection line is defined as a first connection end 17.

FIG. 5 is a schematic diagram showing the connection between the first combined segment of FIG. 3 and the frame start signal line STV, i.e. the cross-sectional view at the position A-A of FIG. 3; FIG. 6 is a schematic diagram showing the connection of the first, second and third combined sections in FIG. 3; i.e., the cross-sectional view of the position B-B in fig. 3, as shown in fig. 3 to 6, the first connection line includes a first combination section 14, a second combination section 16, and a third combination section 15, the frame start signal line STV is located at the gate layer 21, and the first combination section 14 and the second combination section 16 are located at the source-drain metal layer 28; in other embodiments, the frame start signal line STV may be located in the source drain metal layer 28, and the first combined segment 14 and the second combined segment 16 are located in the gate layer 21, respectively.

The first combined section 14 is connected with the frame start signal line STV through the first via hole 13 and extends to the unit area 12 along the second direction, and the second combined section 16 is connected with the first connection end 17 through the second via hole 18; the third combined segment 15 is located on the electrode layer 26 and is connected to the first combined segment 14 through a third via 20 and to the second combined segment 16 through a fourth via 19. The first via hole 13, the third via hole 20, the fourth via hole 19 and the third combined section 15 are structures fabricated in the same layer as the electrode layer 26.

Since the first via hole 13, the third via hole 20, the fourth via hole 19 and the third combined section 15 are formed in the same layer as the electrode layer 26, the first combined section 14 and the second combined section 16 are in a disconnected state when the organic film layer 25 and the passivation layer are formed on the array substrate 1, that is, the frame start signal line STV is in a disconnected state with the GOA unit, and even if ESD occurs, the ESD does not enter the GOA unit, so that the characteristics of the thin film transistor in the GOA unit are not affected and breakdown failure is avoided.

Fig. 7 is a schematic structural diagram of another first connection line provided in this embodiment of the present application, as shown in fig. 7, in order to avoid shorting the first connection line when bridging other signal lines, in another possible implementation manner, the first connection line is configured by winding, that is, a first combined section 14 in the first connection line is led out from a side of the self-walking line area 11 near the DPO side and extends into the unit area 12 at the DPO side, and the second combined section 16 and the third combined section 15 may be described with reference to the above, which will not be repeated herein.

In addition, in a possible embodiment, the frame start signal line STV may extend beyond one end of the other signal lines on the DPO side, and the first connection line may be led out at the extended portion, thereby facilitating the wiring.

Fig. 8 is a schematic structural diagram of another first connection line provided in this embodiment of the present application, and fig. 9 is a schematic connection diagram of the connection line body 29 and the first connection end 17 in fig. 8, that is, a cross-sectional view of the C-C position in fig. 8, as shown in fig. 8 and 9, the first connection line includes the connection line body 29, the connection line body 29 extends from the corresponding frame start signal line STV along the direction between the unit area 12 and the routing area 11, one end of the connection line body 29 is connected to the frame start signal line STV through the first via hole 13, and the other end of the connection line body 29 is connected to the first connection end 17 through the second via hole 18.

The connection line body 29, the first via hole 13, and the second via hole 18 are formed in the same layer as the electrode layer 26.

Because the connecting wire body 29, the first via hole 13 and the second via hole 18 are formed on the same layer as the electrode layer 26, the frame start signal line STV and the GOA unit are disconnected when the organic film layer 25 and the passivation layer are formed on the array substrate 1, and even if ESD occurs, the ESD does not enter the GOA unit, so that the characteristics of the thin film transistor in the GOA unit are not affected and breakdown failure is avoided.

In addition, the connecting wire body 29 is provided on the electrode layer 26, which increases the distance from the signal line, and even if there is a signal line connected across, the short circuit problem due to static electricity can be avoided by a larger pitch.

Fig. 10 is a schematic connection diagram of the connection wire body 29 and the first connection terminal 17 in the alternative embodiment of fig. 8, please refer to fig. 8 and 10, in which an intermediate pad 30 is disposed between the second via hole 18 and the first connection terminal 17, and the intermediate pad 30 is located on the source-drain metal layer 28 and connected to the first connection terminal 17 through the via hole.

Fig. 11 is a schematic partial view of another GOA circuit provided in this embodiment of the present application, as shown in fig. 11, where the difference between the embodiment and the embodiment in fig. 8 is that the frame start signal line STV is broken, and includes a broken fourth combined segment 31 and a fifth combined segment 32, and an intermediate combined segment 33 connecting the first combined segment 14 and the second combined segment 16 through a via hole, where the intermediate combined segment 33 is made of the same layer as the electrode layer 26, and reference may be made to the connection structure in the above embodiment.

It should be noted that, the breaking position of the signal line may not be fixed, may be located near the DPO side, may be located near the DP side, may be located in a middle or other position, and by breaking the signal line, the length of the signal line is reduced before the organic film layer and the passivation layer are manufactured, so as to reduce the accumulation of charges and reduce the probability of ESD occurrence.

The frame start signal line STV in the above embodiment is described as an example, and it is obviously applicable to any signal line, and a signal line for connecting the GOA unit with the first connection line is defined as the first signal line, and the first signal line is connected with the GOA unit with the first connection line in the above embodiment. The signal line wired in a break-off manner is defined as a second signal line.

In addition, the above-described via structure may employ a dual via structure as illustrated in fig. 5, where possible, to ensure connection reliability.

In the description of the embodiments of the present application, it should be noted that, directions or positional relationships indicated by terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., are based on directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and simplification of the description, and do not indicate or imply that the apparatus or element referred to must have a specific direction, be configured and operated in the specific direction, and therefore should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the embodiments of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in the embodiments of the present application will be understood by those of ordinary skill in the art in a specific context.

In addition, the technical features described above in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.

Thus far, the technical solution of the present application has been described in connection with the preferred embodiments shown in the drawings, but it is easily understood by those skilled in the art that the scope of protection of the present application is not limited to these specific embodiments. Equivalent modifications and substitutions for related technical features may be made by those skilled in the art without departing from the principles of the present application, and such modifications and substitutions will be within the scope of the present application.

Claims

1. The array substrate is characterized by comprising a unit area and a wiring area positioned at one side of the unit area, wherein the unit area is provided with a plurality of cascaded shift register units, the wiring area is provided with a plurality of signal wires for controlling the shift register units, at least one signal wire is a first signal wire, the first signal wire is connected with the shift register units through a first connecting wire, and the shift register units comprise first connecting ends connected with the first connecting wire;

the array substrate comprises a grid layer, a grid insulating layer, a source-drain metal layer, a passivation layer and an electrode layer which are sequentially stacked; the first connecting end is positioned on the grid electrode layer, the first signal line is positioned on the grid electrode layer, and the first connecting line comprises a part which is manufactured in the same layer as the electrode layer;

the array substrate comprises a data binding side and a data binding opposite side which are oppositely arranged, and the wiring area and the unit area are positioned between the data binding side and the data binding opposite side;

the first connecting line comprises a first combined section, a second combined section and a third combined section, and the first combined section and the second combined section are positioned on the source-drain metal layer; the first combined section is led out from one side of the wiring area close to the data binding opposite side and extends into the unit area on the data binding opposite side.

2. The array substrate of claim 1, wherein,

3. The array substrate of claim 1, wherein the second combined segment and the third combined segment are located in the cell region.

4. The array substrate of claim 2, wherein at least one of the first via, the second via, the third via, and the fourth via is a dual via structure.

5. The array substrate of claim 2, wherein the first combined segment extends from the corresponding first signal line in a direction between the cell region and the trace region, and the second combined segment and the third combined segment are located in the cell region.

6. The array substrate according to claim 1, wherein the electrode layer is a transparent metal layer made of indium tin oxide or indium zinc oxide.

7. The array substrate of claim 1, wherein at least one of the signal lines is a second signal line, the second signal line includes a fourth combined segment and a fifth combined segment that are disconnected, and an intermediate combined segment that connects the first combined segment and the second combined segment through a via hole, the intermediate combined segment being a structure fabricated in the same layer as the electrode layer.

8. The array substrate of claim 1, wherein a plurality of the signal lines are arranged side by side in the wiring region in a direction away from the cell region, the wiring region is provided with a frame start signal line away from an outside of the cell region, and the first connection line includes a frame start signal line.

9. The array substrate of claim 1, wherein the array substrate comprises an organic film layer, the passivation layer comprises a first passivation layer and a second passivation layer on two sides of the organic film layer, the first passivation layer is stacked on one side of the source drain metal layer, and the electrode layer is stacked on one side of the second passivation layer.

10. A display panel, comprising the array substrate of any one of claims 1-9, further comprising a color film substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color film substrate.

11. A display device comprising the display panel of claim 10.