CN114973993B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
- Publication number
- CN114973993B CN114973993B CN202210572924.3A CN202210572924A CN114973993B CN 114973993 B CN114973993 B CN 114973993B CN 202210572924 A CN202210572924 A CN 202210572924A CN 114973993 B CN114973993 B CN 114973993B
- Authority
- CN
- China
- Prior art keywords
- transistor
- conductive layer
- gate
- display panel
- shielding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012546 transfer Methods 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 82
- 239000010408 film Substances 0.000 claims description 17
- 238000002161 passivation Methods 0.000 claims description 17
- 239000010409 thin film Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 5
- 239000003990 capacitor Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000009191 jumping Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229920001621 AMOLED Polymers 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
- G09F9/335—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes being organic light emitting diodes [OLED]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/126—Shielding, e.g. light-blocking means over the TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Abstract
The invention provides a display panel and a display device, wherein the display panel comprises a display area and a non-display area, and the display panel comprises: a first conductive layer including a plurality of gate lines arranged in a longitudinal direction and extending in a lateral direction within the display area; a second conductive layer on the first conductive layer, comprising: a plurality of data lines and a plurality of gate wirings arranged on the same layer, wherein the plurality of data lines and the plurality of gate wirings extend in the longitudinal direction and are arranged in the transverse direction in the display area; the grid electrode wires are electrically connected to the grid electrode wires through the transfer holes; the data flip chip film and the grid flip chip film are positioned in the non-display area and are respectively and electrically connected with the data lines and the grid wires; and shielding wires are arranged between at least one data wire and the adjacent grid wires. According to the invention, the shielding wiring is arranged, so that the diagonal Mura on the display panel can be effectively improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a display device.
Background
With the development of the display industry, the requirement on the size of the panel is higher and higher, as shown in fig. 1, for an AMLED or AMOLED panel, the design of three narrow and one wide panels is an effective solution for solving the problem of large-size splicing, in this solution, since the data flip chip film and the gate flip chip film are located on the same side, the gate routing is inevitably changed from longitudinal to transverse in the display area, so that regular transfer holes inevitably exist in the design, and when the display panel is normally lightened, as shown in fig. 2, due to the larger lateral capacitance between the data lines and the gate routing, the jump of the gate routing signal can be coupled with the adjacent data line signals, so that the voltage of the data lines is abnormal, and the diagonal Mura is easy to occur.
For this twill Mura, conventional improvement methods are: (1) The space between the grid electrode wiring and the data line is enlarged, but the scheme is easy to be limited by the arrangement space; (2) The jump amplitude of the grid electrode wiring voltage is reduced, or the coupling of the grid electrode wiring signal to the data line signal through the lateral capacitor is reduced by chamfering the grid electrode wiring signal, wherein the reduction of the grid electrode wiring voltage can cause poor switching state of a TFT device, so that charging is insufficient, the brightness of a panel is reduced, and the chamfering action can bring out higher requirements on the IC function of the panel and has poor effect.
Therefore, the conventional improvement methods of the diagonal Mura have corresponding problems, and the display effect of the display panel cannot be improved on the premise of avoiding other display problems.
Disclosure of Invention
The embodiment of the invention provides a display panel and a display device, which are used for solving the problem that the voltage of a grid electrode wiring is easy to cause abnormal voltage of the data line in the jumping process due to the existence of lateral capacitance between the data line and the grid electrode wiring, so that diagonal Mura occurs.
The invention provides a display panel, which comprises a display area and a non-display area positioned on at least one side of the display area, and comprises:
a first conductive layer including a plurality of gate lines arranged in a longitudinal direction and extending in a lateral direction within the display area;
a second conductive layer on the first conductive layer, comprising: a plurality of data lines and a plurality of gate wirings arranged on the same layer, wherein the plurality of data lines and the plurality of gate wirings extend in the longitudinal direction and are arranged in the transverse direction in the display area; the grid electrode wires are electrically connected to the grid electrode wires through the transfer holes; the data flip chip film and the grid flip chip film are positioned in the non-display area and are respectively and electrically connected with the data lines and the grid wires;
and shielding wires are arranged between at least one data wire and the adjacent grid wires.
In some embodiments of the present invention, a first passivation layer is disposed on the second conductive layer, and the shielding trace is disposed on the first passivation layer.
In some embodiments of the invention, a height of a lower edge of the shielding trace is less than a height of an upper edge of the second conductive layer.
In some embodiments of the invention, a height of a lower edge of the shielding trace is greater than a height of a lower edge of the second conductive layer.
In some embodiments of the invention, the width of the shield trace is less than the spacing between the data line and the gate trace within the second conductive layer.
In some embodiments of the present invention, the semiconductor device further includes a substrate and an interlayer insulating layer, the first conductive layer is located on the substrate, the interlayer insulating layer is located between the first conductive layer and the second conductive layer, the first conductive layer further includes a plurality of gates of a plurality of transistors, the second conductive layer includes a plurality of sources and a plurality of drains of the transistors, the plurality of transistors includes a first transistor, a second transistor and a third transistor, the first transistor and the light emitting element are connected in series between a first power line and a second power line, the second transistor is connected in series between the corresponding data line and the corresponding gate of the first transistor, the gate of the second transistor is electrically connected to the corresponding gate line, the third transistor is connected in series between the source of the first transistor and the reference power line, the gate of the third transistor is used for loading a sensing signal, and the gate of the first transistor is further connected in series between the source of the first transistor and the reference power line.
In some embodiments of the present invention, a second passivation layer is disposed over the shielding trace, and a light shielding layer having a plurality of light shielding portions is disposed over the second passivation layer, and each light emitting element is located between adjacent light shielding portions.
In some embodiments of the invention, the shield trace is located within the display area, the shield trace comprising indium tin oxide material.
In some embodiments of the present invention, the display device further includes a pixel electrode, the pixel electrode is electrically connected to the corresponding data line through a thin film transistor, and the pixel electrode and the shielding trace are disposed on the same layer.
The invention also comprises a display device comprising any one of the display panels.
In the display panel and the display device provided by the embodiment of the invention, the shielding wiring is arranged between the data wire and the adjacent grid wiring, and the arranged shielding wiring can effectively reduce the lateral capacitance of the data wire and the adjacent grid wiring, so that the influence on the voltage of the data wire is weakened in the voltage jumping process of the grid wiring, the diagonal Mura defect of the display panel can be effectively improved, and the display effect of the display panel is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a three-narrow-one-wide design structure of a display panel according to the prior art;
FIG. 2 is a schematic diagram of a circuit structure of a gate trace and a data line coupled in a conventional 3T1C circuit according to the present invention;
fig. 3 is a schematic top view of a display panel according to an embodiment of the present invention;
fig. 4 is a schematic cross-sectional structure of a display panel according to an embodiment of the present invention;
fig. 5 is a schematic cross-sectional view of a display panel according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a 3T1C circuit corresponding to a display panel according to an embodiment of the present invention;
fig. 7 is a schematic diagram of another cross-sectional structure of a display panel according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention. Furthermore, it should be understood that the detailed description is presented herein for purposes of illustration and description only, and is not intended to limit the invention. In the present invention, unless otherwise indicated, terms of orientation such as "upper" and "lower" are used to generally refer to the upper and lower positions of the device in actual use or operation, and specifically the orientation of the drawing figures; while "inner" and "outer" are for the outline of the device.
Specifically, referring to fig. 3 and 4, the display panel includes a display area 10 and a non-display area 20 located on at least one side of the display area 10, and the display panel includes: a first conductive layer 100 including a plurality of gate lines 110, the plurality of gate lines 110 being arranged in a longitudinal direction and extending in a lateral direction within the display area 10; a second conductive layer 200 on the first conductive layer 100, comprising: a plurality of data lines 210 and a plurality of gate wires 220 arranged in the same layer, wherein a plurality of the data lines 210 and a plurality of the gate wires 220 extend in the longitudinal direction and are arranged in the transverse direction in the display area 10; the gate wires 220 are electrically connected to the gate wires 110 through the via holes; and a data flip chip film and a gate flip chip film, which are located in the non-display area 10 and are electrically connected to the plurality of data lines 210 and the plurality of gate wires 220, respectively; wherein, a shielding trace 230 is disposed between at least one of the data lines 210 and the adjacent gate trace 220.
As shown in fig. 3, in the display panel, there are a plurality of data lines 210 and gate wires 220 arranged in a transverse direction, and a plurality of gate lines 110 arranged in a longitudinal direction, in this embodiment, since the data flip chip film (D-COF) and the gate flip chip film (G-COF) are located on the same side of the display panel, the plurality of gate lines 110 arranged in the longitudinal direction and extending in the transverse direction on the display panel cannot be directly connected to the gate flip chip film, and therefore, in this embodiment, the plurality of gate lines 110 are electrically connected to the plurality of gate wires 220 by providing a plurality of through holes, the gate wires 220 and the data lines 210 are located on the same layer, and the plurality of gate wires 220 and the data lines 210 are alternately arranged, so that the plurality of gate wires 220 and the gate flip chip film located on one side of the display panel can be electrically connected.
It can be understood that, in the present embodiment, the numbers of the data flip-chip thin films and the gate flip-chip thin films located on the same side of the display panel are not limited to those shown in fig. 3, and in the actual application process, the numbers of the data flip-chip thin films and the gate flip-chip thin films correspond to the actual requirements.
Further, since the plurality of gate wirings 220 are distributed on the display panel, the gate wirings 220 and the adjacent data lines 210 are located at the same layer, so that a lateral capacitance exists between the data lines 210 and the gate wirings 220, and according to the content described in the background of the invention, the voltage of the data lines 210 is affected by the existence of the lateral capacitance, which further causes the problem that the display panel is prone to have diagonal Mura.
In order to solve the diagonal Mura appearing in the display panel, in this embodiment, the shielding trace 230 is disposed between the data line 210 and the adjacent gate trace 220, and the shielding trace 230 reduces the facing area of the lateral capacitor, so that the voltage interference of the lateral capacitor on the data line 210 can be effectively reduced, thereby weakening the problem of the diagonal Mura appearing in the display panel and improving the display effect of the display panel.
It should be noted that in this embodiment, as shown in fig. 3, two gate flip films are disposed on one side of the display panel, and the gate flip films are disposed on two sides of the data flip film, and as there are two gate flip films, a single gate line 110 is correspondingly connected to two gate wires 220 through a connection hole, it is understood that a single gate line 110 is correspondingly connected to two gate wires 220, and the two gate wires 220 are connected to different positions of the gate line 110, which is beneficial to the transmission of signals of the gate flip films on the gate line 110.
Further, according to the related simulation test, the result shows that the scheme adopted in the embodiment can sharply reduce the lateral capacitance, the variation of the voltage of the gate trace 220 is reduced from 10% to 2.1%, and the coupling of the signal jump of the gate trace 220 to the signal of the adjacent data line 210 is reduced, so that the problem of the diagonal Mura of the display panel is significantly improved.
Optionally, a first passivation layer 300 is disposed on the second conductive layer 200, and the shielding trace 230 is disposed on the first passivation layer 300.
In this embodiment, the first passivation layer 300 is disposed on the second conductive layer 200 to effectively protect the second conductive layer 200, thereby preventing the material of the second conductive layer 200 from being corroded by water or oxygen in the air.
Optionally, the height of the lower edge of the shielding trace 230 is smaller than the height of the upper edge of the second conductive layer 200.
In this embodiment, the shielding trace 230 is configured to reduce the facing area between the data line 210 and the gate trace 220, and by setting the height of the lower edge of the shielding trace 230 to be smaller than the height of the upper edge of the second conductive layer 200, the shielding trace 230 can effectively occupy a part of the spatial position between the data line 210 and the gate trace 220, so that the influence of the lateral capacitance formed by the data line 210 and the gate trace 220 on the voltage of the data line 210 can be reduced.
Optionally, the height of the lower edge of the shielding trace 230 is greater than the height of the lower edge of the second conductive layer 200.
It is understood that, the shielding trace 230 is disposed on the first passivation layer 300, and during the preparation process, since the shielding trace 230 is recessed during the deposition process, the height of the lower edge of the shielding trace 230 is smaller than the horizontal height of the side of the second conductive layer 200 contacting the first passivation layer 300, so that the lateral capacitance formed by the data line 210 and the gate trace 220 can be reduced, and therefore, the height of the lower edge of the shielding trace 230 is generally greater than the height of the lower edge of the second conductive layer 200.
Further, the width of the shielding trace 230 is smaller than the interval between the data line 210 and the gate trace 220 in the second conductive layer 200.
In this embodiment, the shielding trace 230 is configured to reduce the facing area between the data line 210 and the gate trace 220, and if the width of the shielding trace 230 is greater than the distance between the data line 210 and the gate trace 220, a part of the shielding trace 230 is disposed above the data line 210 and the gate trace 220, which is easy to cause other display problems, and will not be described in detail in this application.
Further, as shown in fig. 5, the display panel further includes a substrate 400 and an interlayer insulating layer 500, the first conductive layer 100 is located on the substrate 400, the interlayer insulating layer 500 is located between the first conductive layer 100 and the second conductive layer 200, the first conductive layer 100 further includes a plurality of gates of a plurality of transistors, the second conductive layer 200 includes a plurality of sources and a plurality of drains of a plurality of transistors, as shown in fig. 6, the structure of the 3T1C circuit corresponding to the display panel provided by the embodiment of the present invention is schematically shown in fig. 6, the plurality of transistors includes a first transistor (T1), a second transistor (T2) and a third transistor (T3), the first transistor and the light emitting element are connected in series between a first power line (VDD) and a second power line (VSS), the second transistor is connected in series between the corresponding Data line (Data) and the gate of the first transistor, the second transistor is connected in series between the corresponding gate of the second transistor and the sense line (v) and the second transistor is connected in series between the corresponding gate of the second transistor (v) and the first transistor (v) and the source (v) and the third transistor (v) is connected in series between the first transistor and the source (v 1).
Optionally, as shown in fig. 7, a second passivation layer 600 is disposed above the shielding trace 230, and a light shielding layer 700 having a plurality of light shielding portions 710 is disposed above the second passivation layer 600, and each light emitting element is located between adjacent light shielding portions 710.
In this embodiment, the second passivation layer 600 may protect the shielding trace 230 from being corroded by moisture and oxygen in the air, and the light shielding layer 700 is disposed above the second passivation layer 600, where the light shielding layer 700 includes a plurality of light shielding portions 710, the light emitting elements are located between the adjacent light shielding portions 710, and the light shielding portions 710 may prevent the light emitted by the adjacent light emitting elements from interfering with each other, so as to improve the display effect of the display panel.
Optionally, the shielding trace 230 is located in the display area 10, and the shielding trace 230 includes indium tin oxide material.
It will be appreciated that indium tin oxide material is a common material for the metal layer of the display panel, and is advantageous for the fabrication of the display panel by using indium tin oxide material for the shield trace 230.
Further, the pixel electrode is electrically connected to the corresponding data line 210 through a thin film transistor, and the pixel electrode and the shielding trace 230 are disposed on the same layer.
In this embodiment, considering that, when the LCD is applied to an LCD, the structure of the LCD includes the pixel electrode in addition to the gate electrode connected to the gate line 110 and the drain electrode connected to the data line 210, where the pixel electrode is connected to the source electrode of the thin film transistor, in general, when the pixel electrode layer is prepared, metals at other portions except for the pixel electrode layer need to be etched away, in this embodiment, by disposing the pixel electrode and the shielding trace 230 in the same layer, on one hand, the extra metal material that is etched away is fully utilized and used for preparing the shielding trace 230, so that the influence of the lateral capacitance existing between the data line 210 and the adjacent gate trace 220 on the voltage of the data line 210 can be effectively reduced, thereby improving the diagonal Mura of the display panel, and on the other hand, in the preparation process, the preparation of the pixel electrode and the shielding trace 230 is completed once, saving the additional manufacturing mask, and being beneficial to reducing the preparation cost.
The invention also comprises a display device which comprises any one of the display panels.
It will be appreciated that the display device includes a removable display device (e.g., notebook, cell phone, etc.), a fixed terminal (e.g., desktop, television, etc.), a measuring device (e.g., exercise bracelet, thermometer, etc.), etc.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present invention, the present description should not be construed as limiting the present invention.
Claims (6)
1. A display panel comprising a display area and a non-display area on at least one side of the display area, the display panel comprising:
a first conductive layer including a plurality of gate lines arranged in a longitudinal direction and extending in a lateral direction within the display area;
a second conductive layer on the first conductive layer, comprising: the data lines and the gate wirings are arranged on the same layer, the data lines and the gate wirings extend in the longitudinal direction in the display area and are arranged in the transverse direction, and the gate wirings and the data lines are alternately arranged; the grid electrode wires are electrically connected to the grid electrode wires through the transfer holes; the data flip chip film and the grid flip chip film are positioned in the non-display area and are respectively and electrically connected with the data lines and the grid wires;
wherein, shielding wires are arranged between at least one data wire and the adjacent grid wires; the second conductive layer is provided with a first passivation layer, and the shielding wiring is arranged on the first passivation layer; the height of the lower edge of the shielding wire is smaller than that of the upper edge of the second conductive layer; the height of the lower edge of the shielding wire is larger than that of the lower edge of the second conductive layer; the width of the shielding wire is smaller than the interval between the data wire and the grid wire in the second conductive layer.
2. The display panel of claim 1, further comprising a substrate and an interlayer insulating layer, wherein the first conductive layer is disposed on the substrate, the interlayer insulating layer is disposed between the first conductive layer and the second conductive layer, the first conductive layer further comprises a plurality of gates of a plurality of transistors, the second conductive layer comprises a plurality of sources and a plurality of drains of the plurality of transistors, the plurality of transistors comprises a first transistor, a second transistor and a third transistor, the first transistor and the light emitting element are connected in series between a first power line and a second power line, the second transistor is connected in series between the corresponding data line and the corresponding gate of the first transistor, the gate of the second transistor is electrically connected to the corresponding gate line, the third transistor is connected in series between the source of the first transistor and a reference power line, the gate of the third transistor is used for sensing a signal, and the gate of the third transistor is further connected in series between the first transistor and the sense capacitor.
3. The display panel according to claim 2, wherein a second passivation layer is disposed over the shielding wiring, a light shielding layer having a plurality of light shielding portions is disposed over the second passivation layer, and each of the light emitting elements is located between adjacent light shielding portions.
4. The display panel of claim 1, wherein the shield trace is located within the display area, the shield trace comprising an indium tin oxide material.
5. The display panel according to claim 4, further comprising a pixel electrode electrically connected to the corresponding data line through a thin film transistor, wherein the pixel electrode is disposed on the same layer as the shielding wiring.
6. A display device comprising the display panel according to any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210572924.3A CN114973993B (en) | 2022-05-24 | 2022-05-24 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210572924.3A CN114973993B (en) | 2022-05-24 | 2022-05-24 | Display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114973993A CN114973993A (en) | 2022-08-30 |
| CN114973993B true CN114973993B (en) | 2024-01-02 |
Family
ID=82956560
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210572924.3A Active CN114973993B (en) | 2022-05-24 | 2022-05-24 | Display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114973993B (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1837936A (en) * | 2005-03-22 | 2006-09-27 | 三星电子株式会社 | Liquid crystal display and method |
| CN103872080A (en) * | 2012-12-13 | 2014-06-18 | 乐金显示有限公司 | Organic light-emitting diode display device |
| CN105372894A (en) * | 2015-12-24 | 2016-03-02 | 上海天马微电子有限公司 | Array substrate and liquid crystal display device |
| CN105932029A (en) * | 2016-06-08 | 2016-09-07 | 京东方科技集团股份有限公司 | Array substrate, production method thereof, touch display panel and display device |
| CN109856874A (en) * | 2019-02-28 | 2019-06-07 | 武汉天马微电子有限公司 | Array substrate, display panel and display device |
| CN110114885A (en) * | 2019-03-29 | 2019-08-09 | 京东方科技集团股份有限公司 | Display base plate and preparation method thereof, display panel |
| CN111293140A (en) * | 2018-12-10 | 2020-06-16 | 乐金显示有限公司 | Thin film transistor array substrate and electronic device including the same |
| CN113721394A (en) * | 2020-05-25 | 2021-11-30 | 三星显示有限公司 | Display device |
| CN114171574A (en) * | 2021-12-08 | 2022-03-11 | 武汉华星光电半导体显示技术有限公司 | Display panel |
| CN114495810A (en) * | 2020-11-13 | 2022-05-13 | 乐金显示有限公司 | Display device and driving method thereof |
-
2022
- 2022-05-24 CN CN202210572924.3A patent/CN114973993B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1837936A (en) * | 2005-03-22 | 2006-09-27 | 三星电子株式会社 | Liquid crystal display and method |
| CN103872080A (en) * | 2012-12-13 | 2014-06-18 | 乐金显示有限公司 | Organic light-emitting diode display device |
| CN105372894A (en) * | 2015-12-24 | 2016-03-02 | 上海天马微电子有限公司 | Array substrate and liquid crystal display device |
| CN105932029A (en) * | 2016-06-08 | 2016-09-07 | 京东方科技集团股份有限公司 | Array substrate, production method thereof, touch display panel and display device |
| CN111293140A (en) * | 2018-12-10 | 2020-06-16 | 乐金显示有限公司 | Thin film transistor array substrate and electronic device including the same |
| CN109856874A (en) * | 2019-02-28 | 2019-06-07 | 武汉天马微电子有限公司 | Array substrate, display panel and display device |
| CN110114885A (en) * | 2019-03-29 | 2019-08-09 | 京东方科技集团股份有限公司 | Display base plate and preparation method thereof, display panel |
| CN113721394A (en) * | 2020-05-25 | 2021-11-30 | 三星显示有限公司 | Display device |
| CN114495810A (en) * | 2020-11-13 | 2022-05-13 | 乐金显示有限公司 | Display device and driving method thereof |
| CN114171574A (en) * | 2021-12-08 | 2022-03-11 | 武汉华星光电半导体显示技术有限公司 | Display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114973993A (en) | 2022-08-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11043547B2 (en) | Display panel and display device having same | |
| US20170309644A1 (en) | Display device | |
| US8023059B2 (en) | Array substrate of liquid crystal display, method of repairing same, and liquid crystal display | |
| JP6080316B2 (en) | Display device | |
| CN106950772B (en) | Array substrate, display panel and display device | |
| US9715153B2 (en) | Display device | |
| CN111624827B (en) | Array substrate, display panel and display device | |
| WO2021190163A1 (en) | Display panel and display device | |
| CN109725450B (en) | Display panel and manufacturing method thereof | |
| CN105261655A (en) | Thin film transistor | |
| CN112735262A (en) | Display substrate, manufacturing method thereof and display device | |
| US11842019B2 (en) | Touch substrate and display panel | |
| CN110827732A (en) | Display panel and display device | |
| KR100943284B1 (en) | Pad structure of chip on glass package liquid crystal display device | |
| CN100456090C (en) | Liquid crystal display device and thin film transistor base plate thereof | |
| WO2019041654A1 (en) | Liquid crystal display panel with ultra-narrow lower bezel and manufacturing method therefor | |
| CN114973993B (en) | Display panel and display device | |
| CN110707100A (en) | Display panel | |
| WO2024000793A1 (en) | Display panel and display device | |
| US20220123088A1 (en) | Display panel and manufacturing method thereof | |
| CN114975549A (en) | Display panel and display device | |
| US20200243572A1 (en) | Display device | |
| WO2023124279A1 (en) | Display substrate and display device | |
| CN111338136B (en) | Array substrate and display device | |
| US20240136364A1 (en) | Array substrate and method for manufacturing the same, and display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |