CN111338136B - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN111338136B CN111338136B CN202010174234.3A CN202010174234A CN111338136B CN 111338136 B CN111338136 B CN 111338136B CN 202010174234 A CN202010174234 A CN 202010174234A CN 111338136 B CN111338136 B CN 111338136B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
Abstract
The invention discloses an array substrate and a display device. The array substrate comprises a substrate, a first metal layer, an insulating layer and a second metal layer which are arranged in a stacked mode; the non-display area of the array substrate is provided with at least one fan-shaped circuit area connected with the chip on film, the non-display area is provided with driving chips at least one side close to the fan-shaped circuit area, and a wiring gap area is formed between the driving chips of the fan-shaped circuit area; the wiring gap area comprises a plurality of gap area routing lines formed on the second metal layer and at least one floating metal block area which is formed on the first metal layer and is positioned below at least part of the gap area routing lines. According to the invention, the floating metal block area is used for filling the gaps of the first metal layer below the multiple gap area wires, so that the film layer can be effectively smoothed, the formed multiple gap area wires are ensured not to be broken, and the product percent of pass is improved.
Description
Technical Field
The present disclosure relates to display devices, and particularly to an array substrate and a display device.
Background
Liquid Crystal Displays (LCDs) have the characteristics of light weight, thinness, low power consumption, no radiation pollution and the like, and are therefore widely used in various portable electronic devices such as mobile phones, personal Digital Assistants (PDAs), digital cameras, notebook computers and the like, and even have a tendency to gradually replace the Cathode Ray Tube (CRT) monitors of conventional desktop computers.
The conventional display array substrate binding area comprises a driving chip area, a flexible circuit board area and a liquid crystal box test area; wherein, the drive chip (IC) area is used for binding of IC, and the in-plane circuit and the Thin Film Transistor (TFT) are driven by the IC; the flexible circuit board area is used for binding a flexible circuit board (FPC) and is connected with an electronic equipment mainboard through the FPC; and the liquid crystal Cell Test area is used for testing the display effect of the array substrate by transmitting signals through liquid crystal Cell Test pads (Cell Test pads) after the product is formed into a Cell (Cell).
At present, the development trend of liquid crystal display panels is large size, high resolution 8K, 120Hz, etc., in order to achieve these objectives, the material of the metal wires in the manufacturing process is copper, and the narrow frame is achieved by reducing the line width of the metal wires and increasing the thickness, and simultaneously narrowing the space of the metal wires.
However, the above approaches have some problems associated therewith: when a high-resolution thick copper product is designed, the wiring space is limited, and photoresist is lost in the process due to the increase of the copper thickness. The distance between Chip On Film (COF) is shortened, that is, the area marked by a circle in fig. 1 becomes narrow, and the area is easy to have photoresist missing phenomenon in the manufacturing process of the array substrate so as to cause the disconnection of the wire, specifically, as shown in fig. 2, the formed metal wire has a gap to cause the disconnection of the metal wire, and because the area is small, the risk that the defect is easy to be ignored exists, and the product defect can be caused once the defect occurs.
As shown in fig. 3, which is a schematic diagram of photoresist loss caused by increased copper thickness in the process, the conventional array substrate 9 includes a substrate 91, a first metal layer 92, an insulating layer 93, and a second metal layer 94, which are sequentially stacked from bottom to top; there is the groove gap 921 on the first metal layer 92, when the second metal layer 94 is manufactured at the position corresponding to the groove gap 921, because the metal film has a certain ductility, the second metal layer 94 has a certain recess phenomenon in the groove gap 921, which makes the recess of the groove gap 921 be unable to be evenly coated with the photoresist 95 when the subsequent patterning process is performed on the second metal layer 94 for multiple metal wires, in the subsequent exposure and development, there is a notch 941 on the metal wire formed at the missing position of the coated photoresist 95, which causes the open circuit phenomenon of the metal wire, thereby causing the product to be bad.
Disclosure of Invention
The invention provides an array substrate and a display device, and aims to solve the technical problems that in the prior art, in order to achieve the aim of a high-definition large-size liquid crystal display panel, in an actual manufacturing process, due to the fact that copper thickness is increased, the space of a design surface is narrowed, photoresist is lost when photoresist is coated, and the product is poor.
The invention provides an array substrate, which comprises a substrate, a first metal layer arranged on the substrate, an insulating layer arranged on the first metal layer and a second metal layer arranged on the insulating layer, wherein the first metal layer is arranged on the substrate; the array substrate can be divided into a display area and a non-display area, the non-display area is provided with at least one fan-shaped circuit area connected with a chip on film, the non-display area is provided with a driving chip at least one side close to the fan-shaped circuit area, and a wiring gap area is formed between the driving chips in the fan-shaped circuit area; the wiring gap area comprises a plurality of gap area routing lines formed on the second metal layer and at least one floating metal block area which is formed on the first metal layer and is positioned below at least part of the gap area routing lines.
Further, the wiring of the sector circuit region is formed on the first metal layer.
Further, the floating metal block region includes a plurality of independent metal blocks insulated from the wirings of the sector circuit region.
Further, the metal blocks are of long strip-shaped structures arranged at intervals, so that a fence-shaped pattern is formed in the floating metal block area.
Furthermore, the non-display area is provided with at least two fan-shaped circuit areas connected with the chip on film, a plurality of driving chips are arranged between the two adjacent fan-shaped circuit areas, the floating metal block area is arranged between the driving chip positioned at the leftmost side and the fan-shaped circuit area positioned at the left side of the driving chip, and the floating metal block area is also arranged between the driving chip positioned at the rightmost side and the fan-shaped circuit area positioned at the right side of the driving chip.
Further, the floating metal block area is located below the bent part of the gap area routing.
Further, all the bent parts of the gap area routing are overlapped with the floating metal block area.
Furthermore, the non-display area is provided with at least two fan-shaped circuit areas which are respectively connected with the chip on films, and the gap area wires are metal wires which are connected with two adjacent chip on films.
In order to solve the above problems, the present invention further provides a display panel including the array substrate.
Further, the wiring of the sector circuit region is formed on the first metal layer, the floating metal block region comprises a plurality of independent metal blocks, and the metal blocks are insulated from the wiring of the sector circuit region; the floating metal block area is positioned below the bent part of the gap area routing.
The array substrate and the display device have the advantages that the wiring gap area structure between the fan-shaped circuit area of the array substrate and the driving chip is improved, the at least one floating metal block area is arranged below the wires of the plurality of gap areas of the second metal layer in part of the wiring gap area and used for filling the gaps of the first metal layer below the wires of the plurality of gap areas, the film layer can be effectively smoothed, the influence of gap difference is relieved, photoresist is uniformly coated when the wires of the plurality of gap areas are formed by patterning the second metal layer, the risk of photoresist coating loss is reduced, the condition that the wires of the plurality of gap areas formed by subsequent exposure and development are not broken is guaranteed, and the product qualification rate is improved.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic view of an array substrate in the prior art.
Fig. 2 is a schematic plan view of a metal trace on an array substrate in the prior art.
Fig. 3 is a cross-sectional view of a prior art array substrate with metal traces missing.
Fig. 4 is a cross-sectional view of an array substrate in an embodiment of the present invention.
Fig. 5 is a schematic plan view of an array substrate according to an embodiment of the present invention.
Fig. 6 is a partial enlarged view of a floating metal block region in the array substrate of fig. 5.
The designations in the drawings are as follows:
1. a substrate, 2, a first metal layer, 3, an insulating layer, 4, a second metal layer,
11. a display area, 12, a non-display area, 21, a floating metal block area,
41. a gap area trace 100, an array substrate 121, a flip chip film,
122. a sector circuit area 123, a driving chip 124, a wiring gap area,
210. a metal block.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The directional terms used in the present invention, such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", and the like, are only directions in the drawings, and are used herein for explaining and explaining the present invention, and are not intended to limit the scope of the present invention. When certain components are described as being "on" another component, the component can be directly on the other component; there may also be an intermediate component disposed on the intermediate component and the intermediate component disposed on another component.
In the drawings, elements that are structurally identical are represented by like reference numerals, and elements that are structurally or functionally similar in each instance are represented by like reference numerals. In addition, the size and thickness of each component shown in the drawings are arbitrarily illustrated for convenience of understanding and description, and the present invention is not limited to the size and thickness of each component.
As shown in fig. 4, 5, and 6, an array substrate 100 according to an embodiment of the present invention includes a substrate 1, a first metal layer 2 disposed on the substrate 1, an insulating layer 3 disposed on the first metal layer 2, and a second metal layer 4 disposed on the insulating layer 3; the array substrate 100 may be divided into a display area 11 and a non-display area 12, the non-display area 12 is provided with at least one sector circuit area 122 connected to a Chip On Film (COF) 121, the non-display area 12 is provided with a driving chip 123 on at least one side close to the sector circuit area 122, and a wiring gap area 124 is formed between the driving chips 123 in the sector circuit area 122; the routing gap area 124 includes a plurality of gap area traces 41 formed on the second metal layer 4, and at least one floating metal block area 21 formed on the first metal layer 2 and located under at least a portion of the gap area traces 41.
This embodiment is through improving wiring clearance district 124 structure between fan-shaped circuit region 122 to array substrate 100 and driver chip 123, it sets up at least one floating metal block region 21 to be located many clearance districts of second metal level 4 at some wiring clearance district 124 and walks 41 below, a clearance for filling many clearance districts and walk first metal level 2 below 41, can smooth rete effectively, thereby alleviate the influence of clearance difference, guarantee evenly coating photoresist when patterning second metal level 4 forms many clearance district's line 41, reduce the risk that coating photoresist lacked, thereby guarantee that many clearance districts that follow-up exposure development formed walk 41 and can not appear breaking, the product percent of pass has been promoted.
Generally, the width of the wire gap region 124 on the array substrate 100 of the 4K, 2K resolution, refresh rate 60Hz product is greater than 20000um, and the width of the wire gap region 124 on the array substrate 100 of the 8K resolution, refresh rate 120Hz high-end product is less than 5000um. In this embodiment, the width of the wire gap region 124 is less than or equal to 5000um, and even if the wire gap region 124 is very small, the plurality of gap region traces 41 formed on the second metal layer 4 will not be broken.
In this embodiment, the wires of the sector circuit region 122 are formed on the first metal layer 2. It can be understood that the wiring of the sector circuit region 122 can be formed by patterning the first metal layer 2, which can reduce the process steps and save the production cost.
As shown in fig. 5 and 6, in the present embodiment, the floating metal block region 21 includes a plurality of independent metal blocks 210, and the metal blocks 210 are insulated from the wires of the sector circuit region 122. Preferably, the thickness of the metal block 210 is equal to the thickness of the first metal layer 2, so that the gap below the gap area trace 41 can be better filled, the film layer can be effectively smoothed, the influence of gap difference is reduced, uniform coating of photoresist is ensured when the patterned second metal layer 4 forms a plurality of gap area traces 41, and the risk of coating of photoresist is reduced. In addition, the metal block 210 may be formed by patterning the first metal layer 2, which may reduce the number of process steps and save the production cost.
As shown in fig. 5 and 6, in the present embodiment, the plurality of metal blocks 210 are long and narrow strip structures arranged at intervals, so that a fence-like pattern is formed in the floating metal block area 21. By the arrangement, bending stress caused by overlong metal blocks 210 can be reduced, gaps below the routing wires 41 in the gap area can be effectively filled, and the film layers can be effectively smoothed, so that the influence of gap difference is reduced.
As shown in fig. 5 and 6, in the present embodiment, the non-display area 12 is provided with at least two sector circuit areas 122 connected to a chip on film 121, a plurality of driving chips 123 are disposed between two adjacent sector circuit areas 122, the floating metal block area 21 is disposed between the leftmost driving chip 123 and the sector circuit area 122 located on the left side, and the floating metal block area 21 is also disposed between the rightmost driving chip 123 and the sector circuit area 122 located on the right side.
As shown in fig. 5 and fig. 6, in this embodiment, the floating metal block area 21 is located below the bent portion of the gap area trace 41.
As shown in fig. 5 and fig. 6, in the present embodiment, all the bent portions of the gap area trace 41 are overlapped with the floating metal block area 21.
As shown in fig. 5 and fig. 6, in the present embodiment, the non-display area 12 is provided with at least two sector circuit areas 122 respectively connected to the flip-chip films 121, and the gap area traces 41 are metal traces connecting two adjacent flip-chip films 121.
The invention further provides a display panel including the array substrate 100. Compared with the prior art, the display device provided by the embodiment of the invention has the same beneficial effects as the mask device provided by the technical scheme, and the structure of the wiring gap area 124 between the fan-shaped circuit area 122 of the array substrate 100 and the driving chip 123 is improved, at least one floating metal block area 21 is arranged below the plurality of gap area wires 41 of the second metal layer 4 in part of the wiring gap area 124 and is used for filling the gaps of the first metal layer 2 below the plurality of gap area wires 41, so that the film layer can be effectively smoothed, the influence of gap difference is reduced, photoresist is uniformly coated when the plurality of gap area wires 41 are formed by patterning the second metal layer 4, the risk of coating photoresist loss is reduced, the condition that the plurality of gap area wires 41 formed by subsequent exposure and development are not broken is ensured, and the product qualification rate is improved.
The display device provided in the above embodiment may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigator.
In this embodiment, the wires of the sector circuit region 122 are formed in the first metal layer 2, the floating metal block region 21 includes a plurality of independent metal blocks 210, and the metal blocks 210 are insulated from the wires of the sector circuit region 122; the floating metal block area 21 is located below the bend of the gap area trace 41. The arrangement can reduce the bending stress caused by overlong metal blocks 210, effectively fill the gap below the routing line 41 in the gap area, and effectively smooth the film layer, thereby reducing the influence of gap difference. And the metal block 210 can be formed by patterning the first metal layer 2, so that the process steps can be reduced, and the production cost can be saved.
The array substrate and the display device have the advantages that the wiring gap area structure between the fan-shaped circuit area of the array substrate and the driving chip is improved, the at least one floating metal block area is arranged below the wires of the plurality of gap areas of the second metal layer in part of the wiring gap area and used for filling the gaps of the first metal layer below the wires of the plurality of gap areas, the film layer can be effectively smoothed, the influence of gap difference is relieved, photoresist is uniformly coated when the wires of the plurality of gap areas are formed by patterning the second metal layer, the risk of photoresist coating loss is reduced, the condition that the wires of the plurality of gap areas formed by subsequent exposure and development are not broken is guaranteed, and the product qualification rate is improved.
Claims (8)
1. An array substrate, comprising:
a substrate;
a first metal layer disposed on the substrate;
an insulating layer disposed on the first metal layer; and
a second metal layer disposed on the insulating layer;
the array substrate is characterized in that the array substrate can be divided into a display area and a non-display area, the non-display area is provided with at least one fan-shaped circuit area connected with a chip on film, the non-display area is provided with a driving chip at least one side close to the fan-shaped circuit area, and a wiring gap area is formed between the fan-shaped circuit area and the driving chip;
the wiring gap area comprises a plurality of gap area wires formed on the second metal layer and at least one floating metal block area formed on the first metal layer, and the floating metal block area is positioned below the bent part of the gap area wires.
2. The array substrate of claim 1, wherein the wires of the sector circuit region are formed on the first metal layer.
3. The array substrate of claim 1, wherein the floating metal block region comprises a plurality of independent metal blocks, and the metal blocks are insulated from the wiring of the sector circuit region.
4. The array substrate of claim 3, wherein the plurality of metal blocks are in a long and narrow strip structure arranged at intervals, so that a fence-like pattern is formed in the floating metal block region.
5. The array substrate of claim 1, wherein the non-display area is provided with at least two fan-shaped circuit areas connected with a chip on film, a plurality of driving chips are arranged between two adjacent fan-shaped circuit areas, the floating metal block area is arranged between the driving chip positioned at the leftmost side and the fan-shaped circuit area positioned at the left side, and the floating metal block area is also arranged between the driving chip positioned at the rightmost side and the fan-shaped circuit area positioned at the right side.
6. The array substrate of claim 1, wherein the non-display area is provided with at least two fan-shaped circuit areas respectively connected to the flip-chip on films, and the gap area traces are metal traces connecting two adjacent flip-chip on films.
7. A display panel comprising the array substrate according to claim 1.
8. The display panel according to claim 7, wherein the wirings of the sector circuit region are formed in the first metal layer, and the floating metal block region includes a plurality of independent metal blocks insulated from the wirings of the sector circuit region;
the floating metal block area is positioned below the bent part of the gap area routing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010174234.3A CN111338136B (en) | 2020-03-13 | 2020-03-13 | Array substrate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010174234.3A CN111338136B (en) | 2020-03-13 | 2020-03-13 | Array substrate and display device |
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| Publication Number | Publication Date |
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| CN111338136A CN111338136A (en) | 2020-06-26 |
| CN111338136B true CN111338136B (en) | 2023-03-28 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101249246B1 (en) * | 2006-06-27 | 2013-04-01 | 삼성디스플레이 주식회사 | Display substrate and display device having the same |
| CN105097670B (en) * | 2015-07-31 | 2018-03-09 | 京东方科技集团股份有限公司 | A kind of motherboard and preparation method thereof |
| CN107393415B (en) * | 2017-08-08 | 2020-03-31 | 惠科股份有限公司 | Display panel and display device |
| CN208999736U (en) * | 2018-12-04 | 2019-06-18 | 惠科股份有限公司 | Display panel and display device |
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