CN108803172A - A kind of array substrate, display panel and display device - Google Patents
A kind of array substrate, display panel and display device Download PDFInfo
- Publication number
- CN108803172A CN108803172A CN201810698770.6A CN201810698770A CN108803172A CN 108803172 A CN108803172 A CN 108803172A CN 201810698770 A CN201810698770 A CN 201810698770A CN 108803172 A CN108803172 A CN 108803172A
- Authority
- CN
- China
- Prior art keywords
- grid
- display area
- cabling
- drive signal
- array substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13454—Drivers integrated on the active matrix substrate
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- Optics & Photonics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a kind of array substrate, display panel and display device, which includes：Display area and non-display area around the display area, the display area includes that at least one section of evagination abnormity shows boundary, the non-display area includes the sub- non-display area of abnormity, and the evagination abnormity shows boundary between the sub- non-display area of the abnormity and the display area；A plurality of grid line, the sub- non-display area of abnormity includes gate driving circuit, and the gate driving circuit is electrically connected with a plurality of grid line positioned at the display area；Gate drive signal bus, the gate drive signal bus is electrically connected with the gate driving circuit, being arranged gate drive signal bus in such a way that the gate driving circuit is close to the side of the display area, the area that gate drive signal bus occupies non-display area is reduced, to realize the narrow frame design of display panel.
Description
Technical field
The present invention relates to display technology field, espespecially a kind of array substrate, display panel and display device.
Background technology
With the development of display technology, people are higher and higher to the functionality and cosmetic requirements of display panel, to meet
Demand has been to be concerned by more and more people the design of special-shaped display panel.
Abnormity display panel in the prior art is located at aobvious as shown in Figure 1, including display area I and non-display area II
Show at least one section of evagination abnormity between region I and non-display area II show boundary III, close to display area I be provided with by
The gate driving circuit 10 of multiple shift register SR cascades compositions, and be connected with the gate driving circuit 10 and be located at the grid
Gate drive signal bus 20 of the pole driving circuit 10 far from the display area sides I.Wherein, gate drive signal bus 20 includes
A plurality of signal wire, the sum of the area shared by each signal wire account for the half or so of 20 area of gate drive signal bus, and grid
Non- thread-changing area (spacer region between each signal wire) in drive signal bus 20 occupies the area of a large amount of non-display area,
It is unfavorable for the narrow frame design of display panel.
Therefore, how to realize that the narrow frame design of display panel is those skilled in the art's technical problem urgently to be resolved hurrily.
Invention content
A kind of array substrate of offer of the embodiment of the present invention, display panel and display device, it is in the prior art to solve
The problem of area that the area of gate drive signal bus occupies a large amount of non-display areas is unfavorable for display panel narrow frame design.
An embodiment of the present invention provides a kind of array substrate, which includes：
Display area and non-display area around the display area, the display area include that at least one section of evagination is different
Shape shows that boundary, the non-display area include the sub- non-display area of abnormity, and it is described different that the evagination abnormity shows that boundary is located at
Between the sub- non-display area of shape and the display area；
A plurality of grid line, the sub- non-display area of abnormity includes gate driving circuit, the gate driving circuit be located at
The a plurality of grid line electrical connection of the display area；
Gate drive signal bus, the gate drive signal bus is electrically connected with the gate driving circuit, and is located at
Side of the gate driving circuit close to the display area.
In one possible implementation, in above-mentioned display panel provided in an embodiment of the present invention, the grid drives
Dynamic circuit includes multiple shift registers, and each shift register is cascaded by cascading cabling；
The cascade cabling is between the gate drive signal bus and the gate driving circuit.
In one possible implementation, in above-mentioned display panel provided in an embodiment of the present invention, the displacement is posted
Storage includes：
At least two grid line efferent ducts, wherein be arranged in parallel between the grid line efferent duct.
In one possible implementation, in above-mentioned display panel provided in an embodiment of the present invention, further include：Substrate
The full-size of substrate, any lateral boundaries of orthographic projection of the grid line efferent duct on the underlay substrate is less than or equal to 45
Micron.
In one possible implementation, in above-mentioned display panel provided in an embodiment of the present invention, further include：
A plurality of grid is fanned out to cabling, and a plurality of grid is fanned out to cabling and is electrically connected respectively with the gate driving circuit, often
Grid line described in item is fanned out to cabling with a grid and is electrically connected；
The display area includes special-shaped sub-viewing areas and rectangle sub-viewing areas, and the abnormity sub-viewing areas includes
The evagination abnormity shows boundary；
The a plurality of grid line includes the first grid line and the second grid line, and first grid line is located at the sub- viewing area of abnormity
Domain, second grid line are located at the rectangle sub-viewing areas, wherein the load of first grid line is less than second grid line
Load；
It includes that first grid is fanned out to cabling that a plurality of grid, which is fanned out to cabling, and the first grid is fanned out to cabling and the first grid
Line is electrically connected；
The first grid be fanned out to cabling at least with a non-perpendicular intersection of gate drive signal bus.
In one possible implementation, in above-mentioned display panel provided in an embodiment of the present invention, the first grid
Pole be fanned out to cabling at least with a non-perpendicular intersection of gate drive signal bus, and in intersection, the first grid fan
Going out cabling has the first line width, and outside intersection, the first grid, which is fanned out to cabling, has the second line width, wherein described the
One line width is more than second line width.
In one possible implementation, in above-mentioned display panel provided in an embodiment of the present invention, the first grid
Pole be fanned out to cabling at least with a non-perpendicular intersection of gate drive signal bus, and in intersection, the first grid fan
The extending direction for going out cabling is identical as the extending direction of gate drive signal bus.
In one possible implementation, in above-mentioned display panel provided in an embodiment of the present invention, the grid drives
Dynamic signal bus includes：
One or more of clock cable, reference voltage signal line, initial signal line and reseting signal line.
On the other hand, it is based on same inventive concept, the embodiment of the present invention additionally provides a kind of display panel, including the present invention
The above-mentioned array substrate that embodiment provides.
On the other hand, it is based on same inventive concept, the embodiment of the present invention also provides a kind of display device, including the present invention is in fact
The above-mentioned display panel of example offer is provided.
The present invention has the beneficial effect that：
A kind of array substrate, display panel and display device provided in an embodiment of the present invention, the array substrate include：Display
Region and non-display area around the display area, the display area include that at least one section of evagination abnormity shows boundary,
The non-display area includes the sub- non-display area of abnormity, and the evagination abnormity shows that boundary is located at the sub- non-display area of abnormity
Between domain and the display area；A plurality of grid line, the sub- non-display area of abnormity includes gate driving circuit, and the grid drives
Dynamic circuit is electrically connected with a plurality of grid line positioned at the display area；Gate drive signal bus, the gate driving letter
Number bus is electrically connected with the gate driving circuit, is leaned in the gate driving circuit by being arranged gate drive signal bus
The mode of the side of the nearly display area reduces the area that gate drive signal bus occupies non-display area, aobvious to realize
Show the narrow frame design of panel.
Description of the drawings
Fig. 1 is the structural schematic diagram that the evagination abnormity of display panel in the related technology shows the partial enlargement of boundary；
Fig. 2 is a kind of structural schematic diagram of array substrate provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of another array substrate provided in an embodiment of the present invention；
Fig. 4 is the structural representation that a kind of evagination abnormity of array substrate in Fig. 2 or Fig. 3 shows the partial enlargement of boundary
Figure；
Fig. 5 is the structural representation that another evagination abnormity of array substrate in Fig. 2 or Fig. 3 shows the partial enlargement of boundary
Figure；
Fig. 6 is the schematic diagram of shift register in the related technology；
Fig. 7 is the schematic diagram of shift register provided in an embodiment of the present invention；
Fig. 8 is a kind of concrete structure schematic diagram of gate output provided in an embodiment of the present invention；
Fig. 9 is the concrete structure schematic diagram of another gate output provided in an embodiment of the present invention；
Figure 10 is the concrete structure schematic diagram of another gate output provided in an embodiment of the present invention；
Figure 11 is the concrete structure schematic diagram of another gate output provided in an embodiment of the present invention；
Figure 12 is the knot that another evagination abnormity of array substrate shown in Fig. 2 or Fig. 3 shows the partial enlargement of boundary
Structure schematic diagram；
Figure 13 is a kind of structural schematic diagram that grid line is fanned out to cabling in array substrate provided in an embodiment of the present invention；
Figure 14 is the section that transistor provided in an embodiment of the present invention is fanned out to cabling and gate drive signal bus with grid
Structural schematic diagram；
Figure 15 is another structural schematic diagram that grid line is fanned out to cabling in array substrate provided in an embodiment of the present invention；
Figure 16 is another structural schematic diagram that grid line is fanned out to cabling in array substrate provided in an embodiment of the present invention；
Figure 17 is a kind of concrete structure schematic diagram of gate driving circuit in array substrate provided in an embodiment of the present invention；
Figure 18 is a kind of structural schematic diagram of liquid crystal display panel provided in an embodiment of the present invention；
Figure 19 is a kind of structural schematic diagram of electroluminescence display panel provided in an embodiment of the present invention；
Figure 20 is a kind of structural schematic diagram of display device provided in an embodiment of the present invention；
Figure 21 is another structural schematic diagram of display device provided in an embodiment of the present invention.
Specific implementation mode
Display panel in the related technology, it is aobvious that as shown in FIG. 1, FIG. 1 is the evagination abnormity of display panel in the related technology
Show the structural schematic diagram of the partial enlargement of boundary；It will be set as evagination fillet at four angles of display panel, corresponding position
Display area I can have evagination abnormity and show boundary III, in order to realize to the grid line positioned at display area I (in figure not specifically
Show) it is driven, being provided with close to display area I the gate driving circuit formed can be cascaded by multiple shift register SR
10, and be connected with the gate driving circuit 10 and driven positioned at grid of the gate driving circuit 10 far from the display area sides I
Dynamic signal bus 20.Wherein, gate drive signal bus 20 includes a plurality of signal wire, and the sum of the area shared by each signal wire accounts for this
The half or so of 20 area of gate drive signal bus, and in gate drive signal bus 20 non-thread-changing area (each signal wire it
Between spacer region) area that occupies a large amount of non-display area II, be unfavorable for the narrow frame design of display panel.
It is unfavorable for realizing the narrow frame of display panel for there is the display panel that the display of evagination abnormity becomes in the related technology
The technical issues of design, an embodiment of the present invention provides a kind of array substrate, display panel and display devices.In order to make the present invention
Purpose, technical solution and advantage are clearer, below in conjunction with the accompanying drawings, to display panel provided in an embodiment of the present invention and display
The specific implementation mode of device is described in detail.It should be appreciated that preferred embodiment disclosed below be merely to illustrate and
It explains the present invention, is not intended to limit the present invention.And in the absence of conflict, in the embodiment and embodiment in the application
Feature can be combined with each other.
The shapes and sizes of each component do not react actual proportions in attached drawing, and purpose is schematically illustrate the content of present invention.
Specifically, a kind of array substrate provided in an embodiment of the present invention, as shown in Figure 2, Figure 3 and Figure 4, wherein Fig. 2 is this
A kind of structural schematic diagram for array substrate that inventive embodiments provide, Fig. 3 are another array base provided in an embodiment of the present invention
The structural schematic diagram of plate, Fig. 4 are the knot that a kind of evagination abnormity of array substrate in Fig. 2 or Fig. 3 shows the partial enlargement of boundary
Structure schematic diagram；The array substrate includes：
Display area A and non-display area B around display area, display area A include that at least one section of evagination abnormity is aobvious
Show that boundary C, non-display area B include the sub- non-display area of abnormity, evagination abnormity shows that boundary C is located at the sub- non-display area of abnormity
Between the A of display area；
A plurality of grid line, the sub- non-display area of abnormity include gate driving circuit 1, gate driving circuit 1 be located at viewing area
The a plurality of grid line in domain is electrically connected；
Gate drive signal bus 2, gate drive signal bus 2 are electrically connected (not specific in figure with gate driving circuit 1
Connection relation is shown), and positioned at gate driving circuit 1 close to the side of display area A.
A kind of array substrate provided in an embodiment of the present invention includes：Display area and non-display area around display area
Domain, display area include that at least one section of evagination abnormity shows that boundary, non-display area include the sub- non-display area of abnormity, and evagination is different
Shape shows that boundary is located between the sub- non-display area of abnormity and display area；A plurality of grid line, the sub- non-display area of abnormity includes grid
Pole driving circuit, gate driving circuit are electrically connected with a plurality of grid line positioned at display area；Gate drive signal bus, grid drive
Dynamic signal bus is electrically connected with gate driving circuit, by the way that the setting of gate drive signal bus is close aobvious in gate driving circuit
Show the mode of the side in region, the area that gate drive signal bus occupies non-display area is reduced, to realize display panel
Narrow frame design.
Wherein, special-shaped sub-viewing areas accounts for the area ratio of array substrate relative to shown in Fig. 3 in array substrate shown in Fig. 2
Array substrate in special-shaped sub-viewing areas account for the area of array substrate than small, array substrate shown in Fig. 2 can be applied to hand
In machine, array substrate shown in Fig. 3 can be applied in electronic watch, and the area of special-shaped sub-viewing areas can be according to application
The difference of scene is adjusted correspondingly, and is not specifically limited herein.
Specifically, it is X with the overall width of gate drive signal bus, gate drive signal bus includes a plurality of signal wire,
It is tight in gate drive signal bus when the gate drive signal bus is located at gate driving circuit far from display area side
The arc radius of a piece signal wire of adjacent display area is Y, when to be located at gate driving circuit close for the gate drive signal bus
When the side of display area, the arc radius of the signal wire close to display area in gate drive signal bus is that Z is
Example illustrates, illustratively, by taking evagination abnormity shows that the radian of boundary C is 90 ° as an example, then：
When gate drive signal bus is located at gate driving circuit far from display area side, gate drive signal bus
The area for occupying non-display area is S1, wherein
When gate drive signal bus is located at gate driving circuit close to display area side, gate drive signal bus
The area for occupying non-display area is S2, wherein
Gate drive signal bus accounts for when gate drive signal bus is located at gate driving circuit close to display area side
Grid drives when the area of non-display area is located at gate driving circuit far from display area side less than gate drive signal bus
Dynamic signal bus accounts for the area of non-display area, and difference in areas is Δ S, wherein
Wherein, when X=316 μm, Y=7400 μm, Z=7060 μm, S=168680 μm of Δ2, S1=3749674 μm2, this
Gate drive signal bus is arranged in gate driving circuit close to display area in the array substrate that inventive embodiments provide
Relative to the side far from display area in gate driving circuit is arranged in gate drive signal bus in the related technology when side
When area reduce 4.5%, be conducive to display panel realize narrow frame design.
In addition to this, the non-display area outer edge of display panel is additionally provided with sealant, close to be carried out to display panel
Envelope, is arranged the side in gate driving circuit close to display area by gate drive signal bus, reduces gate drive signal
Bus occupies the area of non-display area, is advantageously used for the light penetration of solidification sealant, is preferably carried out to sealant
Solidification.
Optionally, in above-mentioned array substrate provided in an embodiment of the present invention, as shown in figure 5, Fig. 5 is battle array in Fig. 2 or Fig. 3
Another evagination abnormity of row substrate shows the structural schematic diagram of the partial enlargement of boundary；Gate driving circuit 1 includes multiple
Shift register SR, each shift register SR are cascaded by cascading cabling 3；
Cabling 3 is cascaded between gate drive signal bus 2 and gate driving circuit 1.
Specifically, in above-mentioned array substrate provided in an embodiment of the present invention, by each shift LD of gate driving circuit
The cascade cabling of device is arranged can make all signal wires (including grade between gate drive signal bus and gate driving circuit
Connection cabling and gate drive signal bus) it is respectively positioned on side of the gate driving circuit close to display area, it compares and letter will be cascaded
Number line is arranged can reduce the area that cascade cabling occupies non-display area in side of the gate driving circuit far from display area.
Optionally, in above-mentioned array substrate provided in an embodiment of the present invention, as shown in fig. 7, Fig. 7 is the embodiment of the present invention
The schematic diagram of the shift register of offer；The shift register includes：
At least two grid line efferent ducts (M4-1 and M4-2), wherein parallel connection is set between grid line efferent duct (M4-1 and M4-2)
It sets.
Specifically, as shown in fig. 6, Fig. 6 is the schematic diagram of shift register in the related technology, including a grid line output
Pipe M4 is connected with signal output end OUT, and grid line drive signal is provided for corresponding grid line；And provided in an embodiment of the present invention
In above-mentioned array substrate, as shown in fig. 7, Fig. 7 be shift register provided in an embodiment of the present invention schematic diagram, including two simultaneously
The sum of channel width-over-length ratio of the gate output M4-1 and M4-2 of connection, wherein M4-1 and M4-2 and the gate output M4 in Fig. 6
Channel width-over-length ratio it is close.Since the size of gate output in a shift register is than the size of other transistors
Greatly, to ensure stable output, but the area shared by the metal wire in large-sized gate output is also bigger, is unfavorable for
In the transmission for carrying out the sealant solidification time, the solidification effect of sealant is influenced, to solve the above-mentioned problems, the present invention uses two
The grid line efferent duct (M4-1 and M4-2) of the small size of a parallel connection replaces a large-sized grid line efferent duct M4, simultaneously due to two
The gap that can have metal wire between the grid line efferent duct (M4-1 and M4-2) of the small size of connection, is conducive to the transmission of light, certainly,
A large-sized grid line efferent duct, grid line output can also be replaced with the grid line efferent duct of three or more small sizes in parallel
The particular number of pipe is selected according to particular condition in use, is not specifically limited herein, wherein region where sealant with
Region where grid line efferent duct (such as M4-1 and M4-2) is mutually overlapping.
Fig. 6 in shift register shown in Fig. 7 in addition to the structure all same of the different outer other parts of gate output terminal, tool
Body, Fig. 6 and shift register shown in Fig. 7 further include：
The grid of input pipe M0, input pipe M0 are connected with signal output end INPUT, the first pole and first of input pipe M0
Reference voltage signal end VREF1 is connected, and the second pole of input pipe M0 is connected with pull-up node P；
The first transistor M1, the grid of the first transistor M1 are connected with the first reset signal end RESET1, first crystal
The first pole of pipe M1 is connected with the second reference voltage signal end VREF2, the second pole and the pull-up node P phases of the first transistor M1
Even；
The grid of second transistor M2, second transistor M2 are connected with pull-down node Q, the first pole of second transistor M2
It is connected with third reference voltage signal end VREF3, the second pole of second transistor M2 is connected with pull-up node P；
The grid of third transistor M3, third transistor M3 are connected with pull-up node P, the first pole of third transistor M3
It is connected with third reference voltage signal end VREF3, the second pole of third transistor M3 is connected with pull-down node Q；
The grid of 5th transistor M5, the 5th transistor M5 are connected with pull-down node Q, the first pole of the 5th transistor M5
It is connected with third reference voltage signal end VREF3, the second pole of the 5th transistor M5 is connected with signal output end OUT；
6th transistor M6, the grid of the 6th transistor M6 are connected with the first clock signal terminal CK, the 6th transistor M6
The first pole be connected with third reference voltage signal end VREF3, the second pole and the signal output end OUT phases of the 6th transistor M6
Even；
7th transistor M7, the grid of the 7th transistor M7 are connected with the second reset signal end RESET2, the 7th crystal
The first pole of pipe M7 is connected with third reference voltage signal end VREF3, the second pole and the pull-up node P phases of the 7th transistor M7
Even；
8th transistor M8, the grid of the 8th transistor M8 are connected with the second reset signal end RESET2, the 8th crystal
The first pole of pipe M8 is connected with third reference voltage signal end VREF3, the second pole and the signal output end OUT of the 8th transistor M8
It is connected；
The first pole of first capacitance C1, first capacitance C1 are connected with second clock signal end CKB, and the of the first capacitance C1
Two poles are connected with pull-down node Q；
The first pole of second capacitance C2, second capacitance C2 are connected with pull-up node P, the second pole and the letter of the second capacitance C2
Number output end OUT is connected.
It should be noted that other structures and connection relation of the shift register in addition to gate output are not limited to
Fig. 6 and structure shown in Fig. 7, above-described embodiment are also applied for the structure of other any shift registers, and shift register removes grid
Other concrete structures other than the efferent duct of pole are selected according to actual use situation, are not specifically limited herein.
It is worth noting that, the grid line efferent duct can be located at close to the side of gate drive signal bus, it can also position
In the side far from gate drive signal bus, specific location is selected according to actual use situation, is not made herein specific
It limits.
Optionally, in above-mentioned array substrate provided in an embodiment of the present invention, as shown in Figs. 8 to 11, wherein Fig. 8 is
A kind of concrete structure schematic diagram of gate output provided in an embodiment of the present invention, Fig. 9 are provided in an embodiment of the present invention another
The concrete structure schematic diagram of kind gate output, Figure 10 are the specific knot of another gate output provided in an embodiment of the present invention
Structure schematic diagram, Figure 11 are the concrete structure schematic diagram of another gate output provided in an embodiment of the present invention；The array substrate
Further include：The full-size of underlay substrate, any lateral boundaries of orthographic projection of the grid line efferent duct on underlay substrate is less than or waits
In 45 microns.
Specifically, in above-mentioned array substrate provided in an embodiment of the present invention, as shown in Figs. 8 to 11, grid line efferent duct
Including grid G, source S, drain D and active layer B, still, there are many concrete structures of grid line efferent duct, as shown in Figure 8
" I " shape structure, "u"-shaped shown in Fig. 9, " T " shape structure shown in Fig. 10 and " L " shape structure as shown in figure 11；No matter
Grid line efferent duct is the transistor of which kind of shape, and needing orthographic projection of the guarantee grid line efferent duct on underlay substrate, (i.e. grid line is defeated
Outlet pipe is formed by shading graph on underlay substrate, figure shown in Fig. 8-Figure 11) full-size (L1/ of any lateral boundaries
L2) it is less than or equal to 45 microns, so that existing gap can enable light better between two or more grid line efferent ducts
Through preferably to be cured to sealant, wherein the quantity of the grid line efferent duct of setting is more, each grid line efferent duct it
Between existing gap it is more, be more conducive to the solidification of sealant, but it is more to be arranged grid line efferent duct, the wiring of shift register
It is more complicated, therefore the quantity of grid line efferent duct wants moderate, it is selected during actual use according to considering, herein
It is not especially limited.
Optionally, in above-mentioned array substrate provided in an embodiment of the present invention, as shown in Figure 12 and Figure 13, Figure 12 Fig. 2
Or another evagination abnormity of array substrate shown in Fig. 3 shows that the structural schematic diagram of the partial enlargement of boundary, Figure 13 are this
Grid line is fanned out to a kind of structural schematic diagram of cabling in the array substrate that inventive embodiments provide；The array substrate further includes：
A plurality of grid is fanned out to cabling, and a plurality of grid is fanned out to cabling and is electrically connected respectively with gate driving circuit 1, and every grid line is equal
Cabling is fanned out to a grid to be electrically connected；
Display area includes abnormity sub-viewing areas A1 and rectangle sub-viewing areas A2, special-shaped sub-viewing areas A1 include outer
Convex abnormity shows boundary C；
A plurality of grid line includes the first grid line 41 and the second grid line 42, and the first grid line 41 is located at special-shaped sub-viewing areas A1, the
Two grid lines 42 are located at rectangle sub-viewing areas A2, wherein load of the load of the first grid line 41 less than the second grid line 42；
It includes that first grid is fanned out to cabling 51 that a plurality of grid, which is fanned out to cabling, and first grid is fanned out to cabling 51 and the first grid line 41
Electrical connection；
First grid be fanned out to cabling 51 at least with a 2 non-perpendicular intersection of gate drive signal bus.
Specifically, in above-mentioned array substrate provided in an embodiment of the present invention, since evagination abnormity shows the presence on boundary,
Display area includes special-shaped sub-viewing areas and rectangle sub-viewing areas, wherein special-shaped sub-viewing areas grid line extending direction compared with
Rectangle sub-viewing areas is small, and therefore, the number for being located at the pixel of the grid line driving of special-shaped sub-viewing areas is relatively aobvious positioned at rectangle
Show that the number for the pixel that the grid line in region is driven is few, that is, is located at the capacitive load of grid line connection of special-shaped sub-viewing areas compared with position
In rectangle sub-viewing areas grid line connect capacitive load it is small, can cause to show in this way it is uneven, to alleviate this problem, need
The capacitive load of grid line positioned at special-shaped sub-viewing areas is compensated, wherein positioned at display area grid line be located at it is non-
The grid line of display area is fanned out to cabling and is connected, thus can by increase the first grid that is connect with the first grid line be fanned out to cabling and
The overlapping area of gate drive signal bus compensates the capacitive load of the first grid line, i.e., by making first grid be fanned out to cabling extremely
It is few it is non-perpendicular with a gate drive signal bus intersect to compensate the capacitive load of the first grid line, shown with guarantee uniform
Property.
It should be noted that first grid is fanned out to the inclined degree of cabling, i.e. first grid is fanned out to cabling needs and several
The non-perpendicular intersection of gate drive signal bus depends on the load compensation degree that the first grid line connected to it needs, and needs to compensate
Load it is bigger, inclined degree is bigger, more with the item number of the non-perpendicular intersection of gate drive signal bus；It needs to compensate negative
Carry smaller, inclined degree is smaller, fewer with the item number of the non-perpendicular intersection of gate drive signal bus.
Specifically, in above-mentioned array substrate provided in an embodiment of the present invention, as shown in figure 14, Figure 14 is that the present invention is implemented
The transistor that example provides is fanned out to the cross-sectional view of cabling and gate drive signal bus with grid；First grid is fanned out to away
Line 51 and second grid are fanned out to cabling 52 and are arranged with 2 different layer of grid line drive signal bus, wherein first grid is fanned out to 51 He of cabling
Second grid, which is fanned out to cabling 52, to be arranged with the source S and drain D same layer of the transistor in shift register, gate driving letter
Number bus 2 can be arranged with the grid G same layer of the transistor in shift register, wherein in the transistor of shift register
Source S and drain D are connected with active layer B.
Optionally, in above-mentioned array substrate provided in an embodiment of the present invention, as shown in Figure 15 and Figure 16, Figure 15 is this hair
Grid line is fanned out to another structural schematic diagram of cabling in the array substrate that bright embodiment provides, and Figure 16 provides for the embodiment of the present invention
Array substrate in grid line be fanned out to another structural schematic diagram of cabling；First grid is fanned out to cabling 51 and is at least driven with a grid
The 2 non-perpendicular intersection of dynamic signal bus, and in intersection, first grid, which is fanned out to cabling 51, has the first line width a, and in intersection
Outside, first grid, which is fanned out to cabling 51, has the second line width b, wherein the first line width a is more than the second line width b.
Specifically, in above-mentioned array substrate provided in an embodiment of the present invention, when being fanned out to cabling and grid by first grid
When the mode of the non-perpendicular intersection of pole drive signal bus can not compensate the capacitive load of the first grid line well, increasing can be passed through
Big first grid is fanned out to the mode that cabling is fanned out to the width of cabling with the non-perpendicular intersection first grid of gate drive signal bus
Increase the capacitive load of the first grid line, i.e., is fanned out to the right opposite of cabling and gate drive signal bus by increasing first grid
It accumulates to be compensated to the capacitive load of the first grid line.
Optionally, in above-mentioned array substrate provided in an embodiment of the present invention, as shown in Figure 15 and Figure 16, first grid fan
Go out cabling 51 at least with a 2 non-perpendicular intersection of gate drive signal bus, and in intersection, first grid is fanned out to cabling 51
Extending direction is identical as the extending direction of gate drive signal bus 2.
Specifically, it in above-mentioned array substrate provided in an embodiment of the present invention, is fanned out to cabling in first grid and is driven with grid
The dynamic non-perpendicular intersection of signal bus so that first grid is fanned out to the extension of the extending direction and gate drive signal bus of cabling
Direction is identical, and aforesaid way is compared with first grid is fanned out to the mode that cabling is directly inclined cross gate drive signal bus, the first grid
Pole be fanned out to cabling extending direction increased first grid identical as the extending direction of gate drive signal bus be fanned out to cabling with
The facing area of gate drive signal bus is big, can preferably be compensated the capacitive load of the first grid line.
Specifically, in above-mentioned array substrate provided in an embodiment of the present invention, as shown in Figure 15 and Figure 16, first grid fan
Go out cabling 51 and 2 non-perpendicular intersection of gate drive signal bus, the shape that first grid is fanned out to cabling 51 can be such as Figure 15
Shown in rectangle or diamond shape as described in Figure 16, can also be other any shapes certainly, selected according to particular condition in use
It selects, is not specifically limited herein.
Optionally, in above-mentioned array substrate provided in an embodiment of the present invention, gate drive signal bus includes：
One or more of clock cable, reference voltage signal line, initial signal line and reseting signal line.
Specifically, in above-mentioned array substrate provided in an embodiment of the present invention, as shown in figure 17, Figure 17 is by multiple cascades
Shift register composition gate driving circuit structural schematic diagram, including cascade multiple shift registers：SR(1),SR
(2) ... SR (n) ... SR (N-1), SR (N) (N number of shift register altogether, 1≤n≤N)；Wherein, first order shift register SR is removed
(1) except, remaining signal output end output per level-one shift register SR (n) respectively post by upper level displacement adjacent thereto
The reset signal end reset of storage SR (n-1) is connected；In addition to afterbody shift register SR (N), remaining is shifted per level-one
The signal output end output of register SR (n) distinguishes the input signal of next stage shift register SR (n+1) adjacent thereto
Input is held to be connected.The input signal end input of first order shift register SR (1) is connected with frame start signal end STV, finally
The reset signal end reset of level-one shift register SR (N) is connected with frame end signal end Res.
The gate drive signal bus being connect with gate driving circuit it can be seen from Figure 17 includes clock cable
CLK and CLKB, reference voltage signal line V1-V3, initial signal line STV, reseting signal line Res can also include other certainly
Signal wire, such as touch-control control signal wire SW, wherein the first clock cable CK and the first clock in shift registers at different levels
Signal end clk is connected, second clock signal wire CKB is connected with the second clock signal end clkb in shift registers at different levels, the
One reference signal line V1 is connected with the first reference voltage signal end Vref1 in shift registers at different levels, the second reference signal line
V2 is connected with the second reference voltage signal end Vref2 in shift registers at different levels, third reference signal line V3 and displacements at different levels
Third reference voltage signal end Vref3 in register is connected, is in touch-control control signal wire SW and shift registers at different levels tactile
Signal end SW is controlled to be connected.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of display panel, as shown in Figure 18 and Figure 19,
In, Figure 18 is a kind of structural schematic diagram of liquid crystal display panel provided in an embodiment of the present invention, and Figure 19 carries for the embodiment of the present invention
A kind of structural schematic diagram of the electroluminescence display panel supplied；The display panel includes provided in an embodiment of the present invention any of the above-described
Array substrate.
Above-mentioned display panel can be liquid crystal display panel as shown in figure 18, including provided in an embodiment of the present invention above-mentioned
Any array substrate SUB1, opposite substrate SUB2, positioned at pixel electrodes of the array substrate SUB1 towards the sides opposite substrate SUB2
Layer 61 and the liquid crystal layer 62 being configured between array substrate SUB1 and opposite substrate SUB2.Certain above-mentioned display panel may be used also
To be organic light emitting display panel as shown in figure 19, including any of the above-described array substrate SUB1 provided in an embodiment of the present invention,
Opposite substrate SUB2 and the anode layer 71 being arranged in order towards the sides opposite substrate SUB2 positioned at array substrate SUB1 shine
Layer 72 and cathode layer 73.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of display device, as shown in Figure 20 and Figure 21, figure
20 for display device provided in an embodiment of the present invention be mobile phone when structural schematic diagram, Figure 21 be it is provided in an embodiment of the present invention
Structural schematic diagram when display device is electronic watch；The display device includes above-mentioned display surface provided in an embodiment of the present invention
Plate.The display device can be：Mobile phone, tablet computer, television set, display, laptop, Digital Frame, navigator, electricity
Any product or component with display function such as sub- wrist-watch.The implementation of the display device may refer to the reality of above-mentioned display panel
Example is applied, overlaps will not be repeated.
A kind of array substrate, display panel and display device provided in an embodiment of the present invention, the array substrate include：Display
Region and non-display area around the display area, the display area include that at least one section of evagination abnormity shows boundary,
The non-display area includes the sub- non-display area of abnormity, and the evagination abnormity shows that boundary is located at the sub- non-display area of abnormity
Between domain and the display area；A plurality of grid line, the sub- non-display area of abnormity includes gate driving circuit, and the grid drives
Dynamic circuit is electrically connected with a plurality of grid line positioned at the display area；Gate drive signal bus, the gate driving letter
Number bus is electrically connected with the gate driving circuit, is leaned in the gate driving circuit by being arranged gate drive signal bus
The mode of the side of the nearly display area reduces the area that gate drive signal bus occupies non-display area, aobvious to realize
Show the narrow frame design of panel.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of array substrate, which is characterized in that including：
Display area and non-display area around the display area, the display area include that at least one section of evagination abnormity is aobvious
Show that boundary, the non-display area include the sub- non-display area of abnormity, the evagination abnormity shows that boundary is located at abnormity
Between non-display area and the display area；
A plurality of grid line, the sub- non-display area of abnormity includes gate driving circuit, the gate driving circuit with positioned at described
The a plurality of grid line electrical connection of display area；
Gate drive signal bus, the gate drive signal bus are electrically connected with the gate driving circuit, and positioned at described
Side of the gate driving circuit close to the display area.
2. array substrate as described in claim 1, which is characterized in that the gate driving circuit includes multiple shift LDs
Device, each shift register are cascaded by cascading cabling；
The cascade cabling is between the gate drive signal bus and the gate driving circuit.
3. array substrate as claimed in claim 2, which is characterized in that the shift register includes：
At least two grid line efferent ducts, wherein be arranged in parallel between the grid line efferent duct.
4. array substrate as claimed in claim 3, which is characterized in that further include：Underlay substrate, the grid line efferent duct is in institute
The full-size for stating any lateral boundaries of the orthographic projection on underlay substrate is less than or equal to 45 microns.
5. array substrate as described in claim 1, which is characterized in that further include：
A plurality of grid is fanned out to cabling, and a plurality of grid is fanned out to cabling and is electrically connected respectively with the gate driving circuit, every institute
It states grid line and is fanned out to cabling with a grid and be electrically connected；
The display area includes special-shaped sub-viewing areas and rectangle sub-viewing areas, and the abnormity sub-viewing areas includes described
Evagination abnormity shows boundary；
The a plurality of grid line includes the first grid line and the second grid line, and first grid line is located at the special-shaped sub-viewing areas, institute
It states the second grid line and is located at the rectangle sub-viewing areas, wherein the load of first grid line is negative less than second grid line
It carries；
It includes that first grid is fanned out to cabling that a plurality of grid, which is fanned out to cabling, and the first grid is fanned out to cabling and first grid line electricity
Connection；
The first grid be fanned out to cabling at least with a non-perpendicular intersection of gate drive signal bus.
6. array substrate as claimed in claim 5, which is characterized in that the first grid be fanned out to cabling at least with described in one
The non-perpendicular intersection of gate drive signal bus, and in intersection, the first grid, which is fanned out to cabling, has the first line width, and in phase
Outside at friendship, the first grid, which is fanned out to cabling, has the second line width, wherein the First Line is wider than second line width.
7. array substrate as claimed in claim 6, which is characterized in that the first grid be fanned out to cabling at least with described in one
The non-perpendicular intersection of gate drive signal bus, and in intersection, the first grid is fanned out to the extending direction of cabling and the grid
The extending direction of pole drive signal bus is identical.
8. array substrate as described in claim 1, which is characterized in that the gate drive signal bus includes：
One or more of clock cable, reference voltage signal line, initial signal line and reseting signal line.
9. a kind of display panel, which is characterized in that including such as claim 1-8 any one of them array substrate.
10. a kind of display device, which is characterized in that including display panel as claimed in claim 9.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110589540.8A CN113325640B (en) | 2018-06-29 | 2018-06-29 | Array substrate, display panel and display device |
| CN202110589812.4A CN113325642B (en) | 2018-06-29 | 2018-06-29 | Array substrate, display panel and display device |
| CN202110589811.XA CN113325641B (en) | 2018-06-29 | 2018-06-29 | Array substrate, display panel and display device |
| CN201810698770.6A CN108803172B (en) | 2018-06-29 | 2018-06-29 | Array substrate, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810698770.6A CN108803172B (en) | 2018-06-29 | 2018-06-29 | Array substrate, display panel and display device |
Related Child Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110589540.8A Division CN113325640B (en) | 2018-06-29 | 2018-06-29 | Array substrate, display panel and display device |
| CN202110589811.XA Division CN113325641B (en) | 2018-06-29 | 2018-06-29 | Array substrate, display panel and display device |
| CN202110589812.4A Division CN113325642B (en) | 2018-06-29 | 2018-06-29 | Array substrate, display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108803172A true CN108803172A (en) | 2018-11-13 |
| CN108803172B CN108803172B (en) | 2021-08-10 |
Family
ID=64073728
Family Applications (4)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810698770.6A Active CN108803172B (en) | 2018-06-29 | 2018-06-29 | Array substrate, display panel and display device |
| CN202110589811.XA Active CN113325641B (en) | 2018-06-29 | 2018-06-29 | Array substrate, display panel and display device |
| CN202110589540.8A Active CN113325640B (en) | 2018-06-29 | 2018-06-29 | Array substrate, display panel and display device |
| CN202110589812.4A Active CN113325642B (en) | 2018-06-29 | 2018-06-29 | Array substrate, display panel and display device |
Family Applications After (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110589811.XA Active CN113325641B (en) | 2018-06-29 | 2018-06-29 | Array substrate, display panel and display device |
| CN202110589540.8A Active CN113325640B (en) | 2018-06-29 | 2018-06-29 | Array substrate, display panel and display device |
| CN202110589812.4A Active CN113325642B (en) | 2018-06-29 | 2018-06-29 | Array substrate, display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (4) | CN108803172B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110297342A (en) * | 2019-06-28 | 2019-10-01 | 上海天马有机发光显示技术有限公司 | A kind of display panel and display device |
| CN111583865A (en) * | 2020-06-12 | 2020-08-25 | 京东方科技集团股份有限公司 | Display panel, display device and method for determining channel width-length ratio of switching device |
| WO2020199485A1 (en) * | 2019-04-03 | 2020-10-08 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN112652272A (en) * | 2019-10-11 | 2021-04-13 | 合肥京东方卓印科技有限公司 | Array substrate, manufacturing method thereof and display device |
| CN113419368A (en) * | 2019-03-20 | 2021-09-21 | 厦门天马微电子有限公司 | Array substrate and display device |
| WO2021253345A1 (en) * | 2020-06-18 | 2021-12-23 | 京东方科技集团股份有限公司 | Display panel and manufacturing method therefor, and display device |
| CN113939863A (en) * | 2020-03-31 | 2022-01-14 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115327824A (en) * | 2022-02-22 | 2022-11-11 | 北京京东方光电科技有限公司 | Array substrate, display panel and display device |
Citations (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1003107A1 (en) * | 1993-10-15 | 2000-05-24 | Hitachi, Ltd. | Data processing system and image processing system |
| US6078365A (en) * | 1996-01-25 | 2000-06-20 | Kabushiki Kaisha Toshiba | Active matrix liquid crystal panel having an active layer and an intervening layer formed of a common semiconductor film |
| KR100403940B1 (en) * | 1996-10-31 | 2003-12-18 | 삼성전자주식회사 | Structure of contact of out lead bonding pad and fan-out part of liquid crystal display panel |
| CN1495700A (en) * | 2002-08-07 | 2004-05-12 | ���ǵ�����ʽ���� | Integrated circuit and display containing the same |
| CN1214282C (en) * | 1997-10-31 | 2005-08-10 | 精工爱普生株式会社 | Electro-optical device and electronic apparatus |
| CN101419349A (en) * | 2007-10-23 | 2009-04-29 | 爱普生映像元器件有限公司 | Electro-optical device |
| CN101714326A (en) * | 2008-10-07 | 2010-05-26 | 三星电子株式会社 | Clock-shared differential signaling interface and related method |
| CN201984789U (en) * | 2011-04-19 | 2011-09-21 | 京东方科技集团股份有限公司 | Array substrate row driving circuit, array substrate and liquid crystal display device |
| CN103309107A (en) * | 2013-05-13 | 2013-09-18 | 深圳市华星光电技术有限公司 | Fan-out line structure of array substrate and display panel |
| CN103487962A (en) * | 2007-04-27 | 2014-01-01 | Nlt科技股份有限公司 | Non-rectangular display apparatus |
| CN103913905A (en) * | 2012-12-31 | 2014-07-09 | 三星显示有限公司 | Display device |
| CN204577057U (en) * | 2012-10-05 | 2015-08-19 | 夏普株式会社 | Display device |
| CN105158998A (en) * | 2015-09-14 | 2015-12-16 | 深圳市华星光电技术有限公司 | Liquid crystal display device and display panel thereof |
| US20160094215A1 (en) * | 2014-09-30 | 2016-03-31 | Apple Inc. | Systems and methods for improving energy efficiency of gate driver circuits |
| CN106647071A (en) * | 2017-02-15 | 2017-05-10 | 上海中航光电子有限公司 | Array substrate, display panel and display device |
| CN106711180A (en) * | 2016-12-29 | 2017-05-24 | 上海天马有机发光显示技术有限公司 | Display panel, display device and display panel manufacture method |
| CN106971696A (en) * | 2017-05-03 | 2017-07-21 | 昆山龙腾光电有限公司 | Display device, drive circuit and preparation method thereof |
| CN106991990A (en) * | 2017-05-27 | 2017-07-28 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN107039464A (en) * | 2016-12-23 | 2017-08-11 | 友达光电股份有限公司 | Wire structure and active element array substrate |
| CN206421362U (en) * | 2017-01-10 | 2017-08-18 | 上海中航光电子有限公司 | A kind of touch-control display panel and touch control display apparatus |
| CN107221536A (en) * | 2017-05-25 | 2017-09-29 | 上海天马微电子有限公司 | Array base palte, special-shaped display and display device |
| CN107479766A (en) * | 2017-09-30 | 2017-12-15 | 厦门天马微电子有限公司 | A kind of array base palte, display panel and display device |
| CN107564938A (en) * | 2016-07-01 | 2018-01-09 | 三星显示有限公司 | Display device |
| CN107561806A (en) * | 2017-09-29 | 2018-01-09 | 厦门天马微电子有限公司 | Array base palte and display panel |
| CN107643638A (en) * | 2017-10-18 | 2018-01-30 | 厦门天马微电子有限公司 | Array base palte and display panel |
| CN107703688A (en) * | 2017-09-28 | 2018-02-16 | 武汉天马微电子有限公司 | A kind of array base palte and display device |
| CN107919090A (en) * | 2017-11-30 | 2018-04-17 | 武汉天马微电子有限公司 | Display panel and display device |
| US9960194B1 (en) * | 2016-10-31 | 2018-05-01 | Lg Display Co., Ltd. | Display device |
| CN207458545U (en) * | 2017-11-23 | 2018-06-05 | 昆山龙腾光电有限公司 | A kind of display panel and display device |
| CN108182921A (en) * | 2018-01-03 | 2018-06-19 | 上海中航光电子有限公司 | A kind of array substrate, display panel and display device |
Family Cites Families (32)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08137443A (en) * | 1994-11-09 | 1996-05-31 | Sharp Corp | Image display device |
| JP4228248B2 (en) * | 1998-09-25 | 2009-02-25 | ソニー株式会社 | Method for manufacturing electro-optical device and method for manufacturing drive substrate for electro-optical device |
| JP2004004541A (en) * | 2002-03-22 | 2004-01-08 | Seiko Epson Corp | Electro-optical device, drive circuit for the same, and electronic apparatus |
| JP3960237B2 (en) * | 2003-02-24 | 2007-08-15 | 株式会社デンソー | EL display driving device and printer head of optical printer |
| JP3922227B2 (en) * | 2003-08-28 | 2007-05-30 | セイコーエプソン株式会社 | Display device |
| KR101019416B1 (en) * | 2004-06-29 | 2011-03-07 | 엘지디스플레이 주식회사 | Shift register and flat panel display including the same |
| KR101143004B1 (en) * | 2005-06-13 | 2012-05-11 | 삼성전자주식회사 | Shift register and display device including shifter register |
| CN100565711C (en) * | 2006-02-23 | 2009-12-02 | 三菱电机株式会社 | Shift-register circuit and be provided with the image display device of this circuit |
| JP5128102B2 (en) * | 2006-02-23 | 2013-01-23 | 三菱電機株式会社 | Shift register circuit and image display apparatus including the same |
| JP2007317288A (en) * | 2006-05-25 | 2007-12-06 | Mitsubishi Electric Corp | Shift register circuit and image display equipped therewith |
| JP5210955B2 (en) * | 2009-04-21 | 2013-06-12 | 株式会社ジャパンディスプレイイースト | Gate signal line driving circuit and display device |
| EP2477172A4 (en) * | 2009-09-11 | 2016-03-23 | Sharp Kk | Active matrix substrate and active matrix display device |
| JP5385954B2 (en) * | 2010-10-29 | 2014-01-08 | 三星ディスプレイ株式會社 | Touch screen panel integrated liquid crystal display device and driving method thereof |
| WO2013002229A1 (en) * | 2011-06-30 | 2013-01-03 | シャープ株式会社 | Shift register, scanning signal line drive circuit, display panel, and display device |
| KR101871993B1 (en) * | 2011-08-23 | 2018-06-28 | 삼성디스플레이 주식회사 | Display device |
| US10394094B2 (en) * | 2013-04-25 | 2019-08-27 | Sharp Kabushiki Kaisha | Display device |
| JP6315892B2 (en) * | 2013-05-15 | 2018-04-25 | 三菱電機株式会社 | LCD panel |
| CN103926769B (en) * | 2013-12-26 | 2016-08-24 | 上海天马微电子有限公司 | A kind of array base palte, display floater and display |
| CN104483771B (en) * | 2014-10-28 | 2018-02-06 | 上海中航光电子有限公司 | A kind of tft array substrate, display panel and display device |
| KR102253529B1 (en) * | 2015-01-06 | 2021-05-18 | 삼성디스플레이 주식회사 | Display device and driving method thereof |
| JP2017021087A (en) * | 2015-07-07 | 2017-01-26 | パナソニック液晶ディスプレイ株式会社 | Drive circuit and display |
| CN105139797A (en) * | 2015-10-15 | 2015-12-09 | 京东方科技集团股份有限公司 | Special-shaped display panel and display device |
| JP6539567B2 (en) * | 2015-10-30 | 2019-07-03 | 株式会社ジャパンディスプレイ | Display device |
| CN105334651B (en) * | 2015-12-07 | 2019-03-26 | 深圳市华星光电技术有限公司 | Liquid crystal display, display device and public electrode voltages adjusting method |
| CN105609037B (en) * | 2015-12-31 | 2019-07-09 | 上海中航光电子有限公司 | A kind of array substrate, touch-control display panel and touch control display apparatus |
| JP6689088B2 (en) * | 2016-02-08 | 2020-04-28 | 株式会社ジャパンディスプレイ | Display device |
| JP6806502B2 (en) * | 2016-09-08 | 2021-01-06 | 株式会社ジャパンディスプレイ | Display device |
| CN106547127B (en) * | 2017-01-16 | 2019-10-25 | 上海天马微电子有限公司 | Array substrate, liquid crystal display panel and display device |
| CN107331297B (en) * | 2017-06-28 | 2019-09-24 | 厦门天马微电子有限公司 | A kind of abnormity display panel and display device |
| CN107561799B (en) * | 2017-08-25 | 2021-07-20 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN107644614B (en) * | 2017-10-26 | 2019-12-03 | 上海中航光电子有限公司 | A kind of array substrate, display panel and display device |
| CN107991799B (en) * | 2018-01-02 | 2021-01-29 | 上海中航光电子有限公司 | Display panel and display device |
-
2018
- 2018-06-29 CN CN201810698770.6A patent/CN108803172B/en active Active
- 2018-06-29 CN CN202110589811.XA patent/CN113325641B/en active Active
- 2018-06-29 CN CN202110589540.8A patent/CN113325640B/en active Active
- 2018-06-29 CN CN202110589812.4A patent/CN113325642B/en active Active
Patent Citations (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1003107A1 (en) * | 1993-10-15 | 2000-05-24 | Hitachi, Ltd. | Data processing system and image processing system |
| US6078365A (en) * | 1996-01-25 | 2000-06-20 | Kabushiki Kaisha Toshiba | Active matrix liquid crystal panel having an active layer and an intervening layer formed of a common semiconductor film |
| KR100403940B1 (en) * | 1996-10-31 | 2003-12-18 | 삼성전자주식회사 | Structure of contact of out lead bonding pad and fan-out part of liquid crystal display panel |
| CN1214282C (en) * | 1997-10-31 | 2005-08-10 | 精工爱普生株式会社 | Electro-optical device and electronic apparatus |
| CN1495700A (en) * | 2002-08-07 | 2004-05-12 | ���ǵ�����ʽ���� | Integrated circuit and display containing the same |
| CN103487962A (en) * | 2007-04-27 | 2014-01-01 | Nlt科技股份有限公司 | Non-rectangular display apparatus |
| CN101419349A (en) * | 2007-10-23 | 2009-04-29 | 爱普生映像元器件有限公司 | Electro-optical device |
| CN101714326A (en) * | 2008-10-07 | 2010-05-26 | 三星电子株式会社 | Clock-shared differential signaling interface and related method |
| CN201984789U (en) * | 2011-04-19 | 2011-09-21 | 京东方科技集团股份有限公司 | Array substrate row driving circuit, array substrate and liquid crystal display device |
| CN204577057U (en) * | 2012-10-05 | 2015-08-19 | 夏普株式会社 | Display device |
| CN103913905A (en) * | 2012-12-31 | 2014-07-09 | 三星显示有限公司 | Display device |
| CN103309107A (en) * | 2013-05-13 | 2013-09-18 | 深圳市华星光电技术有限公司 | Fan-out line structure of array substrate and display panel |
| US20160094215A1 (en) * | 2014-09-30 | 2016-03-31 | Apple Inc. | Systems and methods for improving energy efficiency of gate driver circuits |
| CN105158998A (en) * | 2015-09-14 | 2015-12-16 | 深圳市华星光电技术有限公司 | Liquid crystal display device and display panel thereof |
| CN107564938A (en) * | 2016-07-01 | 2018-01-09 | 三星显示有限公司 | Display device |
| US9960194B1 (en) * | 2016-10-31 | 2018-05-01 | Lg Display Co., Ltd. | Display device |
| CN107039464A (en) * | 2016-12-23 | 2017-08-11 | 友达光电股份有限公司 | Wire structure and active element array substrate |
| CN106711180A (en) * | 2016-12-29 | 2017-05-24 | 上海天马有机发光显示技术有限公司 | Display panel, display device and display panel manufacture method |
| CN206421362U (en) * | 2017-01-10 | 2017-08-18 | 上海中航光电子有限公司 | A kind of touch-control display panel and touch control display apparatus |
| CN106647071A (en) * | 2017-02-15 | 2017-05-10 | 上海中航光电子有限公司 | Array substrate, display panel and display device |
| CN106971696A (en) * | 2017-05-03 | 2017-07-21 | 昆山龙腾光电有限公司 | Display device, drive circuit and preparation method thereof |
| CN107221536A (en) * | 2017-05-25 | 2017-09-29 | 上海天马微电子有限公司 | Array base palte, special-shaped display and display device |
| CN106991990A (en) * | 2017-05-27 | 2017-07-28 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN107703688A (en) * | 2017-09-28 | 2018-02-16 | 武汉天马微电子有限公司 | A kind of array base palte and display device |
| CN107561806A (en) * | 2017-09-29 | 2018-01-09 | 厦门天马微电子有限公司 | Array base palte and display panel |
| CN107479766A (en) * | 2017-09-30 | 2017-12-15 | 厦门天马微电子有限公司 | A kind of array base palte, display panel and display device |
| CN107643638A (en) * | 2017-10-18 | 2018-01-30 | 厦门天马微电子有限公司 | Array base palte and display panel |
| CN207458545U (en) * | 2017-11-23 | 2018-06-05 | 昆山龙腾光电有限公司 | A kind of display panel and display device |
| CN107919090A (en) * | 2017-11-30 | 2018-04-17 | 武汉天马微电子有限公司 | Display panel and display device |
| CN108182921A (en) * | 2018-01-03 | 2018-06-19 | 上海中航光电子有限公司 | A kind of array substrate, display panel and display device |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113419368B (en) * | 2019-03-20 | 2022-05-10 | 厦门天马微电子有限公司 | Array substrate and display device |
| CN113419368A (en) * | 2019-03-20 | 2021-09-21 | 厦门天马微电子有限公司 | Array substrate and display device |
| WO2020199485A1 (en) * | 2019-04-03 | 2020-10-08 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN110297342B (en) * | 2019-06-28 | 2022-01-07 | 武汉天马微电子有限公司 | Display panel and display device |
| CN110297342A (en) * | 2019-06-28 | 2019-10-01 | 上海天马有机发光显示技术有限公司 | A kind of display panel and display device |
| CN112652272B (en) * | 2019-10-11 | 2022-04-26 | 合肥京东方卓印科技有限公司 | Array substrate, manufacturing method thereof and display device |
| CN112652272A (en) * | 2019-10-11 | 2021-04-13 | 合肥京东方卓印科技有限公司 | Array substrate, manufacturing method thereof and display device |
| US11508295B2 (en) | 2019-10-11 | 2022-11-22 | Hefei Boe Joint Technology Co., Ltd. | Array substrate and manufacturing method thereof, and display device |
| CN113939863A (en) * | 2020-03-31 | 2022-01-14 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| CN113939863B (en) * | 2020-03-31 | 2024-03-15 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| CN111583865B (en) * | 2020-06-12 | 2021-11-26 | 京东方科技集团股份有限公司 | Display panel, display device and method for determining channel width-length ratio of switching device |
| CN111583865A (en) * | 2020-06-12 | 2020-08-25 | 京东方科技集团股份有限公司 | Display panel, display device and method for determining channel width-length ratio of switching device |
| US11984072B2 (en) | 2020-06-12 | 2024-05-14 | Hefei Boe Joint Technology Co., Ltd. | Display substrate and design method therefor, and display apparatus |
| WO2021253345A1 (en) * | 2020-06-18 | 2021-12-23 | 京东方科技集团股份有限公司 | Display panel and manufacturing method therefor, and display device |
| US11581391B2 (en) | 2020-06-18 | 2023-02-14 | Boe Technology Group Co., Ltd. | Display panel and manufacturing method thereof, and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113325641A (en) | 2021-08-31 |
| CN113325640A (en) | 2021-08-31 |
| CN113325642B (en) | 2022-12-30 |
| CN113325641B (en) | 2022-12-30 |
| CN113325640B (en) | 2022-12-30 |
| CN108803172B (en) | 2021-08-10 |
| CN113325642A (en) | 2021-08-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108803172A (en) | A kind of array substrate, display panel and display device | |
| CN108648683B (en) | Array substrate, touch display panel and touch display device | |
| US20180166467A1 (en) | Array substrate, display panel and display device | |
| US9811169B2 (en) | Flexible array substrate, display panel having the same, keyboard assembly, and electronic device thereof | |
| US10121403B2 (en) | Gate turn on voltage compensating circuit, display panel, driving method and display apparatus | |
| CN110299070A (en) | A kind of display panel and display device | |
| US10488714B2 (en) | Array substrate and display device | |
| CN108376522A (en) | A kind of abnormity panel and display device | |
| CN110599898A (en) | Grid driving array type display panel | |
| CN104464603A (en) | Display panel and display device | |
| CN111540297B (en) | Display panel and display device | |
| KR20210024382A (en) | Emission signal driver and display device including the same | |
| WO2019007087A1 (en) | Array substrate and display apparatus | |
| CN109445210A (en) | A kind of display panel and display device | |
| CN110570825A (en) | Pixel circuit and liquid crystal display panel | |
| US8610854B2 (en) | Liquid crystal display panel and pixel electrode thereof | |
| CN109285494A (en) | Special-shaped array substrate, display panel and display device | |
| US11474386B2 (en) | Thin-film transistor, array substrate, display panel and display device | |
| JP4163611B2 (en) | Liquid crystal display | |
| CN111540298B (en) | Display panel and display device | |
| KR102195175B1 (en) | Display Device | |
| CN112130386B (en) | Array substrate, display panel and display device | |
| CN109637421A (en) | Gate driving circuit and display base plate | |
| CN105931606B (en) | Gate drive configuration and display device | |
| US9995971B2 (en) | Pixel structure and liquid crystal display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |