JP6806502B2 - Display device - Google Patents

Description

The present invention relates to a display device.

The display device generally has a rectangular outer shape. Further, in recent years, with the expansion of the fields of use of display devices, there are display devices having shapes other than rectangles. For example, Japanese Patent Application Laid-Open No. 2009-1223636 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2008-292995 (Patent Document 2) describe display devices.

JP-A-2009-1223636 Japanese Unexamined Patent Publication No. 2008-292995

The display area of the display device includes a plurality of electrodes for driving the electro-optical layer and signal lines for supplying drive signals and scanning signals to the plurality of electrodes. Further, in the peripheral region around the display region, a circuit for supplying signals to the plurality of electrodes is arranged. When the shape of the display area or the shape of the outer edge of the peripheral area is a shape other than a rectangle or a square, a problem arises due to the shape of the display area or the peripheral area. Hereinafter, in the present specification, a shape other than a rectangle or a square may be referred to as a “variant shape”.

For example, when the lengths of a plurality of signal lines are different from each other due to the irregular shape of the display area, the in-plane distribution of the load applied to the signal lines becomes non-uniform. If the in-plane distribution of the load applied to the signal line becomes non-uniform in this way, the image quality deteriorates.

Further, if the lengths of the plurality of signal lines are the same as each other, it is necessary to make the outer shape of the peripheral region rectangular. In this case, the occupied area of the display area in the display device is reduced.

An object of the present invention is to provide a technique for improving the performance of a display device.

A brief outline of the typical inventions disclosed in the present application is as follows.

The display device as one aspect of the present invention includes a display area in which the first pixels are arranged, a peripheral area that is superimposed on the light-shielding layer and is outside the display area, and a plurality of scanning signal lines in the display area. A plurality of video signal lines, a first control circuit that supplies a control signal including a clock signal, a first drive circuit and a second drive circuit that supply a scan signal, and the first control circuit and the first drive circuit. The first clock line to which the first clock signal is supplied, and the second clock line to which the first control circuit and the second drive circuit are connected and the second clock signal is supplied are provided. ing. Further, the plurality of video signal lines extend in the first direction. The light-shielding layer includes a first extending portion and a second extending portion extending along the first direction, and a first bending portion and a first bending portion between the first extending portion and the second extending portion. It has a second bent portion. The first extending portion is connected to the first bent portion, and the second extending portion is connected to the second bent portion. The length of the second extending portion is longer than the length of the first extending portion. Further, in a plan view, the first bent portion overlaps with the first clock line, and the second bent portion is a terminal portion of the first clock line and a terminal portion of the second clock line. between.

It is a top view which shows one structural example of the display device which is one Embodiment. It is an enlarged sectional view of a part of the display area of the display device shown in FIG. It is a top view which shows an example of the arrangement of common electrodes in the display device shown in FIG. It is an equivalent circuit diagram which shows the pixel in the display device shown in FIG. FIG. 5 is an enlarged cross-sectional view of a connection portion between the driver chip and the substrate shown in FIG. It is a circuit block diagram which shows the structural example of the scanning signal line drive circuit shown in FIG. It is a circuit diagram which shows typically the factor of the load applied to each of the plurality of pixels shown in FIG. Of the display devices shown in FIG. 3, it is an enlarged plan view showing the details of the circuit configuration on the upper side. It is an enlarged plan view of the part A of FIG. It is an enlarged plan view of the part B of FIG. Of the display devices shown in FIG. 3, it is an enlarged plan view showing the details of the circuit configuration on the lower side. FIG. 5 is an enlarged plan view showing an example of pixel layout in the area between the display area and the switch circuit shown in FIG. It is an enlarged plan view which shows by extracting a part of the plurality of scanning signal lines and a part of a plurality of video signal lines shown in FIG. It is a top view which shows typically the region where the arrangement density of the dummy pixel is high and the region where it is low in the region between the display device and a switch circuit shown in FIG. It is an enlarged plan view which shows the example of the layout of the wiring which supplies the electric potential to the scanning signal line in the same part as the display device shown in FIG. It is a top view which shows the outline of the circuit layout around the driver chip shown in FIG. 1 schematically. Of the circuit layout shown in FIG. 16, it is an enlarged plan view around the terminal for inspection and the protection circuit. It is an enlarged sectional view around the detection terminal and protection circuit shown in FIG. It is an equivalent circuit diagram which shows the structural example of the protection circuit shown in FIG. 17 and FIG. It is an enlarged plan view which shows the wiring layout around the driver chip shown in FIG. It is a circuit block diagram which shows the modification with respect to the circuit block shown in FIG. It is explanatory drawing which shows the layout example of the scanning signal line drive circuit of the display device which is the examination example for the display device shown in FIG. It is explanatory drawing which shows the layout example of the scanning signal line drive circuit of the display device which is another study example with respect to the display device shown in FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of changes as appropriate even while maintaining the gist of the invention are naturally included in the scope of the present invention. Further, in order to clarify the description, the drawings may schematically represent the width, thickness, shape, etc. of each part as compared with the embodiment, but this is just an example, and the interpretation of the present invention is used. It is not limited.

Further, in this specification and each figure, the same elements as those described above with respect to the above-mentioned figures may be designated by the same reference numerals, and detailed description thereof may be omitted as appropriate.

Further, in the drawings used in the embodiments, hatching attached to distinguish the structures may be omitted depending on the drawings.

Further, the technique described in the following embodiments can be widely applied to a display device provided with a mechanism for supplying signals from the periphery of the display area to a plurality of elements in the display area provided with an electro-optical layer. The electro-optical layer is a layer provided with an element that is driven by an electrical control signal and has a function of forming a display image. Examples of the display device as described above include various display devices such as a liquid crystal display device, an organic EL (Electro-Luminescence) display device, and a plasma display device. In the following embodiments, a liquid crystal display device will be described as a typical example of the display device.

Further, the liquid crystal display device is roughly classified into the following two types according to the application direction of the electric field for changing the orientation of the liquid crystal molecules in the liquid crystal layer which is the display function layer. That is, as the first classification, there is a so-called vertical electric field mode in which an electric field is applied in the thickness direction (or out-of-plane direction) of the display device. The vertical electric field mode includes, for example, a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. Further, as the second classification, there is a so-called lateral electric field mode in which an electric field is applied in the plane direction (or in-plane direction) of the display device. The lateral electric field mode includes, for example, an IPS (In-Plane Switching) mode and an FFS (Fringe Field Switching) mode, which is one of the IPS modes. The technique described below can be applied to both the longitudinal electric field mode and the transverse electric field mode, but in the embodiment described below, the display device of the transverse electric field mode will be described as an example.

<Display device configuration>
FIG. 1 is a plan view showing a configuration example of a display device according to an embodiment. FIG. 2 is an enlarged cross-sectional view of a part of the display area of the display device shown in FIG. FIG. 3 is a plan view showing an example of a circuit layout in the display device shown in FIG. FIG. 4 is an equivalent circuit diagram showing pixels in the display device shown in FIG. FIG. 5 is an enlarged cross-sectional view of the connection portion between the driver chip and the substrate shown in FIG. FIG. 6 is a circuit block diagram showing a configuration example of the scanning signal line drive circuit shown in FIG. In FIG. 1, a portion of the peripheral region SA that overlaps with the light-shielding layer BM is shown with a darker color pattern than the display region DA. Further, in FIG. 2, in order to show an example of the positional relationship between the scanning signal line GL and the video signal line SL in the thickness direction of the substrate SUB1, the scanning signal line GL provided in a cross section different from that of FIG. 2 is also shown. ing. Further, a large number of video signal connection lines SCL are connected to the switch circuit SWS shown in FIG. 3, but in FIG. 3, a dot pattern is attached to a region where a large number of SCLs are arranged.

As shown in FIG. 1, the display device DSP1 has a display panel PNL1 and a driver chip DRC1 mounted on the display panel PNL1. The display panel PNL1 has a display surface DS (see FIG. 2) on which an image is displayed. The driver chip DRC1 is an IC (Integrated Circuit) chip provided with a control circuit for controlling the drive of the display panel PNL1. Further, the display device DSP1 has a wiring board (wiring portion) FWB1 which is a wiring member connected to the display panel PNL1. The wiring board FWB1 is a flexible wiring board in which a plurality of wirings are covered with resin. The wiring board FWB1 is connected to the terminal portion TM1 of the display panel PNL1 as schematically shown with an arrow in FIG. A power supply voltage for driving the display panel PNL1 is supplied to the terminal portion TM1 from a circuit outside the display panel PNL1 in addition to electric signals such as a drive signal and a video signal via the wiring board FWB1.

Further, the display panel PNL1 includes a display area DA in which a plurality of pixels (first pixel) PX (see FIG. 3) are arranged, and a peripheral area SA outside the display area DA. The display area DA is an area in which an image visible from the display surface DS (see FIG. 2) side is displayed based on the signal input to the display device DSP1. The peripheral region SA is arranged so as to continuously surround the display region DA in a plan view. In a plan view, the inner side (end) of the peripheral region SA is in contact with the outer edge of the display region DA. A plurality of pixels PX are arranged in the display area DA. For example, as shown in FIG. 3, in a plan view, two directions intersecting with each other, preferably orthogonal to each other, are the X direction and the Y direction. The plurality of pixels PX are arranged in a matrix in the X direction and the Y direction in the display area DA in a plan view. In the present application, "in plan view" means a case where the display panel PNL1 is viewed from a direction perpendicular to the display surface.

Further, the peripheral area SA is a non-display area in which an image visible from the outside is not displayed, and is arranged so as to surround the periphery of the display area DA. The peripheral region SA is a non-display region, and most of the peripheral region SA overlaps with the light shielding layer BM.

Further, as shown in FIG. 2, the display panel PNL1 includes a substrate SUB1, a substrate SUB2 arranged to face the substrate SUB1, and a liquid crystal layer LQ as an electro-optical layer arranged between the substrate SUB1 and the substrate SUB2. Have. In other words, the display device DSP1 of the present embodiment is a liquid crystal display device including a liquid crystal layer LQ as an electro-optical layer. In the present embodiment, the substrate SUB1 can be paraphrased as an array substrate, and the substrate SUB2 can be paraphrased as an opposed substrate.

As shown in FIG. 1, the driver chip DRC1 and the terminal portion TM1 are located in a region (exposed region) NDA2 of the peripheral region SA of the display panel PNL1 that does not overlap with the light-shielding layer BM. When one side in the Y direction shown in FIG. 1 is the Y1 side and the other side is the Y2 side, the region NDA2 is on the Y1 side of the display region DA in the Y direction. In most of the display panel PNL1 in a plan view, the substrate SUB1 and the substrate SUB2 face each other as shown in FIG. However, the region NDA2 shown in FIG. 1 is exposed from the substrate SUB2 (see FIG. 5). In the example shown in FIG. 5, the light-shielding layer BM is formed on the substrate SUB2, and the region NDA2 (see FIG. 1) does not overlap with the light-shielding layer BM. The light-shielding layer BM is arranged in the display area DA in addition to the peripheral area SA. In a plan view, it is provided so as to surround each of the plurality of pixels PX (see FIG. 3) in the display area DA.

Further, the driver chip DRC1 is mounted on the region DRA in the peripheral region SA (specifically, region NDA2). As shown in FIG. 5, the terminal PD1 and the terminal PD2 are arranged in the region DRA of the substrate SUB1, and the driver chip DRC1 is connected to the terminal PD1 and the terminal PD2. The terminal PD1 is an interface that electrically connects the circuit formed on the driver chip DRC1 and the circuit formed on the display panel PNL1 (see FIG. 1). Further, the terminal PD2 is an interface for electrically connecting the driver chip DRC1 and the wiring board FWB1. The driver chip DRC1 is connected to the terminal PD3 via the terminal PD2 and the wiring FDW. Further, the wiring FW of the wiring board FWB1 is connected to the terminal PD3. Further, as shown in FIG. 1, at least a part (for example, a long side) of the driver chip DRC1 extends along a direction T3 that is inclined with respect to each of the Y direction and the X direction.

As shown in FIG. 4, the display device DSP1 has a video signal line drive circuit SD. The video signal line drive circuit SD is electrically connected to the pixel PX and drives the liquid crystal layer LQ, which is an electro-optical layer, via the video signal line SL. In the example of this embodiment, the video signal line drive circuit SD is formed on the driver chip DRC1. The video signal line drive circuit SD supplies the video signal Spic to the pixel electrode (first electrode) PE included in each of the plurality of pixel PXs via the video signal line SL. Further, as shown in FIG. 6, the driver chip DRC1 has a control circuit (first control circuit) CTC that supplies a control signal to the drive circuit via the control wiring GW. The control circuit CTC is electrically connected to the drive circuit via the terminal PD1 (see FIG. 5).

In the present embodiment, as shown in FIG. 5, an example in which the driver chip DRC1 is mounted on the substrate SUB1 will be described. However, the position of the driver chip DRC1 and the position of the control circuit CTC have various modifications in addition to the region DRA shown in FIG. For example, the driver chip DRC1 may be mounted on the wiring board FWB1. In this case, the wiring board FWB1 is connected to the terminal PD1. As a result, even when the driver chip DRC1 is mounted on the wiring board FWB1, the control circuit CTC of the driver chip DRC1 is electrically connected to the drive circuit via the terminal PD1 of the region DRA.

As shown in FIG. 3, the display device DSP1 has a plurality of video signal lines SL and a plurality of pixels PX. In the display area DA, a plurality of pixels PX are arranged between the substrate SUB1 and the substrate SUB2 (see FIG. 2). The plurality of pixels PX are arranged in a matrix in the X and Y directions, and m × n are arranged (where m and n are positive integers). The plurality of video signal lines SL extend in the Y direction and are arranged at intervals in the X direction. Each of the plurality of pixels PX is partitioned by the video signal line SL in the X direction. Therefore, the number of pixels PX arranged along the X direction corresponds to the number of video signal lines SL. In the example shown in FIG. 1, m video signal lines SL are arranged in the order of video signal lines SL1, SL2, and SLm from X1 which is one side in the X direction toward X2 side which is the other side. ing. Each of the plurality of video signal lines SL is drawn out to the peripheral region SA outside the display region DA. Each of the plurality of video signal line SLs has a driver chip DRC1 via a video signal connection line SCL as a connection wiring (also referred to as a lead-out wiring) for connecting the video signal line SL in the display area DA and the driver chip DRC1 to each other. Is electrically connected to.

The video signal line SL and the video signal connection line SCL are video lines that function as wiring for transmitting a video signal, but the video signal line SL and the video signal connection line SCL can be distinguished as follows. That is, of the video lines that are connected to the driver chip DRC1 and are signal transmission paths that supply video signals to the plurality of pixels PX, the portion (wiring portion) that overlaps the display area DA is called the video signal line SL. Further, of the video lines, a portion (wiring portion) outside the display area DA is referred to as a video signal connection line SCL (or also referred to as a lead-out wiring). Each of the plurality of video signal lines SL extends linearly in the Y direction. On the other hand, since the video signal connection line SCL is a wiring that connects the video signal line SL and the driver chip DRC1, it has a bent portion between the video signal line SL and the driver chip DRC1 as shown in FIG. ..

In the example shown in FIG. 3, there is a switch circuit (selection circuit) SWS between the video signal line SL and the video signal connection line SCL. The switch circuit SWS is, for example, a multiplexer circuit composed of a plurality of transistors, and outputs an input signal by selecting a video signal line SL for each color. The switch circuit SWS operates as a selection switch for selecting the type of video signal, such as a red signal, a green signal, or a blue signal. In other words, the switch circuit SWS is a selection circuit that selects the type of the video signal Spic (see FIG. 4) supplied to the video signal line SL. In this case, the number of video signal connection lines SCL connecting the switch circuit SWS and the driver chip DRC1 is smaller than the number of video signal lines SL. If the number of video signal connection line SCLs can be reduced by providing the switch circuit SWS in this way, the number of video signal connection line SCLs can be reduced between the driver chip DRC1 and the switch circuit SWS. When the switch circuit SWS is provided as shown in FIG. 3, the video signal line SL and the video signal connection line SCL can be distinguished as follows. That is, the portion (wiring portion) that connects the driver chip DRC1 and the switch circuit SWS is called a video signal connection line SCL. Further, the portion of the video line that overlaps the display area DA (wiring portion) to the portion connected to the switch circuit SWS (wiring portion) is referred to as a video signal line SL.

Further, as shown in FIG. 3, the switch circuit SWS is bent according to the shape of the side on the Y1 side of the display area DA. Specifically, since the switch circuit SWS is composed of a plurality of transistors, the array lines of the plurality of transistors constituting the switch circuit SWS are bent along the shape of the Y1 side side of the display area DA. .. As described above, since the switch circuit SWS is bent along the side of the display area DA on the Y1 side, the portion of the peripheral area SA on the Y1 side (the bent portions BEN3, BEN4, and the extension portion shown in FIG. 1) is extended. The area of the part EXT4) can be reduced.

Further, the display device DSP1 has a plurality of scanning signal lines GL and a drive circuit as a scanning signal output circuit that outputs scanning signals Gsi (see FIG. 6) input to the plurality of scanning signal lines GL. The drive circuit is provided on the substrate SUB1 in the peripheral region SA (see FIG. 1). The driver chip DRC1 is connected to the drive circuit via the control wiring GW. The plurality of scanning signal lines GL extend in the X direction and are arranged at intervals in the Y direction. Each of the plurality of pixels PX is partitioned by the scanning signal line GL in the Y direction. Therefore, the number of pixels PX arranged along the Y direction corresponds to the number of scanning signal lines GL. In the example shown in FIG. 3, n scanning signal lines GL are arranged in the order of scanning signal lines GL1, GL2, and GLn from one side in the Y direction toward the other side. Each of the plurality of scanning signal lines GL is drawn out to the peripheral region SA outside the display region DA and connected to the drive circuit. Further, the plurality of scanning signal lines GL intersect with the plurality of video signal lines SL. The scanning signal line GL includes the gate electrode GE of the transistor Tr1 as the pixel switch element PSW shown in FIG.

In FIG. 3, the area where the drive circuit GD is provided is schematically shown by surrounding it with a frame. The drive circuit includes a plurality of types of circuit parts. For example, as shown in FIG. 6, the drive circuit GD is connected to the shift register circuit GSR and the shift register circuit GSR, and is a switch circuit (scanning signal switch) that selects a potential to be supplied to the scanning signal line GL based on a control signal. Circuit) GSW and. Further, the drive circuit GD is connected to the driver chip DRC1 via the control wiring GW. The driver chip DRC1 supplies control signals such as a clock signal GCL and an enable signal ENB to the drive circuit GD via the control wiring GW.

In the example shown in FIG. 6, the clock signal GCL is transmitted to each of the plurality of shift register circuits GSR of the drive circuit GD via the clock line GWC. Further, the enable signal ENB is transmitted to each of the plurality of switch circuits GSW of the drive circuit GD via the enable line GWE. The enable line GWE is a potential supply line that supplies the potential as the scanning signal Gsi to the scanning signal line GL. In the example shown in FIG. 6, the scanning signal Gsi1 is supplied to the scanning signal line GL1, the scanning signal Gsi2 is supplied to the scanning signal line GL2, and the scanning signal Gsin is supplied to the scanning signal line GLn. As schematically shown in FIG. 6, each of the plurality of scanning signals Gsi is a pulse signal whose voltage level changes according to the timing of the clock signal GCL. Further, the start pulse signal GSP is transmitted to the shift register circuit GSR that is driven first among the plurality of shift register circuits GSR via the start pulse line GWS.

Further, in the example shown in FIG. 6, a set of a shift register circuit GSR and a switch circuit GSW constitutes a circuit block GDB1 or GDB2, and each of the circuit blocks GDB1 and GDB2 is connected to a scanning signal line GL. In FIG. 6, for the sake of clarity, one switch circuit GSW is connected to the non-loss shift register circuit GSR, and a scanning signal line GL is connected to each of the switch circuits GSW. However, there are various variations in the circuit configurations of the circuit blocks GDB1 and GDB2. For example, a plurality of switch circuits GSW may be connected to one shift register circuit GSR.

Further, a buffer circuit GBU is connected between the drive circuit GD and the driver chip DRC1. The buffer circuit GBU is a circuit that relays the potential supplied to the scanning signal line GL via the drive circuit GD. When the buffer circuit GBU is interposed in the transmission path of the control signal, the waveform of the gate signal supplied to the drive circuit GD is corrected by the buffer circuit GBU. As shown in FIG. 6, the buffer circuit GBU and the power supply circuit PSC are connected via a power supply wiring PL that supplies a power supply potential to the drive circuit GD. Specifically, the buffer circuit GBU and the power supply circuit PSC are connected via a wiring PLL to which a relatively high potential VDH is supplied and a wiring PLL to which a potential lower than the potential VDH is supplied. In the buffer circuit GBU, the waveform of the control signal such as the enable signal ENB is corrected by using the potential VDH and the potential VDC, and is output to the drive circuit GD. The power supply circuit PSC shown in FIG. 6 is formed on, for example, the wiring board FWB1. Further, as a modification, the power supply circuit PSC may be formed outside the display device DSP1 and may be connected to the buffer circuit GBU via the wiring board FWB1.

Further, in the example shown in FIG. 3, the drive circuit GD is arranged on both the X1 side, which is one side, and the X2 side, which is the other side, in the X direction. Specifically, in the X direction, the drive circuit (scanning signal line drive circuit, first drive circuit) GD1 is on the X1 side, and the drive circuit (scanning signal line drive circuit, second drive circuit) GD2 is on the X2 side. There is. Further, in the X direction, the display area DA is between the drive circuit GD1 and the drive circuit GD2. As shown in FIG. 3, a drive system in which drive circuits GD are connected to both ends of the scan signal line GL is called a double-sided drive system of the scan signal line GL. However, there are various variations in the layout of the drive circuit GD. For example, in the X direction shown in FIG. 3, the drive circuit GD may be arranged on either the X1 side or the X2 side. A drive system in which the drive circuit GD is connected to one end of the scanning signal line GL and the drive circuit GD is not connected to the other end is called a one-sided drive system of the scanning signal line GL. Further, for example, the buffer circuit GBU (see FIG. 6) may not be connected between the driver chip DRC1 and the drive circuit GD.

Further, as shown in FIG. 2, the display device DSP1 has a common electrode (second electrode) CE. Further, as shown in FIG. 4, the display device DSP1 has a common electrode drive circuit (also referred to as a common potential circuit) CD that drives the common electrode CE when the display device DSP1 displays an image. The common electrode CE is electrically connected to the common electrode drive circuit CD via a common wire CML. In the example shown in FIG. 4, the common electrode drive circuit CD is formed on the wiring board FWB1. The common electrode CE is an electrode to which a common potential is supplied to each of a plurality of pixels. Therefore, it is sufficient that one common electrode CE is provided so as to overlap with the display area DA. However, the common electrode CE divided into a plurality of parts may be provided so as to overlap with the display area DA.

The position where the common electrode drive circuit CD is formed has various modifications in addition to the embodiment shown in FIG. For example, the common electrode drive circuit CD may be formed on the driver chip DRC1. Further, for example, a form in which the common electrode drive circuit CD is arranged on the substrate SUB1 shown in FIG. 1 is also included in the embodiment in which the common electrode drive circuit CD is formed in the peripheral region SA. Further, for example, the common electrode drive circuit CD may be formed outside the display device DSP1 and connected to the wiring board FWB1.

As shown in FIG. 4, the pixel PX has a pixel switch element PSW and a pixel electrode PE. Further, in the example of the present embodiment, the plurality of pixels PX share the common electrode CE. The pixel switch element PSW includes, for example, a transistor Tr1 which is a thin film transistor (TFT). The pixel switch element PSW is electrically connected to the scanning signal line GL and the video signal line SL. Specifically, the source electrode SE of the transistor Tr1 which is the pixel switch element PSW is connected to the video signal line SL, and the drain electrode DE is connected to the pixel electrode PE. Further, the gate electrode GE of the transistor Tr1 is included in the scanning signal line GL. The drive circuit (see FIG. 3) controls the supply state of the video signal Spic to the pixel electrode PE by supplying an electric potential (scanning signal Gsi shown in FIG. 6) to the gate electrode GE and operating the pixel switch element PSW on and off. To do. In other words, the transistor Tr1 functions as a pixel switch element PSW that controls the potential supply to the pixel electrode PE.

The pixel switch element PSW may be either a top gate type TFT or a bottom gate type TFT. Further, the material of the semiconductor layer of the pixel switch element PSW is, for example, polycrystalline silicon (polysilicon), but oxide semiconductor or amorphous silicon may also be used.

The pixel electrode PE faces the common electrode CE via the insulating film 14 (see FIG. 2). The common electrode CE, the insulating film 14, and the pixel electrode PE form a holding capacitance CS. During the display operation period in which the display image is formed based on the video signal, an electric field is formed between the pixel electrode PE and the common electrode CE based on the drive signal applied to each electrode. The liquid crystal molecules constituting the liquid crystal layer LQ, which is an electro-optical layer, are driven by an electric field formed between the pixel electrode PE and the common electrode CE. For example, in the display device DSP1 that utilizes the lateral electric field mode as in the present embodiment, as shown in FIG. 2, the substrate SUB1 is provided with the pixel electrode PE and the common electrode CE. The liquid crystal molecules constituting the liquid crystal layer LQ are rotated by using an electric field formed between the pixel electrode PE and the common electrode CE (for example, an electric field in the fringe electric field that is substantially parallel to the main surface of the substrate). ..

That is, during the display operation period, each of the pixel electrode PE and the common electrode CE operates as a drive electrode for driving the liquid crystal layer LQ, which is an electro-optical layer. In other words, each of the plurality of pixel electrode PEs is a first electrode that drives the electro-optical layer. Further, each of the common electrodes CE is a second electrode for driving the electro-optical layer.

As shown in FIG. 2, the substrate SUB1 and the substrate SUB2 are bonded to each other in a state of being separated from each other. The liquid crystal layer LQ is enclosed between the substrate SUB1 and the substrate SUB2. The substrate SUB 1 has an insulating substrate 10 having light transmittance such as a glass substrate or a resin substrate. Further, the substrate SUB1 has a plurality of conductor patterns on the side of the insulating substrate 10 facing the substrate SUB2. The plurality of conductor patterns include a plurality of scanning signal lines GL, a plurality of video signal lines SL, a plurality of common line CMLs, a plurality of common electrodes CE, and a plurality of pixel electrodes PE. In addition, an insulating film is interposed between each of the plurality of conductor patterns. The insulating film arranged between the adjacent conductor patterns and insulating the conductor patterns from each other includes an insulating film 11, an insulating film 12, an insulating film 13, an insulating film 14, and an alignment film AL1. In FIG. 2, one scan signal line GL, one common electrode CE, and one common line CML are shown.

Each of the plurality of conductor patterns described above is formed in a plurality of laminated wiring layers. In the example shown in FIG. 2, the common electrode CE and the pixel electrode PE are formed in different layers, and three wiring layers are provided below the layer in which the common electrode CE is formed. Of the three wiring layers formed on the insulating substrate 10, the scanning signal line GL is mainly formed in the first wiring layer WL1 provided on the most insulating substrate 10 side. The conductor pattern formed on the wiring layer WL1 is made of a metal such as chromium (Cr), titanium (Ti), or molybdenum (Mo) or an alloy thereof.

The insulating film 11 is formed on the wiring layer WL1 and the insulating substrate 10. The insulating film 11 is a transparent insulating film made of, for example, silicon nitride or silicon oxide. In addition to the scanning signal line GL, a gate electrode of a pixel switch element, a semiconductor layer, and the like are formed between the insulating substrate 10 and the insulating film 11.

A second wiring layer WL2 is formed on the insulating film 11. A video signal line SL is mainly formed in the wiring layer WL2. The wiring layer (second wiring layer) WL2 is formed of a material having a resistivity lower than that of the wiring layer (first wiring layer) WL1. The conductor pattern formed on the wiring layer WL2 is composed of, for example, a multi-layered metal film in which aluminum (Al) is sandwiched between molybdenum (Mo), titanium (Ti), and the like. It is preferable that the wiring material of the wiring layer WL2 has a lower specific resistance than the wiring material of the wiring layer WL1. Further, the source electrode and the drain electrode of the pixel switch element are also formed on the insulating film 11. In the example shown in FIG. 2, the video signal line SL extends in the Y direction. The insulating film 12 is formed on each of the video signal line SL and the insulating film 11.

Further, in the example shown in FIG. 2, the wiring layer WL3 of the third layer is formed on the insulating film 12. A common wire CML is mainly formed in the wiring layer WL3. Similar to the wiring layer WL2, the conductor pattern formed on the wiring layer WL3 is composed of, for example, a multi-layered metal film in which aluminum (Al) is sandwiched between molybdenum (Mo), titanium (Ti), and the like. In the example shown in FIG. 2, the common line CML extends in the Y direction. The insulating film 13 is formed on each of the common wire CML and the insulating film 12. In FIG. 2, the insulating film 13 shows an example in which wirings such as a scanning signal line GL, a video signal line SL, and a common line CML are arranged in three wiring layers. However, the number of layers of the wiring layer is not limited to the above, and there are various modifications. For example, the wiring layer WL3 shown in FIG. 2 may not be provided. In this case, the common wire CML may be formed in the same layer as the layer on which the common electrode CE is formed, for example.

Although FIG. 2 shows an enlarged cross section of the display region DA shown in FIG. 1, each of the wiring layers WL1, WL2, and WL3 shown in FIG. 2 is also arranged in the peripheral region SA shown in FIG. The video signal connection line SCL, control wiring GW, and power supply wiring PL shown in FIG. 3 are formed in one or more of the wiring layers WL1, WL2, and WL3. Further, each of the plurality of circuits arranged in the peripheral region SA, such as the switch circuit SWS shown in FIG. 3, is formed in one or a plurality of wiring layers among the wiring layers WL1, WL2, and WL3.

As shown in FIG. 2, the common electrode CE is formed on the insulating film 13. The common electrode CE is preferably a transparent conductive material such as ITO (Indium tin oxide) or IZO (Indium Zinc Oxide). When the display device is a display device such as TN mode or VA mode as the vertical electric field mode, the common electrode CE may be formed on the substrate SUB2. Further, in the cross section shown in FIG. 2, an insulating film 13 is interposed between the common electrode CE and the common wire CML. However, as shown in FIG. 3, a part of the common wire CML and a part of the common electrode CE are electrically connected. Further, the common electrode CE may be made of a metal material as long as it is a reflective display device that utilizes reflection of external light.

The insulating film 14 is formed on the insulating film 13 and the common electrode CE. The pixel electrode PE is formed on the insulating film 14. In a plan view, each pixel electrode PE is located between two video signal lines SL adjacent to each other, and is arranged at a position facing the common electrode CE. The pixel electrode PE is preferably a transparent conductive material or metal material such as ITO or IZO. The alignment film AL1 covers the pixel electrode PE and the insulating film 14.

On the other hand, the substrate SUB2 has an insulating substrate 20 having light transmittance such as a glass substrate or a resin substrate. Further, the substrate SUB2 has a light-shielding layer BM which is a light-shielding film, color filters CFR, CFG and CFB, an overcoat layer OCL, an alignment film AL2, and a conductive film CDF on the side of the insulating substrate 20 facing the substrate SUB1. Has.

The conductive film CDF is arranged on the plane opposite to the plane facing the liquid crystal layer LQ in the plane of the insulating substrate 20. The conductive film CDF is made of a transparent conductive material such as ITO or IZO. The conductive film CDF functions as a shield layer that suppresses the influence of electromagnetic waves from the outside on the liquid crystal layer LQ and the like. Further, when the method for driving the liquid crystal layer LQ is a longitudinal electrolysis mode such as TN mode or VA mode, an electrode is provided on the substrate SUB2, and this electrode also functions as a shield layer, so that the conductive film CDF can be omitted. ..

The display device DSP1 has an optical element OD1 and an optical element OD2. The optical element OD1 is arranged between the insulating substrate 10 and the backlight unit BL. The optical element OD2 is arranged above the insulating substrate 20, that is, on the side opposite to the substrate SUB1 with the insulating substrate 20 interposed therebetween. The optical element OD1 and the optical element OD2 each include at least a polarizing plate, and may include a retardation plate if necessary.

<Display device plan shape and circuit layout>
Next, the relationship between the planar shape of the display device of the present embodiment and the circuit layout will be described. FIG. 7 is a circuit diagram schematically showing the factors of the load applied to each of the plurality of pixels shown in FIG. Further, FIG. 8 is an enlarged plan view showing details of the circuit configuration on the upper side of the display device shown in FIG. 22 and 23 are explanatory views showing a layout example of a scanning signal line drive circuit of the display device, which is an example of examination for the display device shown in FIG.

In addition, in FIG. 7, a sheet-shaped common electrode CE is shown in order to explicitly show that the common electrode CE is arranged across a plurality of pixel PEs. Further, in FIG. 8, for the sake of easy viewing of the circuit layout of the drive circuits GD1 and GD2, the clock line GWC for transmitting the clock signal is typically shown among the plurality of control wiring GWs shown in FIG. For the same reason, FIG. 8 shows the circuit blocks GDB1 and GDB2 included in the drive circuit GD shown in FIG. At least one or more scanning signal lines GL are connected to each of the plurality of circuit blocks GDB1 and GDB2, but in FIG. 8, for the sake of visibility, the scanning signals arranged most on the Y2 side in the Y direction. The line GL1 is indicated by a chain line, and the other scanning signal lines GL are not shown.

As shown in FIG. 1, in the display device DSP1 of the present embodiment, the planar shape of the display area DA and the shape of the peripheral area SA are "variant" respectively. In the example shown in FIG. 1, the display device DSP1 is also used as a rearview mirror for checking the rear of an automobile, and the planar shape of the display area DA and the outer shape of the peripheral area SA are trapezoidal, respectively. Further, in a plan view, the shape of the light-shielding layer BM arranged around the display area DA is as follows. That is, the light-shielding layer BM has an extending portion (first extending portion) EXT1 and an extending portion (second extending portion) EXT2 extending in the Y direction, respectively. Further, the light-shielding layer BM has a bent portion (first bent portion) BEN1 and a bent portion (second bent portion) BEN2 located between the extending portion EXT1 and the extending portion EXT2. Further, the extending portion EXT1 is connected to the bent portion BEN1, and the extending portion EXT2 is connected to the bent portion BEN2. Further, the length of the extending portion EXT2 is longer than the length of the extending portion EXT1. Further, in the example shown in FIG. 1, the light-shielding layer BM has an extending portion (third extending portion) EXT3 between the bent portion BEN1 and the bent portion BEN2, and the extending portion EXT3 is in the Y direction and X. It has a side (inner end side) extending along the direction T1 that is inclined with respect to each of the directions. The direction of inclination with respect to the Y direction is a direction forming an angle other than a right angle and a parallel with respect to the Y direction. Similarly, the direction of inclination with respect to the X direction is a direction forming an angle other than right angle and parallel with respect to the X direction.

The bent portion means a portion where the extending direction changes. As shown in FIG. 1, the bent portion includes not only a curved portion but also a bent portion. Further, when the curve is curved, the amount of change (angle) in the extending direction due to the curved portion / the total length of the curved portion can be defined as the curvature.

Further, in the example shown in FIG. 1, the light-shielding layer BM has a bent portion (third bent portion) BEN3 on the opposite side of the bent portion BEN1 via the extending portion EXT1. Further, the light-shielding layer BM has a bent portion (fourth bent portion) BEN4 on the opposite side of the bent portion BEN2 via the extending portion EXT2. Further, the light-shielding layer BM has an extending portion (fourth extending portion) EXT4 between the bent portion BEN3 and the bent portion BEN4, and the extending portion EXT4 is inclined with respect to each of the Y direction and the X direction. It has a side (inner end side) extending along the direction T2. In the example of this embodiment, since the display area DA is trapezoidal, the directions T1 and T2 are not parallel to each other. Further, in the example shown in FIG. 1, the direction T2 and the direction T3 are parallel to each other. The expression "direction T2 and direction T3 are parallel to each other" can be regarded as substantially parallel, although not strictly parallel due to the influence of processing accuracy, etc., in addition to the case where both are strictly parallel. Including things. In FIG. 1, in order to distinguish from the bent portion BEN1 and the bent portion BEN2 on the Y2 side in the Y direction, the bent portion BEN3 is described as the third bent portion, and the bent portion BEN4 is described as the fourth bent portion. However, as shown in FIG. 11 to be described later, if attention is paid to the portion on the Y1 side, the bent portion BEN3 can be read as the first bent portion, and the bent portion BEN4 can be read as the second bent portion. Similarly, although the extended portion EXT4 is described as the fourth extended portion, it can be read as the third extended portion.

Here, from the viewpoint of improving the quality of the image displayed on the display device DSP1, it is caused by the load value (for example, parasitic capacitance, wiring resistance, etc.) applied to each of the plurality of pixels PX arranged in the display area DA. It is preferable to make the impedance value) uniform in the plane overlapping with the display region DA. If the in-plane distribution of the load value with respect to the pixel PX becomes non-uniform in the display area DA, it causes deterioration of image quality such as display unevenness.

The load factors applied to each of the plurality of pixels PX include the parasitic capacitances C1 to C5 shown in FIG. 7, the wiring resistance of the scanning signal line GL, and the wiring resistance of the video signal line SL. The parasitic capacitance C1 is the parasitic capacitance between the scanning signal line GL and the video signal line SL. The parasitic capacitance C2 is the parasitic capacitance between the source electrode and drain electrode of the transistor Tr1 and the video signal line SL. The parasitic capacitance C3 is the parasitic capacitance between the source electrode and the drain electrode of the transistor Tr1 and the scanning signal line GL. Further, the parasitic capacitance C4 is the parasitic capacitance between the scanning signal line GL and the common electrode CE. The parasitic capacitance C5 is the parasitic capacitance between the video signal line SL and the common electrode CE.

Further, in the present embodiment, a plurality of pixels PX are connected to one scanning signal line GL. Further, a plurality of pixels PX are connected to one video signal line SL. Therefore, as the number of pixel PXs connected to each of the plurality of scanning signal lines GL increases, the value of the load applied to the pixel PX increases. Similarly, as the number of pixel PXs connected to each of the plurality of video signal lines SL increases, the value of the load applied to the pixel PX increases. In other words, the load factor given to the plurality of pixel PXs includes the number of pixel PXs connected to each of the plurality of scanning signal lines GL. Further, the load factor given to the plurality of pixel PXs includes the number of pixel PXs connected to each of the plurality of video signal lines SL.

Further, in the present embodiment, drive circuits are connected to both ends of the scanning signal line GL. In other words, each of the plurality of scanning signal lines GL is driven by a double-sided drive system. In this way, when a plurality of scanning signal lines GL are driven by the two-sided drive method, if a part of the plurality of scanning signal lines GL is driven by the one-side drive method, the plurality of scanning signal lines This causes the in-plane distribution of the load applied to the GL to become uneven. That is, from the viewpoint of improving the image quality, it is preferable that all the scanning signal lines GL are driven by the double-sided drive method.

If the plane shape of the display area DA is square or rectangular, it is easy to make the lengths of the plurality of scanning signal lines GL uniform and the lengths of the plurality of video signal lines SL uniform. Therefore, it is relatively easy to make the value of the load applied to each of the plurality of pixels PX arranged so as to overlap the display area DA substantially constant.

However, in the case of the display device DSP1 having the irregular display area DA as in the present embodiment, the in-plane distribution of the load values applied to each of the plurality of pixels PX tends to be non-uniform. For example, when the drive circuit is not arranged so as to overlap between the bent portion BEN1 and the bent portion BEN2 as in the display device DSPh1 shown in FIG. 22, the one-sided drive method is applied to a part of the display area DA. Will be done. Further, for example, when the extension distance of the drive circuit GD1 and the extension distance of the drive circuit GD2 are equalized as in the display device DSPh2 shown in FIG. 23, the outer shape (planar shape) of the display device DSPh2 becomes rectangular. In this case, the display device DSPh2 is further increased in size.

In the case of the display device DSP1 of the present embodiment, as shown in FIG. 3, the drive circuit GD1 straddles the region overlapping the bent portion BEN1 (see FIG. 1) and extends to the vicinity of the bent portion BEN2 (see FIG. 2). It is extending. In other words, in plan view, the bent portion BEN2 is between the end portion of the drive circuit GD1 and the end portion of the drive circuit GD2. As a result, the drive circuit GD is connected to both ends of the scanning signal line GL1 arranged on the Y2 side most in the Y direction among the plurality of scanning signal lines GL. In other words, each of the plurality of scanning signal lines GL including the scanning signal line GL1 is driven by the two-sided driving method. As a result, it is possible to suppress deterioration in image quality caused by driving a part of the plurality of scanning signal lines GL by the one-side drive method.

As described above, in FIG. 3, the region where the drive circuit GD is provided is schematically shown by surrounding it with a frame, but the drive circuit GD includes a plurality of types of circuits. The above configuration can also be expressed as follows using the clock lines GWC1 and GWC2 shown in FIG. That is, the display device DSP1 connects the control circuit CTC and the drive circuit GD1, and supplies the clock signal (first clock signal) GCL1 (see FIG. 6) to the clock line (first clock line) GWC1 and the control circuit. The CTC and the drive circuit GD1 are connected to each other, and a clock line (second clock line) GWC2 to which a clock signal (second clock signal) GCL2 (see FIG. 6) is supplied is provided. Further, in a plan view, the bent portion BEN1 overlaps with the clock line GWC1, and the bent portion BEN2 is located between the end portion of the clock line GWC1 and the end portion of the clock line GWC2. As shown in FIG. 8, the end portion of the clock line GWC1 is between the bent portion BEN1 and the bent portion BEN2. In the example shown in FIG. 8, the end portion of the clock line GWC2 overlaps with the bent portion BEN2, and the end portion of the clock line GWC1 does not overlap with the bent portion BEN2.

Further, as described above, from the viewpoint of making the in-plane distribution of the load uniform, it is preferable to make the number of pixels PX (see FIG. 7) connected to each of the plurality of scanning signal lines GL uniform. However, as shown in FIG. 3, in the case of the display device DSP1 having the irregular display area DA, the length of the display area DA in the X direction, which is the extending direction of the scanning signal line GL, is not a constant value, so that the scanning signal The number of corresponding pixels PX is different for each line GL. For example, in the example shown in FIG. 8, the length of the portion of the display area DA sandwiched between the extending portion EXT3 and the bending portion BEN2 is the portion sandwiched between the extending portion EXT1 and the extending portion EXT2. Is shorter than the length in the X direction. Therefore, the number of pixels PX arranged in the portion where the length in the X direction is relatively short is small.

Therefore, a dummy pixel (second pixel) PXd (see FIG. 9) is provided in a part of the peripheral region SA (see FIG. 1), and a dummy is provided for the scanning signal line GL in which the number of corresponding pixel PXs is relatively small. It is preferable that the pixels PXd are connected. Thereby, it is possible to reduce the variation in the load due to the number of pixels PX connected to each of the plurality of scanning signal lines GL. The dummy pixel PXd is located in the peripheral region SA (see FIG. 1) and differs from the pixel PX in that it overlaps with the light-shielding layer BM (see FIG. 1), but the other points are the pixel PX in the display region DA. Is similar to. The dummy pixel PXd includes at least the transistor Tr2, and a part of the scanning signal line GL constitutes the gate electrode GE of the transistor Tr2. The transistor Tr2 is a semiconductor element having the same structure as the transistor Tr1 shown in FIG. Further, although the video signal line SL is not shown in FIG. 9, the video signal line SL may be connected to the dummy pixel PXd as shown in FIG. 12 described later. As shown in FIG. 9, for example, a part of the pixel PX (for example, a part of the pixel electrode PE shown in FIG. 2) is superimposed on the light-shielding layer BM, and the other part is not superimposed on the light-shielding layer BM. , The pixel PX is treated as a non-dummy pixel PX. However, when the configuration of the pixel PX in which a part thereof overlaps with the light-shielding layer BM is insufficient as compared with the configuration described with reference to FIG. 4, the pixel PX is treated as a dummy pixel PXd. Further, when the pixel PX does not directly contribute to the formation of the display image, for example, when most of the pixel PX is superimposed on the light-shielding layer BM, the pixel PX is treated as a dummy pixel PXd.

A configuration that uses the dummy pixel PXd to reduce the load variation due to the number of pixels PX connected to each of the plurality of scanning signal lines GL can be expressed as follows. FIG. 9 is an enlarged plan view of part A in FIG. Further, FIG. 10 is an enlarged plan view of a portion B of FIG. The drive circuit GD1 has a circuit block (first A circuit block) GBA1 (see FIG. 10) and a circuit block (first B circuit block) GBB1 (see FIG. 9) connected via a clock line GWC1. The circuit block GBA1 is superimposed on the extending portion EXT1 of the light-shielding layer BM, and the circuit block GBB1 is superimposed on the extending portion EXT3. In this case, the number of pixels PX connected to the scanning signal line GLB connected to the circuit block GBB1 shown in FIG. 9 is the pixel PX corresponding to the scanning signal line GLA connected to the circuit block GBA1 shown in FIG. Less than the number of. On the other hand, the number of dummy pixels PXd connected to the scanning signal line GLB connected to the circuit block GBB1 is larger than the number of dummy pixels PXd connected to the scanning signal line GLA connected to the circuit block GBA1. Therefore, it is possible to reduce the difference in the total number of pixels PX and dummy pixels PXd connected to each of the scanning signal lines GL.

In the example shown in FIG. 10, the dummy pixel PXd (see FIG. 9) is not connected to the scanning signal line GLA. In other words, zero dummy pixels PXd are connected to the scanning signal line GLA. The expression "the number of dummy pixels PXd connected to the scanning signal line GLB is larger than the number of dummy pixels PXd connected to the scanning signal line GLA" is expressed as a dummy pixel in the scanning signal line GLA as shown in FIG. This includes the case where the PXd (see FIG. 9) is not connected. Further, as a modification, a relatively small number of dummy pixels PXd may be connected to the scanning signal line GLA. In the present application, when it is described that "the number of A is larger than the number of B" or "the number of A is smaller than the number of B", the case where one of the numbers is zero is also included as described above.

As described above, on one hypotenuse of the display device DSP1 having a trapezoidal planar shape, that is, the side along the extending portion EXT3 shown in FIG. 8, the drive circuit GD1 can be arranged along the hypotenuse. Thereby, the double-sided drive system of the scanning signal line GL can be applied to the terminal portion of the drive circuit GD1 and the terminal portion of the drive circuit GD2, in other words, the terminal portion of the clock line GWC1 and the terminal portion of the clock line GWC2. On the other hand, a switch circuit SWS is arranged on the other hypotenuse of the display device DSP1 having a trapezoidal planar shape, that is, on the side along the extending portion EXT4 (see FIG. 1), and a plurality of video signal lines SL are displayed in the display area. It extends toward DA. Therefore, it is difficult to arrange the drive circuit GD1 or the drive circuit GD2 along the extending portion EXT4. That is, the drive circuit GD1 and the drive circuit GD2 have different circuit layouts applied to the Y1 side side and the Y2 side side in the Y direction shown in FIG.

FIG. 11 is an enlarged plan view showing details of the circuit configuration on the lower side of the display device shown in FIG. Further, FIG. 12 is an enlarged plan view showing an example of pixel layout in the area between the display area and the switch circuit shown in FIG. As shown in FIG. 11, the display device DSP1 includes a switch circuit (selection circuit) SWS between the display area DA and the driver chip DRC1 in which the control circuit CTC (see FIG. 6) is formed. Further, in a plan view, there is no drive circuit GD1 and drive circuit GD2 between the switch circuit SWS and the display area DA. When the drive circuits GD1 and GD2 are arranged between the switch circuit SWS and the display area DA, it may be necessary to bend a part of the plurality of video signal lines SL depending on the positions of the drive circuits GD1 and GD2. .. The total number of video signal lines SL is larger than the total number of scanning signal lines GL. In this case, when a part of the video signal line SL is bent, the wiring layout around the bent portion becomes complicated. Therefore, it is preferable that each of the plurality of video signal lines SL does not bend and extends linearly. As shown in FIG. 11, in the case of the present embodiment, since the drive circuits GD1 and GD2 are not arranged between the switch circuit SWS and the display area DA, each of the plurality of video signal lines SL is bent in the middle. It has no portion and extends linearly along the Y direction.

However, depending on the number of circuit blocks GDB1 and GDB2 constituting the drive circuits GD1 and GD2, a part of the plurality of circuit blocks GDB1 may be arranged between the switch circuit SWS and the display area DA. Hereinafter, the embodiment will be described.

When the two-sided drive method is applied to each of the plurality of scanning signal lines GL, the number of circuit blocks GDB1 and the number of circuit blocks GDB2 are equal. However, since the extension portion EXT1 and the extension portion EXT2 have different lengths as described above, the arrangement spaces of the circuit blocks GDB1 and GDB2 are different. That is, as described above, the extending portion EXT2 is longer than the extending portion EXT1 in the Y direction. In this case, a wide space for arranging the plurality of circuit blocks GDB2 can be secured in the region overlapping with the extending portion EXT2. Therefore, the plurality of circuit blocks GDB2 are linearly arranged along the Y direction. In other words, the plurality of circuit blocks GDB2 can be easily arranged so as to avoid the space between the switch circuit SWS and the display area DA.

However, in the Y direction, the extending portion EXT1 is shorter than the extending portion EXT2. The area that overlaps with the extending portion EXT1 becomes a space for arranging the plurality of circuit blocks GDB1, but the area is smaller than the area of the area that overlaps with the extending portion EXT2. As a result, the plurality of circuit blocks GDB1 are arranged not only in the region superposed on the extending portion EXT1 but also in the region superimposing on the bent portion BEN3. The circuit block GDB1 that overlaps with the bent portion BEN3 is arranged at a narrower pitch than the circuit block GDB2 that overlaps with the extending portion EXT2. However, if the number of circuit blocks GDB1 that overlap with the bent portion BEN3 increases, some of these circuit blocks GDB1 are arranged closer to the X2 side in the X direction as shown in FIG. Then, depending on the position of the switch circuit SWS, a part of the circuit block GDB1 arranged closer to the X2 side may be arranged between the display area DA and the switch circuit SWS.

Further, in the example shown in FIG. 11, each of the plurality of video signal lines SL extends from the switch circuit SWS toward the display area DA. Each of the plurality of video signal lines SL has a different length from the switch circuit SWS to the display area DA. That is, the plurality of video signal lines SL have a video signal line (first video signal line) SLd1 and a video signal line (second video signal line) SLd2. In a plan view, the length L2 of the video signal line SLd2 from the switch circuit SWS to the display area DA is longer than the length L1 of the video signal line SLd1 from the switch circuit SWS to the display area DA.

As shown in FIG. 11, among the plurality of scanning signal lines GL, the scanning signal line GLn arranged at the position closest to the switch circuit SWS intersects the video signal line SLd1 in the display area DA. Since the video signal line SLd1 does not need to intersect the scanning signal line GL outside the display area DA, the length L1 can be made relatively short. On the other hand, the scanning signal line GLn intersects the video signal line SLd2 outside the display area DA (specifically, between the display area DA and the switch circuit SWS). In this way, by crossing a part of the plurality of scanning signal lines GL and the video signal line SLd2 outside the display area DA, the number of times the video signal line SL intersects with each scanning signal line GL is made uniform. can do. As described with reference to FIG. 7, the parasitic capacitance C1 between the scanning signal line GL and the video signal line SL is one of the load factors given to the pixel PX. Therefore, by equalizing the number of intersecting each of the plurality of video signal lines SL and each of the plurality of scanning signal lines GL, it is possible to reduce the variation in the in-plane distribution of the load applied to the pixel PX. it can.

Further, the dummy pixel PXd described with reference to FIGS. 9 and 10 is connected to the region between the display region DA shown in FIG. 11 and the switch circuit SWS. Specifically, as shown in FIG. 12, the number of dummy pixels PXd connected to the video signal line SLd2 is larger than the number of dummy pixels PXd connected to the video signal line SLd1. Focusing on the portion that overlaps with the display area DA, the number of pixel PXs connected to the video signal line SLd2 is smaller than the number of pixel PXs connected to the video signal line SLd1. Therefore, by connecting the dummy pixel PXd to the video signal line SLd2, it is possible to reduce the difference in the total number of the pixel PX and the dummy pixel PXd connected to each of the video signal lines SL. In the example shown in FIG. 12, the dummy pixel PXd is not connected to the video signal line SLd1. However, as a modification with respect to FIG. 12, a dummy pixel PXd may be connected to the video signal line SLd1.

Further, as shown in FIG. 11, in the region between the display region DA and the switch circuit SWS, a part of the scanning signal line GL is pulled out to the Y1 side from the connection position with the circuit block GDB1. Then, the scanning signal line GL extends along the outer edge portion (outer peripheral side) of the display area DA. Further, in this region, since the arrangement pitch of the plurality of circuit blocks GDB1 is narrowed, there is an area in which the arrangement density of the scanning signal line GL is locally high (near the area overlapping with the extending portion BEN3). As shown in FIG. 11, in the scanning signal line GL, in the area between the display area DA and the switch circuit SWS, a portion where the plurality of video signal lines SL are orthogonal to each other in a plan view and an angle other than the orthogonal angle. Includes intersecting parts. The arrangement density of the scanning signal lines GL is relatively high in the portion where the plurality of scanning signal lines GL and the plurality of video signal lines SL intersect at angles other than orthogonal. The wiring layout shown in FIG. 11 can be expressed as follows. FIG. 13 is an enlarged plan view showing a part of the plurality of scanning signal lines shown in FIG. 11 and a part of the plurality of video signal lines extracted. In FIG. 13, different line types are used for each part in order to distinguish each part constituting the scanning signal line GL. The wiring part (main wiring part) GLp1 is a thick wire, the wiring part (first wiring part) GLp2 and the wiring part (third wiring part) GLp4 are thick dotted lines, and the wiring part (second wiring part) GLp3 is a thick one-point chain wire. Shown.

As shown in FIG. 13, the plurality of scanning signal lines GL are the scanning signal line (first scanning signal line) GLn1 and the scanning signal line (second scanning signal line) GLn2 that pass between the switch circuit SWS and the display area DA. have. Each of the scanning signal line GLn1 and the scanning signal line GLn2 overlaps with the wiring portion GLp1 in the display area DA, the wiring portion GLp2 overlapping the bending portion BEN3, and the extending portion EXT4, and extends along the direction T2. , And a wiring portion GLp4 that overlaps with the bent portion BEN4. Since the scanning signal line GL passing between the switch circuit SWS and the display area DA is bent according to the shape of the outer edge of the display area DA, the double-sided drive system can be applied also on the Y1 side of the display area DA. ..

Further, in a plan view, the number of the plurality of video signal lines SL where the scanning signal lines GLn1 intersect is the same as the number of the plurality of video signal lines SL where the scanning signal lines GLn2 intersect. However, in the display area DA, the number of the plurality of video signal lines SL where the scanning signal lines GLn1 intersect is different from the number of the plurality of video signal lines SL where the scanning signal lines GLn2 intersect. In this way, by making the number of video signal lines SL at which each of the plurality of scanning signal lines GL intersects the same number, the load applied to the scanning signal lines GL can be made uniform. Further, by making the number of the plurality of scanning signal lines GL at which the plurality of video signal lines SL intersect the same number, the load applied to the video signal lines SL can be made uniform.

Further, the display area DA is trapezoidal, and the peripheral area SA (see FIG. 1) is arranged so as to surround the trapezoidal display area DA. Therefore, in the Y direction, the end portion of the extending portion EXT2 (boundary with the bent portion BEN4) is on the Y1 side of the end portion of the extending portion EXT1 (boundary with the bent portion BEN3). In this case, as shown in FIG. 13, the plurality of scanning signal lines GL include those that overlap with the bent portion BEN3 and do not overlap with the extending portion EXT4 and the bent portion BEN4. In other words, the plurality of scanning signal lines GL include scanning signal lines (third scanning signal lines) GLn3 that do not have the wiring portion GLp3 extending along the direction T2. In other words, the scanning signal line GLn3 passing between the switch circuit SWS and the display area DA has the wiring unit GLp1 and the wiring unit GLp2, and does not have the wiring unit GLp3 and the wiring unit GLp4.

Further, as shown in FIG. 11, it is difficult to arrange the dummy pixels PXd shown in FIG. 12 at a high density in the portion where the arrangement density of the scanning signal line GL is high. Therefore, as shown in FIG. 14, in the region between the display region DA and the switch circuit SWS, there are a plurality of regions in which the arrangement densities of the dummy pixels PXd are different.

FIG. 14 is a plan view schematically showing a region where the density of dummy pixels is high and a region where the density of dummy pixels is low in the region between the display device and the switch circuit shown in FIG. In FIG. 14, in order to make it easier to identify each region, hatching is provided in the region where the arrangement density of the dummy pixels PXd is high, and a dot pattern is provided in the region where the arrangement density of the dummy pixels PXd is low.

As shown in FIG. 14, the direction orthogonal to the Y direction (first direction) is the X direction (second direction), one side of the X direction is the X1 side (first side), and the other side is X2 (second side). And. At this time, in the peripheral area SA (see FIG. 1), between the switch circuit SWS and the display area DA, the area on the X1 side (first area) DAM1 and the area on the X2 side (second area) DAM2. , And there is a region (third region) DAM3 between regions DAM1 and region DAM2. Here, the arrangement density of the dummy pixels PXd (see FIG. 12) in the area DAM3 is higher than the arrangement density of the dummy pixels PXd in the areas DAM1 and DAM2.

The configuration shown in FIG. 14 can also be expressed as follows. That is, the number of dummy pixels PXd (see FIG. 12) connected to each of the plurality of video signal lines SL is larger than the number in the area DAM1 and the number in the area DAM2, respectively. In the present embodiment, as described above, a part of the plurality of scanning signal lines GL is arranged at a high density. This makes it possible to drive each of the plurality of scanning signal lines GL by a double-sided drive system. Further, it is difficult to arrange the dummy pixel PXd shown in FIG. 12 in the region where the scanning signal line GL is arranged at a high density. However, by arranging the dummy pixel PXd in the region DAM3, it is possible to reduce the variation in the in-plane distribution of the load applied to the pixel PX.

Further, in the example shown in FIG. 14, the peripheral region SA (see FIG. 1) has a region (fourth region) DAM4 that overlaps with the bent portion BEN3 and is between the region DAM1 and the display region DA. The arrangement density of the dummy pixels PXd (see FIG. 12) in the region DAM4 is higher than the arrangement density of the dummy pixels PXd in the regions DAM1 and DAM2.

Next, as another method for reducing the variation in the in-plane distribution of the load applied to the pixel PX, a method of devising the layout of the enable line GWE (see FIG. 6) that supplies the potential to the scanning signal line GL will be described. .. The technique described below can be applied in combination with the method of using the dummy pixels PXd (see FIG. 9) arranged in the peripheral region SA (see FIG. 9) described above. Further, the technique described below can be applied independently without implementing the method using the dummy pixel PXd described above. FIG. 15 is an enlarged plan view showing an example of a layout of wiring for supplying an electric potential to a scanning signal line in the same portion as the display device shown in FIG. In FIG. 15, in each of the enable lines GWE1 and GWE2, the portion formed on the wiring layer WL1 shown in FIG. 2 is shown by a solid line, and the portion formed on the wiring layer WL2 or the wiring layer WL3 is shown by a dotted line.

As described with reference to FIG. 2, the display device DSP1 includes a wiring layer (first wiring layer) WL1 and a wiring layer (second wiring layer) WL2 formed of a material having a resistivity lower than that of the wiring layer WL1. , Equipped with. The conductor pattern formed on the wiring layer WL1 is made of a metal such as chromium (Cr), titanium (Ti), or molybdenum (Mo) or an alloy thereof. Further, the conductor pattern formed on the wiring layer WL2 is composed of, for example, a metal film having a multi-layer structure in which aluminum (Al) is sandwiched between molybdenum (Mo), titanium (Ti) and the like. In this case, the resistivity (specific resistance) of the wiring layer WL1 is higher than the specific resistance of the wiring layer WL2. As shown in FIG. 2, the scanning signal line GL is formed in the wiring layer WL1.

Further, as shown in FIG. 15, the display device DSP1 provides an enable line (first potential supply line) GWE1 that supplies a potential as a scanning signal Gsi (see FIG. 6) to the scanning signal line GL via the drive circuit GD1. I have. In plan view, the enable line GWE1 overlaps with the extending portion EXT1, the bending portion BEN1, and the extending portion EXT3, respectively. The enable line GWE1 passes through the wiring layer WL1 and the wiring layer WL2 in the region overlapped with the extending portion EXT3. It is preferable that the enable line GWE1 does not pass through the wiring layer WL1 only from the viewpoint of reducing the wiring resistance of the enable line GWE1. However, as shown in FIG. 15, since a part of the enable line GWE1 is formed in the wiring layer WL1, the in-plane difference of the time constant (gate time constant) between the plurality of scanning signal lines GL can be reduced. it can.

For example, in the example shown in FIG. 15, the length of the scanning signal line GLB connected to the circuit block GBB1 of the drive circuit GD1 and the circuit block GBB2 of the drive circuit GD2 is the length of the circuit block GBD1 and the drive circuit GD2 of the drive circuit GD1. It is shorter than the length of the scanning signal line GLD connected to the circuit block GBD2. In this case, the resistance value of the scanning signal line GLB is lower than the resistance value of the scanning signal line GLD. However, when a part of the enable line GWE1 that supplies the potential to the scanning signal line GLB is formed in the wiring layer WL1 having a high resistance value, the resistance value of the enable line GWE1 in the portion formed in the wiring layer WL1 becomes high. Therefore, when considering the entire supply path of the potential as the scanning signal Gsi, the difference in resistance value of each of the plurality of transmission paths can be reduced. As a result, the in-plane difference of the time constant can be reduced. That is, if the enable line GWE1 passes through the wiring layer WL1 between the circuit block GBD1 and the circuit block GBB1, the difference between the resistance values of the scanning signal line GLB and the scanning signal line GLD is reduced.

Further, in the example shown in FIG. 15, the display device DSP1 includes an enable line (second potential supply line) GWE2 that supplies a potential as a scanning signal Gsi to the scanning signal line GL via the drive circuit GD2. In a plan view, the enable line GWE2 overlaps with the extending portion EXT2 and the bending portion BEN2, respectively. The enable line GWE2 passes through the wiring layer WL1 and the wiring layer WL2 in the region overlapped with the bent portion BEN2. In the case of the enable line GWE2, since it does not overlap with the extending portion EXT3, the length of the portion formed in the wiring layer WL1 is shorter than that of the enable line GWE1. Therefore, the effect of suppressing the variation in the time constant due to the partial formation of the wiring layer WL1 is higher in the enable line GWE1. However, when each of the enable line GWE1 and the enable line GWE2 passes through both the wiring layer WL1 and the wiring layer WL2, the effect of suppressing the variation in the time constant is particularly high.

Further, the enable line GWE1 passes through the wiring layer WL2 and does not pass through the wiring layer WL1 in the region overlapped with the extending portion EXT1. Similarly, the enable line GWE2 passes through the wiring layer WL2 and does not pass through the wiring layer WL1 in the region overlapped with the extending portion EXT2. The lengths of the plurality of scanning signal lines GL connecting the extending portion EXT1 and the extending portion EXT2 are the same in design (however, there are some differences due to processing accuracy and the like). The length of each of the plurality of scanning signal lines GL connecting the extending portion EXT1 and the extending portion EXT2 is the longest among the plurality of scanning signal line GLs included in the display device DSP1. Therefore, in these regions, even if the resistance value of the path for supplying the potential is increased, the effect of reducing the variation in the time constant cannot be obtained. Further, in these regions, when the resistance value of the path for supplying the potential is high, the resistance value of the scanning signal line GL (for example, the scanning signal line GL1) connecting the extending portion EXT3 and the bending portion BEN2 becomes rather large. Therefore, it is preferable to reduce the resistance value of the enable line GWE1 or the enable line GWE2 in the region superimposing on the extending portion EXT1 and the region superimposing on the extending portion EXT2.

Further, the drive circuit GD1 has a circuit block (first B circuit block) GBB1, a circuit block (first C circuit block) GBC1, a circuit block (first D circuit block) GBD1, and a circuit block (first E circuit block) GBE1. ing. In the example shown in FIG. 15, the circuit block GBB1 and the circuit block GBC1 are superposed on the extending portion EXT3, and the circuit block GBD1 and the circuit block GBE1 are superposed on the bent portion BEN1. The enable line GWE1 passes through the wiring layer WL1 at a distance (first distance) D1 between the circuit block GBB1 and the circuit block GBC1. Further, the enable line GWE1 passes through the wiring layer WL1 at a distance (first distance) D2 between the circuit block GBD1 and the circuit block GBE1. The distance D2 is shorter than the distance D1.

Further, the drive circuit GD2 has a circuit block (second A circuit block) GBB2 and a circuit block (second B circuit block) GBC2. In the example shown in FIG. 15, the circuit block GBB2 and the circuit block GBC2 are superposed on the bent portion BEN2, and the circuit block GBD1 and the circuit block GBE1 are superposed on the bent portion BEN1. The enable line GWE2 passes through the wiring layer WL1 at a distance (third distance) D3 between the circuit block GBB2 and the circuit block GBC2. The distance D1 is longer than the distance D3.

Each of the plurality of scanning signal lines GL extends along the X direction. Therefore, if the portion of the enable lines GWE1 and GWE2 formed in the wiring layer WL1 extends along the X direction, a plurality of signal transmission paths (wiring path distance including the enable line GWE and the scanning signal line GL). It is easy to align the resistance values of. The length of the extending portion EXT3 in the X direction is longer than the length of the bent portion BEN1 and the bent portion BEN2 in the X direction. Therefore, in the region superimposing on the extending portion EXT3, the wiring length in the X direction can be lengthened as compared with the region superimposing on the bent portions BEN1 and BEN2. Therefore, as shown in FIG. 15, when the distance D1 is longer than the distance D2 and the distance D3, it is easy to align the resistance values of the plurality of signal transmission paths.

Next, the circuit layout in the region NDA2 shown in FIG. 1 will be described. FIG. 16 is a plan view schematically showing an outline of the circuit layout around the driver chip shown in FIG. FIG. 17 is an enlarged plan view of the circuit layout shown in FIG. 16 around the inspection terminal and the protection circuit. FIG. 18 is an enlarged cross-sectional view around the detection terminal and the protection circuit shown in FIG. FIG. 19 is an equivalent circuit diagram showing a configuration example of the protection circuit shown in FIGS. 17 and 18. FIG. 20 is an enlarged plan view showing a wiring layout around the driver chip shown in FIG. In FIG. 20, each of the wiring and the terminal provided at the position overlapping with the driver chip DRC1 is shown by a dotted line. Further, in FIG. 20, in order to visually show the distinction between the wiring GWT and the wiring PLT and other wiring (for example, the video signal connection line SCL), a dot pattern is attached to each of the control wiring GW, the wiring GWT, and the wiring PLT. doing.

The display device tends to prefer a display device having a large area occupancy of the display area DA (see FIG. 1) in the entire device. Therefore, it is preferable that the width (area) of the peripheral region SA (see FIG. 1) around the display region DA is as small as possible. Among the peripheral regions SA shown in FIG. 1, the region having the largest width is the region on the Y1 side of the display region DA in the Y direction. For example, in the Y direction, the width (length in the Y direction) of the peripheral region SA between the outer edge edge on the Y1 side and the display area DA is the width (length in the Y direction) of the extending portion EXT3 shown in FIG. Wider. Further, the width of the peripheral region SA between the outer edge end on the Y1 side and the display region DA is wider in the X direction than the widths of the extending portions EXT1 and EXT2 (the length in the X direction).

Therefore, in order to increase the area occupancy of the display area DA in the entire display device DSP1, it is important to improve the efficiency of the circuit layout in the peripheral area SA on the Y1 side of the display area DA. Therefore, the inventor of the present application has studied a technique for streamlining the layout of the circuit between the terminal portion TM1 in which the external terminal group connected to the external device is arranged and the display area DA in the display device DSP1. For example, the inventor of the present application examined the efficiency of the layout of the inspection terminal TPD shown in FIG. 16 and the protection circuit PC connected to the inspection terminal TPD.

As shown in FIG. 17, the display device DSP1 includes a plurality of terminals (first terminals) TPD. The terminal TPD is an inspection terminal used in a test process for electrically testing various circuits included in the display device DSP1 during the manufacturing process of the display device DSP1 or after the display device DSP1 is completed. As shown in FIG. 16, the terminal TPD is connected to the control wiring GW that controls the drive circuit GD1. The control wiring GW is a signal transmission path for transmitting a control signal to the drive circuits GD1 and GD2, and is an inspection wiring used when conducting an electrical test of the drive circuits GD1 and GD2. Thereby, the electric test of the drive circuits GD1 and GD2 can be performed via the terminal TPD.

Although one control wiring GW is shown in FIG. 16, a plurality of control wiring GWs are connected to the control circuit CTC as shown in FIG. 6 already described. The plurality of control wiring GWs include a clock line GWC, an enable signal ENB, and a start pulse line GWS.

Further, as shown in FIG. 18, each of the plurality of terminal TPDs is formed on the substrate SUB1 and is exposed from the substrate SUB2. As a result, the inspection can be performed in a state where the substrate SUB1 and the substrate SUB2 are overlapped with each other.

When the terminal exposed from the board SUB2 is connected to the internal circuit of the display device DSP1 like the terminal TPD, it is preferable to consider measures against electrostatic discharge (ESD: Electro-Static Discharge) for the internal circuit. .. Therefore, a protection circuit (first circuit) PC is connected between each of the plurality of terminal TPDs shown in FIG. 17 and an internal circuit (for example, a drive circuit) of the display device DSP1.

The protection circuit PC is a bypass circuit that protects the internal circuit from destruction or malfunction by bypassing and discharging the surge current applied from the outside due to electrostatic discharge or the like to the outside. In the example shown in FIG. 19, the protection circuit PC has a transistor Tr3 and a resistor RES1. Specifically, the resistor RES1 is connected between the wiring TW connected to the terminal TPD and the internal circuit DSC. Further, a transistor Tr3 is connected between the wiring TW and the wiring GDW to which the reference potential GND is supplied, and between the wiring TW and the wiring VDW to which the power supply potential VD is supplied. In the case of the example shown in FIG. 18, the surge current applied to the terminal TPD is discharged to the terminal GPD or the terminal VPD via the transistor Tr3. As a result, it is possible to suppress the surge current from flowing into the internal circuit DSC, and to suppress the destruction or malfunction of the internal circuit DSC.

Note that FIG. 19 shows a configuration example of the protection circuit PC, and there are various modifications in the structure of the protection circuit PC. For example, instead of the transistor Tr3 shown in FIG. 19, a diode (not shown) may be connected to the terminal TPD. Further, the number and connection positions of the resistor RES1 and the transistor Tr3 (or diode) have various modifications in addition to the example shown in FIG. For example, when the potential of the applied surge voltage is known, only one of the two transistors Tr3 shown in FIG. 19 may be connected to the terminal TPD. Further, three or more transistors Tr3 may be connected to one terminal TPD.

Further, as shown in FIG. 16, the peripheral region SA of the substrate SUB1 has a region NDA1 covered with the substrate SUB2 and a region NDA2 exposed from the substrate SUB2. The protection circuit PC is arranged in the area NDA1. In other words, as shown in FIG. 18, the protection circuit PC is located between the substrate SUB1 and the substrate SUB2. As a result, it is possible to suppress the direct application of electrostatic discharge to the protection circuit PC itself. However, when the protection circuit PC is arranged in the area NDA1, it is necessary to improve the efficiency of the circuit layout in the area NDA1.

Therefore, as shown in FIG. 16, in the display device DSP1, each of the plurality of terminal TPDs used for inspection is on the Y1 side of the display area DA, and the driver chip DRC1 on which the control circuit CTC is formed is formed. It is on the X1 side. Further, the protection circuit PC connected to the terminal TPD is on the Y1 side of the display area DA and on the X1 side of the driver chip DRC1 in which the control circuit CTC is formed. On the other hand, there is no terminal TPD and protection circuit PC on the Y2 side of the display area DA (see FIG. 1) and the X2 side of the driver chip DRC1. When there are drive circuits GD on both sides of the X1 side and the X2 side in the X direction as in the present embodiment, a method of arranging the inspection terminal TPD and the protection circuit PC on the X1 side and the X2 side, respectively, can be considered. However, as in the present embodiment, the inspection terminal TPD and the protection circuit PC are centrally arranged on either the X1 side or the X2 side to improve the efficiency of the layout of the circuit connected to the terminal TPD. it can.

Further, when comparing the region on the X1 side and the region on the X2 side of the driver chip DRC1, the region on the X1 side has more space. In the case of a trapezoid as in the present embodiment, at both ends of the side connecting the short side and the long side which are parallel to each other, the angle formed by the side and the short side is an acute angle, and the side and the long side The angle formed by is an acute angle. For example, in FIG. 1, the angle formed by the extension line of the extension portion EXT1 and the extension line of the extension portion EXT4 is an obtuse angle. Further, the angle formed by the extension line of the extending portion EXT2 and the extension line of the extending portion EXT4 is an acute angle. In this case, as shown in FIG. 16, in the direction T3 which is the extending direction of the driver chip DRC1, the distance D4 from the end of the driver chip DRC1 on the X1 side to the outer edge of the substrate SUB1 on the X1 side is the driver chip DRC1. The distance from the end of the X2 side to the outer edge of the substrate SUB1 on the X2 side is longer than D5.

In this way, when comparing the area on the X1 side of the driver chip DRC1 and the area on the X2 side, if there is more space in the area on the X1 side, the inspection terminal TPD and the protection circuit PC are used as the driver chip DRC1. By arranging the terminal TPD and the protection circuit PC for inspection on the X1 side of the above, it is possible to suppress an increase in the area of the peripheral region SA due to the arrangement.

As shown in FIG. 16, each of the plurality of terminal TPDs is on a line extending the driver chip DRC1 along the direction T3. As shown in FIG. 17, each of the plurality of terminal TPDs is arranged along the direction T3 which is the extending direction of the long side of the driver chip DRC1 (see FIG. 16).

Further, as described above, the display device DSP1 has a drive circuit GD1 on the X1 side and a drive circuit GD2 on the X2 side in the X direction. When a plurality of terminal TPDs are integrated in one place, a control wiring GW for connecting the terminal TPDs and the plurality of drive circuits GD1 and GD2 is required. Therefore, the control wiring GW has a control wiring (first control wiring) GW1 for transmitting a control signal to the drive circuit GD1 and a control wiring (second control wiring) GW2 for transmitting the control signal to the drive circuit GD2. The control wiring GW1 is connected to the driver chip DRC1, the drive circuit GD1, and the terminal TPD. The control wiring GW2 is connected to the driver chip DRC1 and the drive circuit GD2. As shown in FIG. 16, the terminal TPD is arranged on the X1 side of the driver chip DRC1. Therefore, a path for electrically connecting the control wiring GW2 and the inspection terminal TPD is required. Therefore, the display device DSP1 has the wiring (first inspection wiring) GWT (the portion indicated by the alternate long and short dash line at the position overlapping with the driver chip DRC1) shown in FIGS. 16 and 20 as the wiring path for connecting the control wiring GW2 and the terminal TPD. have. The wiring GWT overlaps with the driver chip DRC1 in a plan view and extends along the direction T3. The control wiring GW2 is electrically connected to the terminal TPD via the wiring GWT.

Further, in the case of the display device DSP1, the power supply wiring PL that supplies the power supply potential to the drive circuit GD is connected to the terminal TPD via the protection circuit PC. As described with reference to FIG. 6, the power supply wiring PL includes a wiring PLH to which the potential VDH is supplied and a wiring PLL to which a potential lower than the potential VDH is supplied. The power supply wiring PL is connected to each of the plurality of drive circuits GD1 and GD2. Therefore, the power supply wiring PL includes a power supply wiring (first power supply wiring) PL1 for transmitting the power supply potential to the drive circuit GD1 and a power supply wiring (second power supply wiring) PL2 for transmitting the power supply potential to the drive circuit GD2. The power supply wiring PL1 is connected to the drive circuit GD1 and the terminal TPD. The power supply wiring PL2 is connected to the drive circuit GD2. Further, the display device DSP1 provides a wiring (second inspection wiring) PLT (a portion indicated by a dotted line at a position overlapping the driver chip DRC1) shown in FIGS. 16 and 20 as a wiring path for connecting the power supply wiring PL2 and the terminal TPD. Have. The wiring PLT overlaps with the driver chip DRC1 in a plan view and extends along the direction T3. The power supply wiring PL2 is electrically connected to the terminal TPD via the wiring PLT.

As shown in FIG. 20, each of the plurality of terminals PD1 and the plurality of terminals PD2 connected to the driver chip DRC1 are arranged along the direction T3 inclined with respect to each of the Y direction and the X direction. The wiring GWT and wiring PLT are arranged between the terminal PD1 and the terminal PD2. In other words, the wiring GWT and wiring PLT traverse the region DRA along direction T3. Further, as shown in FIG. 5, the wiring GWT and the wiring PLT are located between the driver chip DRC1 and the substrate SUB1 in the Z direction. The Z direction is a direction perpendicular to the XY plane including the X direction and the Y direction shown in FIG. Further, a large number of video signal connection lines SCL are arranged on the Y2 side of the terminal PD1. Further, a wiring FDW for connecting the wiring board FWB1 and the driver chip DRC1 is arranged between the terminal PD2 and the terminal PD3. Therefore, the wiring GWT and the wiring PLT are between the terminal PD1 and the terminal PD2. When the inspection wiring GWT and the wiring PLT are arranged between the terminal PD1 and the terminal PD2, the location where the inspection wiring and the other wiring intersect can be reduced. As a result, the influence of noise on the inspection wiring from other wiring can be reduced. Alternatively, it is possible to reduce the noise effect of other wiring from the inspection wiring.

Note that FIG. 16 shows a single wiring GWT and wiring PLT at a position where it overlaps with the driver chip DRC1 for ease of viewing. However, the number of wiring GWTs and the number of wiring PLTs are not limited to one, and may be a plurality of wirings. If there are a plurality of wiring GWTs in the region DRA (see FIG. 3) that overlaps with the driver chip DRC1, the types of signals transmitted via the region DRA can be increased.

Further, as shown in FIG. 20, in a plan view, the control wiring GW does not overlap with each of the plurality of video signal connection lines SCL. Therefore, it is possible to suppress the influence of noise on the control wiring GW and the plurality of video signal connection lines SCL. As shown in FIG. 16, a plurality of video signal connection lines SCL are located between the control wiring GW and the display area DA. In this case, since the control wiring GW is arranged along the outer edge portion of the substrate SUB1, the control wiring GW is bent at a plurality of points. Although each of the plurality of video signal connection line SCLs is also bent, the number of bent portions of the control wiring GW is larger than the number of bent portions of each video signal connection line SCL. In other words, since each video signal connection line SCL is arranged between the control wiring GW and the display area DA, the number of bent portions can be reduced. The total number of video signal connection lines SCL is larger than that of the control wiring GW. Therefore, the arrangement pitch of the video signal connection line SCL is narrower than the arrangement pitch of the control wiring GW. By reducing the number of bent portions of each video signal connecting line SCL, it is possible to reduce the number of places where the arrangement pitch of the video signal connecting line SCL is locally narrowed. Therefore, a large number of video signal connection lines SCL can be arranged at a narrow pitch.

The technique found by the inventor of the present application has been specifically described above based on the embodiment as an example, but the present invention is not limited to the above embodiment and is variously modified without departing from the gist thereof. It is possible.

For example, in the above embodiment, the case of a liquid crystal display device is illustrated as a disclosure example, but as another application example, an organic EL display device, another self-luminous display device, an electronic paper having an electrophoresis element, or the like is used. All flat panel type display devices such as type display devices can be mentioned. In addition, it can be applied from small to medium size to large size without any particular limitation.

Further, for example, in the above embodiment, as shown in FIG. 3, both ends of each of the plurality of scanning signal lines GL are connected to the drive circuit GD1 and the drive circuit GD2, and the entire display area DA is driven on both sides. An embodiment of driving by a method has been described. However, as a modification, the entire display area DA may be driven by a one-sided drive method. In this case, for example, the drive circuit GD1 shown in FIG. 3 may not be provided, and all the scanning signal lines GL may be driven by the drive circuit GD2 in a one-sided drive system. Alternatively, each of the plurality of scanning signal lines GL may be connected to one of the drive circuit GD1 and the drive circuit GD2, and may not be connected to the other.

Further, for example, in each diagram for explaining the relationship between the drive circuit GD and the scanning signal line GL connected to the drive circuit GD, such as FIG. 6, a circuit block in which one switch circuit GSW is connected to one shift register circuit GSR. An example is shown in which one scanning signal line GL is connected to each of the GDBs. The switch circuit GSW and the scanning signal line GL need to have a one-to-one correspondence, but as shown in the modified example shown in FIG. 21, a plurality of switch circuits GSW are connected to one shift register circuit GSR. Is also good. FIG. 21 is a circuit block diagram showing a modified example of the circuit block shown in FIG. In the example shown in FIG. 21, four switch circuits GSW are connected to each of the plurality of shift register circuits GSR. A set of one shift register circuit GSR and four switch circuits GSW constitutes one circuit block. Further, one scanning signal line GL is connected to each of the plurality of switch circuits.

In the case of the modified example shown in FIG. 21, enable lines GWE independent of each other are connected to each of the switch circuits GSW included in one circuit block GDB. In this case, by combining the pulse signal supplied from the shift register circuit GSR and the pulse signal supplied from the enable line GWE, the scanning signal Gsi (see FIG. 6) is sequentially generated for each of the plurality of scanning signal lines GL. Can be transmitted. In the case of the modified example shown in FIG. 21, the number of shift register circuits GSR can be reduced as compared with the example described with reference to FIG. Further, assuming that the number of scanning signal lines GL is the same, as shown in FIG. 21, each of the plurality of scanning signal lines GL is connected to one of a plurality of enable lines GWE independent of each other. The configuration is advantageous in the following points. That is, since the number of switch circuits GSW connected to the enable line GWE is reduced (1/4) in the example shown in the figure, the load capacitance of the enable GWE line can be reduced.

Further, for example, in the above embodiment, an example in which each of the plurality of terminal TPDs is connected via the protection circuit PC has been described as shown in FIG. However, if it is not necessary to consider electrostatic discharge to the internal circuit, the protection circuit PC may not be provided.

Within the scope of the idea of the present invention, those skilled in the art can come up with various modified examples and modified examples, and it is understood that these modified examples and modified examples also belong to the scope of the present invention.

For example, a person skilled in the art appropriately adds, deletes, or changes the design of each of the above-described embodiments, or adds, omits, or changes the conditions of the process of the present invention. As long as it has a gist, it is included in the scope of the present invention.

The present invention is effective when applied to an input device or a display device having an input detection function.

10,20 Insulation substrate 11,12,13,14 Insulation film AL1, AL2 Alignment film BEN1, BEN2, BEN3, BEN4 Bending part BL Backlight unit BM Light-shielding layer C1, C2, C3, C4, C5 Parasitic capacitance CD Common electrode drive Circuit CDF Conductive CE Common electrode CFB, CFG, CFR Color filter CML Common line CS Stray capacitance GCL Clock signal GSP Start pulse signal CTC Control circuit D1, D2, D3, D4, D5 Distance DA display area DAM1, DAM2, DAM3, DAM4 Region DE drain electrode DR1, DR2
DRC1 driver chip (semiconductor chip)
DRA area (first area)
DS display surface DSC internal circuit DSP1, DSPh1, DSPh2 Display device ENB Enable signal EXT1, EXT2, EXT3, EXT4 Extended parts FDW, FW, GDW, GWT, PLH, PLL, PLT, TW, VDW Wiring FWB1 Wiring board GBA1, GBB1 , GBB2, GBC1, GBC2, GBD1, GBD2, GBE1, GDB, GDB1, GDB2 Circuit block GBU Buffer circuit GCL, GCL1, GCL2 Clock signal GD, GD1, GD2 Drive circuit GE Gate electrode GL, GL1, GL2, GLA, GLB, GLD, GLn, GLn1, GLn2, GLn3 Scanning signal line GLp1, GLp2, GLp3, GLp4 Wiring part GND Reference potential GPD, PD1, PD2, PD3, TM1, TPD, VPD terminal Gsi, Gsi1, Gsi2, Gsin Scanning signal GSR shift register Circuit GSW Switch circuit GW, GW1, GW2 Control wiring GWC, GWC1, GWC2 Clock line GWE, GWE1, GWE2 Enable line GWS Start pulse line LQ Liquid crystal layer NDA1, NDA2 Area OCL Overcoat layer OD1, OD2 Optical element PC protection circuit PE pixel Electrodes PL, PL1, PL2 Power supply wiring PNL1 Display panel PSC Power supply circuit PSW Pixel switch element PX Pixel PXd Dummy pixel RES1 Resistance SA Peripheral area SCL Video signal connection line SD Video signal line Drive circuit SE Source electrode SL, SL1, SL2, SLd1, SLd2, SLm Video signal line Spic Video signal SUB1, SUB2 Board SWS switch circuit T1, T2, T3, X, Y direction Tr1, Tr2, Tr3 Transistor VD Power supply potential VDH, VDL potential WL1, WL2, WL3 Wiring layer

Claims (11)

The display area where the first pixel is arranged and
Overlapping with the light-shielding layer, the peripheral area outside the display area,
A plurality of scanning signal lines and a plurality of video signal lines in the display area,
The first control circuit that supplies control signals including clock signals,
The first drive circuit and the second drive circuit that supply the scan signal,
A first clock line that connects the first control circuit and the first drive circuit and is supplied with a first clock signal, and
A second clock line that connects the first control circuit and the second drive circuit and is supplied with a second clock signal is provided.
The plurality of video signal lines extend in the first direction,
The light-shielding layer includes a first extending portion and a second extending portion extending along the first direction, and a first bending portion and a first bending portion between the first extending portion and the second extending portion. Has a second bend and
The first extending portion is connected to the first bending portion, and the second extending portion is connected to the second bending portion.
The length of the second extending portion is longer than the length of the first extending portion.
In a plan view, the first bent portion overlaps with the first clock line, and the second bent portion is between the end portion of the first clock line and the end portion of the second clock line. There is a display device. A second pixel arranged in the peripheral region is provided.
The first drive circuit has a first A circuit block and a first B circuit block connected via the first clock line.
The light-shielding layer has a third extending portion between the first bent portion and the second bent portion.
The first A circuit block is superimposed on the first extending portion, and the first B circuit block is superimposed on the third extending portion.
The plurality of scanning signal lines include a first A scanning signal line connected to the first A circuit block and a first B scanning signal line connected to the first B circuit block.
The display device according to claim 1, wherein the number of the second pixels connected to the first B scanning signal line is larger than the number of the second pixels connected to the first A scanning signal line. A selection circuit is provided between the display area and the first control circuit.
The display device according to claim 1 or 2, wherein the second drive circuit is not provided between the selection circuit and the display area in a plan view. A selection circuit is provided between the display area and the first control circuit.
The plurality of video signal lines have a first video signal line and a second video signal line.
In a plan view, the length of the second video signal line from the selection circuit to the display area is longer than the length of the first video signal line from the selection circuit to the display area, claims 1 to 3. The display device according to any one of the above items. A second pixel arranged in the peripheral region is provided.
The display device according to claim 4, wherein the number of the second pixels connected to the second video signal line is larger than the number of the second pixels connected to the first video signal line. A selection circuit between the display area and the first control circuit,
A second pixel arranged in the peripheral region is provided.
When the direction orthogonal to the first direction is the second direction, one side of the second direction is the first side, and the other side is the second side.
Among the peripheral regions, between the selection circuit and the display region are the first region on the first side, the second region on the second side, and the first region and the second region. There is a third area in between,
A claim that the number of the second pixels connected to each of the plurality of video signal lines is such that the number in the third region is larger than the number in the first region and the number in the second region, respectively. The display device according to any one of 1 to 5. The peripheral region has a third bent portion located on the opposite side of the first bent portion via the first extending portion.
Among the peripheral regions, between the selection circuit and the display region, there is a fourth region that overlaps with the third bent portion and is located between the first region and the display region.
The display device according to claim 6 , wherein the arrangement density of the second pixel in the fourth region is higher than the arrangement density of the second pixel in the first region and the second region. A first wiring layer and a second wiring layer formed of a material having a resistivity lower than that of the first wiring layer.
A first potential supply line that supplies a potential to the scanning signal line via the first drive circuit is provided.
The light-shielding layer has a third extending portion between the first bent portion and the second bent portion.
The first potential supply line overlaps with the third extending portion,
The one according to any one of claims 1 to 7 , wherein the first potential supply line passes through the first wiring layer and the second wiring layer in the region overlapped with the third extending portion. Display device. The first drive circuit includes a first B circuit block, a first C circuit block, a first D circuit block, and a first E circuit block.
The first potential supply line passes through the second wiring layer at a first distance between the first B circuit block and the first C circuit block, and the first D circuit block and the first E circuit block. Via the second wiring layer at a second distance to and from
The display device according to claim 8 , wherein the second distance is shorter than the first distance. A second potential supply line for supplying a potential to the scanning signal line via the second drive circuit is provided.
The first drive circuit has a first B circuit block and a first C circuit block.
The first potential supply line passes through the second wiring layer at a first distance between the first B circuit block and the first C circuit block.
The second drive circuit has a second A circuit block and a second B circuit block.
The second potential supply line passes through the second wiring layer at a third distance between the second A circuit block and the second B circuit block.
The first B circuit block and the second A circuit block are connected to the same scanning signal line.
The display device according to claim 8 , wherein the first distance is longer than the third distance. The first potential supply line overlaps with the first extending portion,
The first item according to any one of claims 8 to 10 , wherein the first potential supply line passes through the second wiring layer and does not pass through the first wiring layer in the region superimposed on the first extending portion. Display device.

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