JP6806504B2 - Display device - Google Patents

Description

The present invention relates to a display device.

The display device generally has a rectangular outer shape. Further, in recent years, with the expansion of the fields of use of display devices, there are display devices having shapes other than rectangles. For example, Japanese Patent Application Laid-Open No. 2009-1223636 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2008-292995 (Patent Document 2) describe display devices.

JP-A-2009-1223636 Japanese Unexamined Patent Publication No. 2008-292995

The display area of the display device includes a plurality of electrodes for driving the electro-optical layer and signal lines for supplying drive signals and scanning signals to the plurality of electrodes. Further, in the peripheral region around the display region, a circuit for supplying signals to the plurality of electrodes is arranged. When the shape of the display area or the shape of the outer edge of the peripheral area is a shape other than a rectangle or a square, a problem arises due to the shape of the display area or the peripheral area. Hereinafter, in the present specification, a shape other than a rectangle or a square may be referred to as a “variant shape”.

For example, when the lengths of a plurality of signal lines are different from each other due to the irregular shape of the display area, the in-plane distribution of the load applied to the signal lines becomes non-uniform. If the in-plane distribution of the load applied to the signal line becomes non-uniform in this way, the image quality deteriorates.

Further, if the lengths of the plurality of signal lines are the same as each other, it is necessary to make the outer shape of the peripheral region rectangular. In this case, the occupied area of the display area in the display device is reduced.

An object of the present invention is to provide a technique for improving the performance of a display device.

A brief outline of the typical inventions disclosed in the present application is as follows.

The display device as one aspect of the present invention includes a display area in which the first pixels are arranged, a peripheral area that is superimposed on the light-shielding layer and is outside the display area, and a plurality of scanning signal lines and a plurality of scanning signal lines in the display area. The first drive circuit and the second drive circuit for supplying the video signal line and the scanning signal of the above, the first potential supply line for supplying the potential to the plurality of scanning signal lines via the first drive circuit, and the first wiring. It includes a layer and a second wiring layer made of a material having a resistance lower than that of the first wiring layer. The plurality of video signal lines extend in the first direction. The light-shielding layer includes a first extending portion and a second extending portion extending along the first direction, and a first bending portion and a first bending portion between the first extending portion and the second extending portion. It has a second bent portion and a third extending portion between the first bent portion and the second bent portion. The first extending portion is connected to the first bent portion, and the second extending portion is connected to the second bent portion. The first potential supply line overlaps with the third extending portion. The plurality of scanning signal lines have a first scanning signal line and a second scanning signal line. A part of the first scanning signal line is superimposed on the third extending portion, and a part of the second scanning signal line is superimposed on the first extending portion. In a plan view, the number of the plurality of video signal lines intersecting the first scanning signal lines and the number of the plurality of video signal lines intersecting the second scanning signal lines in the display area are different. There is. In the region overlapped with the third extending portion, the first potential supply line passes through the first wiring layer and the second wiring layer.

It is a top view which shows one structural example of the display device which is one Embodiment. It is an enlarged sectional view of a part of the display area of the display device shown in FIG. It is a top view which shows an example of the arrangement of common electrodes in the display device shown in FIG. It is an equivalent circuit diagram which shows the pixel in the display device shown in FIG. FIG. 5 is an enlarged cross-sectional view of a connection portion between the driver chip and the substrate shown in FIG. It is a circuit block diagram which shows the structural example of the scanning signal line drive circuit shown in FIG. It is a circuit diagram which shows typically the factor of the load applied to each of the plurality of pixels shown in FIG. Of the display devices shown in FIG. 3, it is an enlarged plan view showing the details of the circuit configuration on the upper side. It is an enlarged plan view which shows the example of the layout of the wiring which supplies a clock signal to a drive circuit in the same part as the display device shown in FIG. It is an enlarged plan view of the display device which is a modification with respect to FIG. It is an enlarged plan view which shows the circuit layout around the circuit block shown in FIG. It is an enlarged plan view which shows the modification with respect to FIG. It is an enlarged plan view of the display device which is another modification with respect to FIG. It is an enlarged plan view which shows the circuit layout around the circuit block shown in FIG. Of the plurality of circuit blocks shown in FIG. 13, it is an enlarged plan view showing a circuit layout around a circuit block different from the circuit block shown in FIG. FIG. 5 is an enlarged plan view showing a circuit layout around a circuit block of a display device, which is a modification of FIGS. 12 and 14. Of the display devices shown in FIG. 3, it is an enlarged plan view showing the details of the circuit configuration on the lower side. FIG. 5 is an enlarged plan view showing an example of a layout of common electrodes in the plane shown in FIG. It is a circuit block diagram which shows the modification with respect to the circuit block shown in FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of changes as appropriate even while maintaining the gist of the invention are naturally included in the scope of the present invention. Further, in order to clarify the description, the drawings may schematically represent the width, thickness, shape, etc. of each part as compared with the embodiment, but this is just an example, and the interpretation of the present invention is used. It is not limited.

Further, in this specification and each figure, the same elements as those described above with respect to the above-mentioned figures may be designated by the same reference numerals, and detailed description thereof may be omitted as appropriate.

Further, in the drawings used in the embodiments, hatching attached to distinguish the structures may be omitted depending on the drawings.

Further, the technique described in the following embodiments can be widely applied to a display device provided with a mechanism for supplying signals from the periphery of the display area to a plurality of elements in the display area provided with an electro-optical layer. The electro-optical layer is a layer provided with an element that is driven by an electrical control signal and has a function of forming a display image. Examples of the display device as described above include various display devices such as a liquid crystal display device, an organic EL (Electro-Luminescence) display device, and a plasma display device. In the following embodiments, a liquid crystal display device will be described as a typical example of the display device.

Further, the liquid crystal display device is roughly classified into the following two types according to the application direction of the electric field for changing the orientation of the liquid crystal molecules in the liquid crystal layer which is the display function layer. That is, as the first classification, there is a so-called vertical electric field mode in which an electric field is applied in the thickness direction (or out-of-plane direction) of the display device. The vertical electric field mode includes, for example, a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. Further, as the second classification, there is a so-called lateral electric field mode in which an electric field is applied in the plane direction (or in-plane direction) of the display device. The lateral electric field mode includes, for example, an IPS (In-Plane Switching) mode and an FFS (Fringe Field Switching) mode, which is one of the IPS modes. The technique described below can be applied to both the longitudinal electric field mode and the transverse electric field mode, but in the embodiment described below, the display device of the transverse electric field mode will be described as an example.

<Display device configuration>
FIG. 1 is a plan view showing a configuration example of a display device according to an embodiment. FIG. 2 is an enlarged cross-sectional view of a part of the display area of the display device shown in FIG. FIG. 3 is a plan view showing an example of a circuit layout in the display device shown in FIG. FIG. 4 is an equivalent circuit diagram showing pixels in the display device shown in FIG. FIG. 5 is an enlarged cross-sectional view of the connection portion between the driver chip and the substrate shown in FIG. FIG. 6 is a circuit block diagram showing a configuration example of the scanning signal line drive circuit shown in FIG. In FIG. 1, a portion of the peripheral region SA that overlaps with the light-shielding layer BM is shown with a darker color pattern than the display region DA. Further, in FIG. 2, in order to show an example of the positional relationship between the scanning signal line GL and the video signal line SL in the thickness direction of the substrate SUB1, the scanning signal line GL provided in a cross section different from that of FIG. 2 is also shown. ing. Further, a large number of video signal connection lines SCL are connected to the switch circuit SWS shown in FIG. 3, but in FIG. 3, a dot pattern is attached to a region where a large number of SCLs are arranged.

As shown in FIG. 1, the display device DSP1 has a display panel PNL1 and a driver chip DRC1 mounted on the display panel PNL1. The display panel PNL1 has a display surface DS (see FIG. 2) on which an image is displayed. The driver chip DRC1 is an IC (Integrated Circuit) chip provided with a control circuit for controlling the drive of the display panel PNL1. Further, the display device DSP1 has a wiring board (wiring portion) FWB1 which is a wiring member connected to the display panel PNL1. The wiring board FWB1 is a flexible wiring board in which a plurality of wirings are covered with resin. The wiring board FWB1 is connected to the terminal portion TM1 of the display panel PNL1 as schematically shown with an arrow in FIG. In addition to electrical signals such as drive signals and video signals, a power supply voltage for driving the display panel PNL1 is supplied to the terminal portion TM1 from a circuit outside the display panel PNL1 via the wiring board FWB1.

Further, the display panel PNL1 includes a display area DA in which a plurality of pixels (first pixel) PX (see FIG. 3) are arranged, and a peripheral area SA outside the display area DA. In the example shown in FIG. 1, the display area DA is trapezoidal, and each of the long side and the short side extending parallel to each other extends along the Y direction. Further, in the example shown in FIG. 1, the Y direction is the longitudinal direction of the display area DA. The display area DA is an area in which an image visible from the display surface DS (see FIG. 2) side is displayed based on the signal input to the display device DSP1. The peripheral region SA is arranged so as to continuously surround the display region DA in a plan view. In a plan view, the inner side (end) of the peripheral region SA is in contact with the outer edge of the display region DA. A plurality of pixels PX are arranged in the display area DA. For example, as shown in FIG. 1, in a plan view, two directions intersecting with each other, preferably orthogonal to each other, are the X direction and the Y direction. The plurality of pixels PX are arranged in a matrix in the X direction and the Y direction in the display area DA in a plan view. In the present application, "in plan view" means a case where the display panel PNL1 is viewed from a direction perpendicular to the display surface.

Further, the peripheral area SA is a non-display area in which an image visible from the outside is not displayed, and is arranged so as to surround the periphery of the display area DA. The peripheral region SA is a non-display region, and most of the peripheral region SA overlaps with the light shielding layer BM.

Further, as shown in FIG. 2, the display panel PNL1 includes a substrate SUB1, a substrate SUB2 arranged to face the substrate SUB1, and a liquid crystal layer LQ as an electro-optical layer arranged between the substrate SUB1 and the substrate SUB2. Have. In other words, the display device DSP1 of the present embodiment is a liquid crystal display device including a liquid crystal layer LQ as an electro-optical layer. In the present embodiment, the substrate SUB1 can be paraphrased as an array substrate, and the substrate SUB2 can be paraphrased as an opposed substrate.

As shown in FIG. 1, the driver chip DRC1 and the terminal portion TM1 are located in a region (exposed region) NDA2 of the peripheral region SA of the display panel PNL1 that does not overlap with the light-shielding layer BM. When one side in the Y direction shown in FIG. 1 is the Y1 side and the other side is the Y2 side, the region NDA2 is on the Y1 side of the display region DA in the Y direction. In most of the display panel PNL1 in a plan view, the substrate SUB1 and the substrate SUB2 face each other as shown in FIG. However, the region NDA2 shown in FIG. 1 is exposed from the substrate SUB2 (see FIG. 5). In the example shown in FIG. 5, the light-shielding layer BM is formed on the substrate SUB2, and the region NDA2 (see FIG. 1) does not overlap with the light-shielding layer BM. The light-shielding layer BM is arranged in the display area DA in addition to the peripheral area SA. In a plan view, it is provided so as to surround each of the plurality of pixels PX (see FIG. 3) in the display area DA.

Further, the driver chip DRC1 is mounted on the region DRA in the peripheral region SA (specifically, region NDA2). As shown in FIG. 5, the terminal PD1 and the terminal PD2 are arranged in the region DRA of the substrate SUB1, and the driver chip DRC1 is connected to the terminal PD1 and the terminal PD2. The terminal PD1 is an interface that electrically connects the circuit formed on the driver chip DRC1 and the circuit formed on the display panel PNL1 (see FIG. 1). Further, the terminal PD2 is an interface for electrically connecting the driver chip DRC1 and the wiring board FWB1. The driver chip DRC1 is connected to the terminal PD3 via the terminal PD2 and the wiring FDW. Further, the wiring FW of the wiring board FWB1 is connected to the terminal PD3. Further, as shown in FIG. 1, at least a part (for example, a long side) of the driver chip DRC1 extends along a direction T3 that is inclined with respect to each of the Y direction and the X direction.

As shown in FIG. 4, the display device DSP1 has a video signal line drive circuit SD. The video signal line drive circuit SD is electrically connected to the pixel PX and drives the liquid crystal layer LQ, which is an electro-optical layer, via the video signal line SL. In the example of this embodiment, the video signal line drive circuit SD is formed on the driver chip DRC1. The video signal line drive circuit SD supplies the video signal Spic to the pixel electrode (first electrode) PE included in each of the plurality of pixel PXs via the video signal line SL. Further, as shown in FIG. 6, the driver chip DRC1 has a control circuit (first control circuit) CTC that supplies a control signal to the drive circuit via the control wiring GW. The control circuit CTC is electrically connected to the drive circuit via the terminal PD1 (see FIG. 5).

In the present embodiment, as shown in FIG. 5, an example in which the driver chip DRC1 is mounted on the substrate SUB1 will be described. However, the position of the driver chip DRC1 and the position of the control circuit CTC have various modifications in addition to the region DRA shown in FIG. For example, the driver chip DRC1 may be mounted on the wiring board FWB1. In this case, the wiring board FWB1 is connected to the terminal PD1. As a result, even when the driver chip DRC1 is mounted on the wiring board FWB1, the control circuit CTC of the driver chip DRC1 is electrically connected to the drive circuit via the terminal PD1 of the region DRA.

As shown in FIG. 3, the display device DSP1 has a plurality of video signal lines SL and a plurality of pixels PX. In the display area DA, a plurality of pixels PX are arranged between the substrate SUB1 and the substrate SUB2 (see FIG. 2). The plurality of pixels PX are arranged in a matrix in the X and Y directions, and m × n are arranged (where m and n are positive integers). The plurality of video signal lines SL extend in the Y direction and are arranged at intervals in the X direction. Each of the plurality of pixels PX is partitioned by the video signal line SL in the X direction. Therefore, the number of pixels PX arranged along the X direction corresponds to the number of video signal lines SL. In the example shown in FIG. 3, m video signal lines SL are arranged in the order of the video signal lines SL1, SL2, and SLm from X1 which is one side in the X direction toward X2 side which is the other side. ing. Each of the plurality of video signal lines SL is drawn out to the peripheral region SA outside the display region DA. Each of the plurality of video signal line SLs has a driver chip DRC1 via a video signal connection line SCL as a connection wiring (also referred to as a lead-out wiring) for connecting the video signal line SL in the display area DA and the driver chip DRC1 to each other. Is electrically connected to.

The video signal line SL and the video signal connection line SCL are video lines that function as wiring for transmitting a video signal, but the video signal line SL and the video signal connection line SCL can be distinguished as follows. That is, of the video lines that are connected to the driver chip DRC1 and are signal transmission paths that supply video signals to the plurality of pixels PX, the portion (wiring portion) that overlaps the display area DA is called the video signal line SL. Further, of the video lines, a portion (wiring portion) outside the display area DA is referred to as a video signal connection line SCL (or also referred to as a lead-out wiring). Each of the plurality of video signal lines SL extends linearly in the Y direction. On the other hand, since the video signal connection line SCL is a wiring that connects the video signal line SL and the driver chip DRC1, it has a bent portion between the video signal line SL and the driver chip DRC1 as shown in FIG. ..

In the example shown in FIG. 3, there is a switch circuit (selection circuit) SWS between the video signal line SL and the video signal connection line SCL. The switch circuit SWS is, for example, a multiplexer circuit composed of a plurality of transistors, and outputs an input signal by selecting a video signal line SL for each color. The switch circuit SWS operates as a selection switch for selecting the type of video signal, such as a red signal, a green signal, or a blue signal. In other words, the switch circuit SWS is a selection circuit that selects the type of the video signal Spic (see FIG. 4) supplied to the video signal line SL. In this case, the number of video signal connection lines SCL connecting the switch circuit SWS and the driver chip DRC1 is smaller than the number of video signal lines SL. If the number of video signal connection lines SCL can be reduced by providing the switch circuit SWS in this way, the number of video signal connection lines SCL can be reduced between the driver chip DRC1 and the switch circuit SWS. When the switch circuit SWS is provided as shown in FIG. 3, the video signal line SL and the video signal connection line SCL can be distinguished as follows. That is, the portion (wiring portion) that connects the driver chip DRC1 and the switch circuit SWS is called a video signal connection line SCL. Further, the portion of the video line that overlaps the display area DA (wiring portion) to the portion connected to the switch circuit SWS (wiring portion) is referred to as a video signal line SL.

Further, as shown in FIG. 3, the switch circuit SWS is bent according to the shape of the side of the display area DA on the Y1 side. Specifically, since the switch circuit SWS is composed of a plurality of transistors, the array lines of the plurality of transistors constituting the switch circuit SWS are bent along the shape of the Y1 side side of the display area DA. .. As described above, since the switch circuit SWS is bent along the side of the display area DA on the Y1 side, the portion of the peripheral area SA on the Y1 side (the bent portions BEN3 and BEN4 shown in FIG. The area of the part EXT4) can be reduced.

Further, the display device DSP1 has a plurality of scanning signal lines GL and a drive circuit as a scanning signal output circuit that outputs scanning signals Gsi (see FIG. 6) input to the plurality of scanning signal lines GL. The drive circuit is provided on the substrate SUB1 in the peripheral region SA (see FIG. 1). The driver chip DRC1 is connected to the drive circuit via the control wiring GW. The plurality of scanning signal lines GL extend in the X direction and are arranged at intervals in the Y direction. Each of the plurality of pixels PX is partitioned by the scanning signal line GL in the Y direction. Therefore, the number of pixels PX arranged along the Y direction corresponds to the number of scanning signal lines GL. In the example shown in FIG. 1, n scanning signal lines GL are arranged in the order of scanning signal lines GL1, GL2, and GLn from one side in the Y direction toward the other side. Each of the plurality of scanning signal lines GL is drawn out to the peripheral region SA outside the display region DA and connected to the drive circuit. Further, the plurality of scanning signal lines GL intersect with the plurality of video signal lines SL. The scanning signal line GL includes the gate electrode GE of the transistor (pixel transistor) Tr1 as the pixel switch element PSW shown in FIG.

In FIG. 3, the area where the drive circuit GD is provided is schematically shown by surrounding it with a frame. The drive circuit includes a plurality of types of circuit parts. For example, as shown in FIG. 6, the drive circuit GD is connected to the shift register circuit GSR and the shift register circuit GSR, and is a switch circuit (scanning signal switch) that selects a potential to be supplied to the scanning signal line GL based on a control signal. Circuit) GSW and. Further, the drive circuit GD is connected to the driver chip DRC1 via the control wiring GW. The driver chip DRC1 supplies control signals such as a clock signal GCL and an enable signal ENB to the drive circuit GD via the control wiring GW.

In the example shown in FIG. 6, the clock signal GCL is transmitted to each of the plurality of shift register circuits GSR of the drive circuit GD via the clock line GWC. Further, the enable signal ENB is transmitted to each of the plurality of switch circuits GSW of the drive circuit GD via the enable line GWE. The enable line GWE is a potential supply line that supplies the potential as the scanning signal Gsi to the scanning signal line GL. In the example shown in FIG. 6, the scanning signal Gsi1 is supplied to the scanning signal line GL1, the scanning signal Gsi2 is supplied to the scanning signal line GL2, and the scanning signal Gsin is supplied to the scanning signal line GLn. As schematically shown in FIG. 6, each of the plurality of scanning signals Gsi is a pulse signal whose voltage level changes according to the timing of the clock signal GCL. Further, the start pulse signal GSP is transmitted to the shift register circuit GSR that is driven first among the plurality of shift register circuits GSR via the start pulse line GWS.

Further, in the example shown in FIG. 6, a set of a shift register circuit GSR and a switch circuit GSW constitutes a circuit block GDB1 or GDB2, and each of the circuit blocks GDB1 and GDB2 is connected to a scanning signal line GL. In FIG. 6, for the sake of clarity, one switch circuit GSW is connected to the non-loss shift register circuit GSR, and a scanning signal line GL is connected to each of the switch circuits GSW. However, there are various variations in the circuit configurations of the circuit blocks GDB1 and GDB2. For example, a plurality of switch circuits GSW may be connected to one shift register circuit GSR.

Further, a buffer circuit GBU is connected between the drive circuit GD and the driver chip DRC1. The buffer circuit GBU is a circuit that relays the potential supplied to the scanning signal line GL via the drive circuit GD. When the buffer circuit GBU is interposed in the transmission path of the control signal, the waveform of the gate signal supplied to the drive circuit GD is corrected by the buffer circuit GBU. As shown in FIG. 6, the buffer circuit GBU and the power supply circuit PSC are connected via a power supply wiring PL that supplies a power supply potential to the drive circuit GD. Specifically, the buffer circuit GBU and the power supply circuit PSC are connected via a wiring PLL to which a relatively high potential VDH is supplied and a wiring PLL to which a potential lower than the potential VDH is supplied. In the buffer circuit GBU, the waveform of the control signal such as the enable signal ENB is corrected by using the potential VDH and the potential VDC, and is output to the drive circuit GD. The power supply circuit PSC shown in FIG. 6 is formed on, for example, the wiring board FWB1. Further, as a modification, the power supply circuit PSC may be formed outside the display device DSP1 and may be connected to the buffer circuit GBU via the wiring board FWB1.

Further, in the example shown in FIG. 3, the drive circuit GD is arranged on both the X1 side, which is one side, and the X2 side, which is the other side, in the X direction. Specifically, in the X direction, the drive circuit (scanning signal line drive circuit, first drive circuit) GD1 is on the X1 side, and the drive circuit (scanning signal line drive circuit, second drive circuit) GD2 is on the X2 side. There is. Further, in the X direction, the display area DA is between the drive circuit GD1 and the drive circuit GD2. As shown in FIG. 3, a drive system in which drive circuits GD are connected to both ends of the scan signal line GL is called a double-sided drive system of the scan signal line GL. However, there are various variations in the layout of the drive circuit GD. For example, in the X direction shown in FIG. 3, the drive circuit GD may be arranged on either the X1 side or the X2 side. A drive system in which the drive circuit GD is connected to one end of the scanning signal line GL and the drive circuit GD is not connected to the other end is called a one-sided drive system of the scanning signal line GL. Further, for example, the buffer circuit GBU (see FIG. 6) may not be connected between the driver chip DRC1 and the drive circuit GD.

Further, as shown in FIG. 2, the display device DSP1 has a common electrode (second electrode) CE. Further, as shown in FIG. 4, the display device DSP1 has a common electrode drive circuit (also referred to as a common potential circuit) CD that drives the common electrode CE when the display device DSP1 displays an image. The common electrode CE is electrically connected to the common electrode drive circuit CD via a common wire CML. In the example shown in FIG. 4, the common electrode drive circuit CD is formed on the wiring board FWB1. The common electrode CE is an electrode to which a common potential is supplied to each of a plurality of pixels. Therefore, it is sufficient that one common electrode CE is provided so as to overlap with the display area DA. However, the common electrode CE divided into a plurality of parts may be provided so as to overlap with the display area DA.

The position where the common electrode drive circuit CD is formed has various modifications in addition to the embodiment shown in FIG. For example, the common electrode drive circuit CD may be formed on the driver chip DRC1. Further, for example, a form in which the common electrode drive circuit CD is arranged on the substrate SUB1 shown in FIG. 1 is also included in the embodiment in which the common electrode drive circuit CD is formed in the peripheral region SA. Further, for example, the common electrode drive circuit CD may be formed outside the display device DSP1 and connected to the wiring board FWB1.

As shown in FIG. 4, the pixel PX has a pixel switch element PSW and a pixel electrode PE. Further, in the example of the present embodiment, the plurality of pixels PX share the common electrode CE. The pixel switch element PSW includes, for example, a transistor Tr1 which is a thin film transistor (TFT). The pixel switch element PSW is electrically connected to the scanning signal line GL and the video signal line SL. Specifically, the source electrode SE of the transistor Tr1 which is the pixel switch element PSW is connected to the video signal line SL, and the drain electrode DE is connected to the pixel electrode PE. Further, the gate electrode GE of the transistor Tr1 is included in the scanning signal line GL. The drive circuit (see FIG. 3) controls the supply state of the video signal Spic to the pixel electrode PE by supplying an electric potential (scanning signal Gsi shown in FIG. 6) to the gate electrode GE and operating the pixel switch element PSW on and off. To do. In other words, the transistor Tr1 functions as a pixel switch element PSW that controls the potential supply to the pixel electrode PE. The pixel switch element PSW may be either a top gate type TFT or a bottom gate type TFT. Further, the material of the semiconductor layer of the pixel switch element PSW is, for example, polycrystalline silicon (polysilicon), but oxide semiconductor or amorphous silicon may also be used.

The pixel electrode PE faces the common electrode CE via the insulating film 14 (see FIG. 2). The common electrode CE, the insulating film 14, and the pixel electrode PE form a holding capacitance CS. During the display operation period in which the display image is formed based on the video signal, an electric field is formed between the pixel electrode PE and the common electrode CE based on the drive signal applied to each electrode. The liquid crystal molecules constituting the liquid crystal layer LQ, which is an electro-optical layer, are driven by an electric field formed between the pixel electrode PE and the common electrode CE. For example, in the display device DSP1 that utilizes the lateral electric field mode as in the present embodiment, as shown in FIG. 2, the substrate SUB1 is provided with the pixel electrode PE and the common electrode CE. The liquid crystal molecules constituting the liquid crystal layer LQ are rotated by using an electric field formed between the pixel electrode PE and the common electrode CE (for example, an electric field in the fringe electric field that is substantially parallel to the main surface of the substrate). ..

That is, during the display operation period, each of the pixel electrode PE and the common electrode CE operates as a drive electrode for driving the liquid crystal layer LQ, which is an electro-optical layer. In other words, each of the plurality of pixel electrode PEs is a first electrode that drives the electro-optical layer. Further, each of the common electrodes CE is a second electrode for driving the electro-optical layer.

As shown in FIG. 2, the substrate SUB1 and the substrate SUB2 are bonded to each other in a state of being separated from each other. The liquid crystal layer LQ is enclosed between the substrate SUB1 and the substrate SUB2. The substrate SUB 1 has an insulating substrate 10 having light transmittance such as a glass substrate or a resin substrate. Further, the substrate SUB1 has a plurality of conductor patterns on the side of the insulating substrate 10 facing the substrate SUB2. The plurality of conductor patterns include a plurality of scanning signal lines GL, a plurality of video signal lines SL, a plurality of common line CMLs, a plurality of common electrodes CE, and a plurality of pixel electrodes PE. In addition, an insulating film is interposed between each of the plurality of conductor patterns. The insulating film arranged between the adjacent conductor patterns and insulating the conductor patterns from each other includes an insulating film 11, an insulating film 12, an insulating film 13, an insulating film 14, and an alignment film AL1. In FIG. 2, one scan signal line GL, one common electrode CE, and one common line CML are shown.

Each of the plurality of conductor patterns described above is formed in a plurality of laminated wiring layers. In the example shown in FIG. 2, the common electrode CE and the pixel electrode PE are formed in different layers, and three wiring layers are provided below the layer in which the common electrode CE is formed. Of the three wiring layers formed on the insulating substrate 10, the scanning signal line GL is mainly formed in the first wiring layer WL1 provided on the most insulating substrate 10 side. The conductor pattern formed on the wiring layer WL1 is made of a metal such as chromium (Cr), titanium (Ti), or molybdenum (Mo) or an alloy thereof.

The insulating film 11 is formed on the wiring layer WL1 and the insulating substrate 10. The insulating film 11 is a transparent insulating film made of, for example, silicon nitride or silicon oxide. In addition to the scanning signal line GL, a gate electrode of a pixel switch element, a semiconductor layer, and the like are formed between the insulating substrate 10 and the insulating film 11.

A second wiring layer WL2 is formed on the insulating film 11. A video signal line SL is mainly formed in the wiring layer WL2. The wiring layer (two wiring layers) WL2 is formed of a material having a resistivity lower than that of the wiring layer (first wiring layer) WL1. The conductor pattern formed on the wiring layer WL2 is composed of, for example, a multi-layered metal film in which aluminum (Al) is sandwiched between molybdenum (Mo), titanium (Ti), and the like. It is preferable that the wiring material of the wiring layer WL2 has a lower specific resistance than the wiring material of the wiring layer WL1. Further, the source electrode and the drain electrode of the pixel switch element are also formed on the insulating film 11. In the example shown in FIG. 2, the video signal line SL extends in the Y direction. The insulating film 12 is formed on each of the video signal line SL and the insulating film 11. The insulating film 12 is made of, for example, an acrylic photosensitive resin.

Further, in the example shown in FIG. 2, the wiring layer WL3 of the third layer is formed on the insulating film 12. A common wire CML is mainly formed in the wiring layer WL3. Similar to the wiring layer WL2, the conductor pattern formed on the wiring layer WL3 is composed of, for example, a multi-layered metal film in which aluminum (Al) is sandwiched between molybdenum (Mo), titanium (Ti), and the like. In the example shown in FIG. 2, the common line CML extends in the Y direction. The insulating film 13 is formed on each of the common wire CML and the insulating film 12. The insulating film 13 is made of, for example, an acrylic photosensitive resin. Note that FIG. 2 shows an example in which wirings such as a scanning signal line GL, a video signal line SL, and a common line CML are arranged in three wiring layers. However, the number of layers of the wiring layer is not limited to the above, and there are various modifications. For example, the wiring layer WL3 shown in FIG. 2 may not be provided. In this case, the common wire CML may be formed in the same layer as the layer on which the common electrode CE is formed, for example.

Although FIG. 2 shows an enlarged cross section of the display region DA shown in FIG. 1, each of the wiring layers WL1, WL2, and WL3 shown in FIG. 2 is also arranged in the peripheral region SA shown in FIG. The video signal connection line SCL, control wiring GW, and power supply wiring PL shown in FIG. 3 are formed in one or more of the wiring layers WL1, WL2, and WL3. Further, each of the plurality of circuits arranged in the peripheral region SA, such as the switch circuit SWS shown in FIG. 3, is formed in one or a plurality of wiring layers among the wiring layers WL1, WL2, and WL3.

As shown in FIG. 2, the common electrode CE is formed on the insulating film 13. The common electrode CE is preferably a transparent conductive material such as ITO (Indium tin oxide) or IZO (Indium Zinc Oxide). When the display device is a display device such as TN mode or VA mode as the vertical electric field mode, the common electrode CE may be formed on the substrate SUB2. Further, in the cross section shown in FIG. 2, an insulating film 13 is interposed between the common electrode CE and the common wire CML. However, as shown in FIG. 3, a part of the common wire CML and a part of the common electrode CE are electrically connected. Further, the common electrode CE may be made of a metal material as long as it is a reflective display device that utilizes reflection of external light.

The insulating film 14 is formed on the insulating film 13 and the common electrode CE. The pixel electrode PE is formed on the insulating film 14. In a plan view, each pixel electrode PE is located between two video signal lines SL adjacent to each other, and is arranged at a position facing the common electrode CE. The pixel electrode PE is preferably a transparent conductive material or metal material such as ITO or IZO. The alignment film AL1 covers the pixel electrode PE and the insulating film 14.

On the other hand, the substrate SUB2 has an insulating substrate 20 having light transmittance such as a glass substrate or a resin substrate. Further, the substrate SUB2 has a light-shielding layer BM which is a light-shielding film, color filters CFR, CFG and CFB, an overcoat layer OCL, an alignment film AL2, and a conductive film CDF on the side of the insulating substrate 20 facing the substrate SUB1. Has.

The conductive film CDF is arranged on the plane opposite to the plane facing the liquid crystal layer LQ in the plane of the insulating substrate 20. The conductive film CDF is made of a transparent conductive material such as ITO or IZO. The conductive film CDF functions as a shield layer that suppresses the influence of electromagnetic waves from the outside on the liquid crystal layer LQ and the like. Further, when the method for driving the liquid crystal layer LQ is a longitudinal electrolysis mode such as TN mode or VA mode, an electrode is provided on the substrate SUB2, and this electrode also functions as a shield layer, so that the conductive film CDF can be omitted. ..

The display device DSP1 has an optical element OD1 and an optical element OD2. The optical element OD1 is arranged between the insulating substrate 10 and the backlight unit BL. The optical element OD2 is arranged above the insulating substrate 20, that is, on the side opposite to the substrate SUB1 with the insulating substrate 20 interposed therebetween. The optical element OD1 and the optical element OD2 each include at least a polarizing plate, and may include a retardation plate if necessary.

<Display device plan shape and circuit layout>
Next, the relationship between the planar shape of the display device of the present embodiment and the circuit layout will be described. FIG. 7 is a circuit diagram schematically showing the factors of the load applied to each of the plurality of pixels shown in FIG. Further, FIG. 8 is an enlarged plan view showing details of the circuit configuration on the upper side of the display device shown in FIG.

In FIG. 7, the sheet-shaped common electrode CE is shown in order to explicitly show that the common electrode CE is arranged across the plurality of pixel electrode PEs. In FIG. 8, for the sake of easy viewing of the circuit layout of the drive circuits GD1 and GD2, the enable line GWE for transmitting the enable signal is typically shown among the plurality of control wiring GWs shown in FIG. Further, in FIG. 8, the circuit blocks GDB1 and GDB2 shown in FIG. 6 are shown by squares. Each of the circuit blocks GBA1, GBB1, GBC1, GBD1, and GBE1 shown in FIG. 8 is included in a plurality of circuit blocks GDB1 constituting the drive circuit GD1. Further, each of the circuit blocks GBA2, GBB2, GBC2, GBD2, and GBE2 is included in a plurality of circuit blocks GDB2 constituting the drive circuit GD2. The circuit blocks GBA1 and GBA2, GBB1 and GBB2, GBC1 and GBC2, GBD1 and GBD2, and GBE1 and GBE2 are each connected to the same scanning signal line GL. In FIG. 8, for the sake of clarity, each of the plurality of scanning signal lines GL is indicated by a long-dotted line, and each of the plurality of video signal lines SL is indicated by a dotted line. Further, in FIG. 8, in each of the enable lines GWE1 and GWE2, the portion formed in the wiring layer WL1 shown in FIG. 2 is shown by a solid line, and the portion formed in the wiring layer WL2 or the wiring layer WL3 is shown by a dotted line. .. Further, in FIG. 8, among the plurality of pixel PXs, one pixel PXA connected to the scanning signal line GLA and one pixel PXE connected to the scanning signal line GLE are schematically shown by a square.

As shown in FIG. 1, in the display device DSP1 of the present embodiment, the planar shape of the display area DA and the outer shape of the peripheral area SA are each "atypical". In the example shown in FIG. 1, the display device DSP1 is also used as a rearview mirror for checking the rear of an automobile, and the planar shape of the display area DA and the outer shape of the peripheral area SA are trapezoidal, respectively. Further, in a plan view, the shape of the light-shielding layer BM arranged around the display area DA is as follows. That is, the light-shielding layer BM has an extending portion (first extending portion) EXT1 and an extending portion (second extending portion) EXT2 extending in the Y direction, respectively. Further, the light-shielding layer BM has a bent portion (first bent portion) BEN1 and a bent portion (second bent portion) BEN2 located between the extending portion EXT1 and the extending portion EXT2. Further, the extending portion EXT1 is connected to the bent portion BEN1, and the extending portion EXT2 is connected to the bent portion BEN2. Further, the length of the extending portion EXT2 is longer than the length of the extending portion EXT1. Further, in the example shown in FIG. 1, the light-shielding layer BM has an extending portion (third extending portion) EXT3 between the bent portion BEN1 and the bent portion BEN2, and the extending portion EXT3 is in the Y direction and X. It has a side (inner end side) extending along the direction T1 that is inclined with respect to each of the directions. The direction of inclination with respect to the Y direction is a direction forming an angle other than a right angle and a parallel with respect to the Y direction. Similarly, the direction of inclination with respect to the X direction is a direction forming an angle other than right angle and parallel with respect to the X direction.

The bent portion means a portion where the extending direction changes. As shown in FIG. 1, the bent portion includes not only a curved portion but also a bent portion. Further, when the curve is curved, the amount of change (angle) in the extending direction due to the curved portion / the total length of the curved portion can be defined as the curvature.

Further, in the example shown in FIG. 1, the light-shielding layer BM has a bent portion (third bent portion) BEN3 on the opposite side of the bent portion BEN1 via the extending portion EXT1. Further, the light-shielding layer BM has a bent portion (fourth bent portion) BEN4 on the opposite side of the bent portion BEN2 via the extending portion EXT2. Further, the light-shielding layer BM has an extending portion (fourth extending portion) EXT4 between the bent portion BEN3 and the bent portion BEN4, and the extending portion EXT4 is inclined with respect to each of the Y direction and the X direction. It has a side (inner end side) extending along the direction T2. In the example of this embodiment, since the display area DA is trapezoidal, the directions T1 and T2 are not parallel to each other. Further, in the example shown in FIG. 1, the direction T2 and the direction T3 are parallel to each other. The expression "direction T2 and direction T3 are parallel to each other" can be regarded as substantially parallel, although not strictly parallel due to the influence of processing accuracy, etc., in addition to the case where both are strictly parallel. Including things. In FIG. 1, in order to distinguish from the bent portion BEN1 and the bent portion BEN2 on the Y2 side in the Y direction, the bent portion BEN3 is described as the third bent portion, and the bent portion BEN4 is described as the fourth bent portion. However, as shown in FIG. 17, which will be described later, focusing on the portion on the Y1 side, the bent portion BEN3 can be read as the first bent portion, and the bent portion BEN4 can be read as the second bent portion. Similarly, although the extended portion EXT4 is described as the fourth extended portion, it can be read as the third extended portion.

From the viewpoint of improving the quality of the image displayed on the display device DSP1, the value of the load applied to each of the plurality of pixels PX arranged in the display area DA (for example, the impedance value due to parasitic capacitance, wiring resistance, etc.) ) Is preferably made uniform in the plane overlapping the display area DA. If the in-plane distribution of the load value with respect to the pixel PX becomes non-uniform in the display area DA, it causes deterioration of image quality such as display unevenness.

The load factors applied to each of the plurality of pixels PX include the parasitic capacitances C1 to C5 shown in FIG. 7, the wiring resistance of the scanning signal line GL, and the wiring resistance of the video signal line SL. The parasitic capacitance C1 is the parasitic capacitance between the scanning signal line GL and the video signal line SL. The parasitic capacitance C2 is the parasitic capacitance between the source electrode and drain electrode of the transistor Tr1 and the video signal line SL. The parasitic capacitance C3 is the parasitic capacitance between the source electrode and the drain electrode of the transistor Tr1 and the scanning signal line GL. Further, the parasitic capacitance C4 is the parasitic capacitance between the scanning signal line GL and the common electrode CE. The parasitic capacitance C5 is the parasitic capacitance between the video signal line SL and the common electrode CE.

First, among the load factors given to each of the plurality of pixels PX, the load mainly caused by the wiring resistance of the scanning signal line GL will be examined. As shown in FIG. 8, each of the plurality of scanning signal lines GL is arranged so as to cross the display area DA along the X direction. When the shape of the display area DA is not square or rectangular, the plurality of scanning signal lines GL include those having different lengths (extending distances) from each other. For example, in the example shown in FIG. 8, the scanning signal line GLA and the scanning signal line GLE have different lengths from each other. Specifically, the scanning signal line GLA is connected to the circuit block GBA1 superposed on the extending portion EXT3 and the circuit block GBA2 superimposing on the bending portion BEN2. In other words, a part of the scanning signal line GLA overlaps with the extending portion EXT3, and the other part overlaps with the bending portion BEN2. Further, the scanning signal line GLE is connected to the circuit block GBE1 superposed on the extending portion EXT1 and the circuit block GBE2 superimposing on the extending portion EXT2. In other words, a part of the scanning signal line GLE is superposed on the extending portion EXT1, and the other part is superposed on the extending portion EXT2. In this case, the length (extended distance) of the scanning signal line GLE is longer than the length of the scanning signal line GLA.

Here, among the loads applied to the pixel PXA located near the center of the scanning signal line GLA and the pixel PXE located near the center of the scanning signal line GLE shown in FIG. 8, the wiring of the scanning signal line GL. The load caused by the resistance is as follows. That is, the wiring resistance of the scanning signal line GL increases in proportion to the path distance from the end of the scanning signal line GL to the gate electrode GE (FIG. 4) of the pixel PX. That is, the wiring resistance of the scanning signal line GL increases in proportion to the path distance from the end of the scanning signal line GL to the gate electrode GE (FIG. 4) of the pixel PX. Further, as shown in FIG. 7, the wiring resistance of the scanning signal line GL increases under the influence of parasitic capacitance as the number of times of crossing with the transistor Tr1 and the video signal line SL of each pixel increases. Therefore, in order to improve the display quality, it is preferable to reduce the difference in time constant corresponding to each of the plurality of pixels PX.

Therefore, in the present embodiment, a plurality of wiring resistances of the enable line GWE that supplies the potential as the scanning signal Gsi (see FIG. 6) to the scanning signal line GL via the drive circuit GD shown in FIG. 6 are adjusted. The load applied to the pixel PX (see FIG. 8) is made uniform. More specifically, as described with reference to FIG. 2, the display device DSP1 has a wiring layer (first wiring layer) WL1 and a wiring layer (second wiring layer) formed of a material having a resistivity lower than that of the wiring layer WL1. ) WL2 and. The conductor pattern formed on the wiring layer WL1 is made of a metal such as chromium (Cr), titanium (Ti), or molybdenum (Mo) or an alloy thereof. Further, the conductor pattern formed on the wiring layer WL2 is composed of, for example, a metal film having a multi-layer structure in which aluminum (Al) is sandwiched between molybdenum (Mo), titanium (Ti) and the like. In this case, the resistivity (specific resistance) of the wiring layer WL1 is higher than the specific resistance of the wiring layer WL2. As shown in FIG. 2, the scanning signal line GL is formed in the wiring layer WL1. Then, in the region superposed on the extending portion EXT3, the enable line (first potential supply line) GWE1 passes through the wiring layer WL1 and the wiring layer WL2.

It is preferable that the enable line GWE1 does not pass through the wiring layer WL1 only from the viewpoint of reducing the wiring resistance of the enable line GWE1. For example, when the enable line GWE1 passes only through the wiring layer WL2, the load applied to the pixel PX due to the wiring resistance of the enable line GWE1 can be made substantially negligible. However, when a part of the enable line GWE1 passes through the wiring layer WL1, the value of the wiring resistance of the enable line GWE1 can be adjusted according to the wiring path distance of the portion passing through the wiring layer WL1. For example, in the example shown in FIG. 8, in the wiring path of the enable line GWE1 from the control circuit CTC to the circuit block GBA1, the enable line GWE1 is wired at a plurality of portions (parts indicated by solid lines extending along the X direction). Via layer WL1.

Here, among the enable lines GWE1 that supply the potential to the scanning signal line GLA, the total value of the wiring path distances of the portions that pass through the wiring layer WL1 is, for example, the enable line GWE1 that supplies the potential to the scanning signal line GLE. , It is longer than the wiring path distance of the portion passing through the wiring layer WL1. In this case, the wiring resistance of the enable line GWE1 that supplies the potential to the scanning signal line GLA is larger than the wiring resistance of the enable line GWE1 that supplies the potential to the scanning signal line GLE. Further, when a part of the enable line GWE1 passes through the wiring layer WL1, the load factor applied to each of the pixel PXA and the pixel PXE includes the wiring resistance of the enable line GWE1. Then, in the scanning signal Gsi of the pixel PXA and the pixel PXE, the difference in time constant can be reduced by comprehensively considering the influence of the wiring resistance of the scanning signal line GL, the wiring resistance of the enable wiring GWE1, and the parasitic capacitance C1. it can. In other words, it is possible to reduce the in-plane difference of the time constant with respect to each of the plurality of pixels PX arranged in the display area DA. That is, according to the present embodiment, by adjusting the wiring resistance of the enable wiring GWE1, the variation in the in-plane distribution of the load due to the wiring resistance of the scanning signal line GL and the parasitic capacitance C1 is reduced. As a result, the quality of the image displayed on the display device DSP1 can be improved.

Further, the drive circuit GD1 has a circuit block (first A circuit block) GBA1 circuit block (first B circuit block) GBB1, a circuit block (first C circuit block) GBC1, and a circuit block (first D circuit block) GBD1. There is. In the example shown in FIG. 8, the circuit block GBA1 and the circuit block GBB1 are superimposed on the extending portion EXT3, and the circuit block GBC1 and the circuit block GBD1 are superimposed on the bending portion BEN1. The enable line GWE1 passes through the wiring layer WL1 at a distance (first distance) D1 between the circuit block GBA1 and the circuit block GBB1. Further, the enable line GWE1 passes through the wiring layer WL1 at a distance (first distance) D2 between the circuit block GBC1 and the circuit block GBD1. The distance D2 is shorter than the distance D1.

In the example shown in FIG. 8, the enable line GWE1 passes through the wiring layer WL1 at a distance D4 between the circuit block GDB1 at the end of the drive circuit GD1 and the circuit block GBA1 adjacent thereto. In the example shown in FIG. 8, the distance D4 is shorter than the distance D1. However, since the length of the distance D4 is determined according to the space of the extending portion EXT3, the distance D4 and the distance D1 may be equal to each other.

Further, the drive circuit GD2 has a circuit block (second A circuit block) GBA2 and a circuit block (second B circuit block) GBB2. In the example shown in FIG. 8, the circuit block GBA2 and the circuit block GBB2 overlap with the bent portion BEN2. The enable line GWE2 passes through the wiring layer WL1 at a distance (third distance) D3 between the circuit block GBA2 and the circuit block GBB2. The distance D1 is longer than the distance D3.

Each of the plurality of scanning signal lines GL extends along the X direction. Therefore, if the portion of the enable lines GWE1 and GWE2 formed in the wiring layer WL1 extends along the X direction, a plurality of signal transmission paths (wiring path distance including the enable line GWE and the scanning signal line GL). It is easy to align the resistance values of. The length of the extending portion EXT3 in the X direction is longer than the length of the bent portion BEN1 and the bent portion BEN2 in the X direction. Therefore, in the region superimposing on the extending portion EXT3, the wiring length in the X direction can be lengthened as compared with the region superimposing on the bent portions BEN1 and BEN2. Therefore, as shown in FIG. 8, when the distance D1 is longer than the distance D2 and the distance D3, it is easy to align the resistance values of the plurality of signal transmission paths.

Further, in the example shown in FIG. 8, the enable line (second potential supply line) GWE2 passes through the wiring layer WL1 and the wiring layer WL2 in the region overlapped with the bent portion BEN2. In this case, by adjusting the wiring resistance of the enable wiring GWE2, it is possible to reduce the variation in the in-plane distribution of the load due to the wiring resistance of the scanning signal line GL and the parasitic capacitance C1. However, since the extending portion EXT3 has a larger area than the bent portion BEN2, the distance via the wiring layer WL1 can be lengthened. Therefore, the effect of suppressing the variation in the time constant due to a part of the enable line passing through the wiring layer WL1 is relatively higher in the enable line GWE1. However, when each of the enable line GWE1 and the enable line GWE2 passes through both the wiring layer WL1 and the wiring layer WL2, the effect of suppressing the variation in the time constant is particularly high.

Further, from the viewpoint of reducing the in-plane difference of the load applied to the plurality of pixels PX as in the present embodiment, the enable line is connected to the scanning signal line GL having a relatively low wiring resistance. In some cases, it may be preferable that a part of GWE1 or GW2 does not pass through the wiring layer WL1. For example, in the example shown in FIG. 8, the enable line GWE1 passes through the wiring layer WL2 and does not pass through the wiring layer WL1 in the region overlapped with the extending portion EXT1. Further, in the region overlapped with the extending portion EXT2, the enable line GWE2 passes through the wiring layer WL2 and does not pass through the wiring layer WL1. The lengths of the plurality of scanning signal lines GL connecting the extending portion EXT1 and the extending portion EXT2 are the same in design (however, there are some differences due to processing accuracy and the like). The length of each of the plurality of scanning signal lines GL connecting the extending portion EXT1 and the extending portion EXT2 is the longest among the plurality of scanning signal line GLs included in the display device DSP1. For example, as in the case of the scanning signal line GL, the length of a plurality of scanning signal lines GL in which one end overlaps with the extending portion EXT1 and the other end overlaps with the extending portion EXT2 has one end. It is longer than the length of the scanning signal line GL (for example, the scanning signal line GLA) that overlaps with the extending portion EXT3. That is, the wiring resistance of the scanning signal line GLE is larger than the wiring resistance of the scanning signal line GLA. Therefore, in the region overlapping the extending portions EXT1 and EXT2, even if the wiring resistance of the path for supplying the potential (enabled lines GWE1 and GWE2) is increased, the effect of reducing the in-plane difference of the time constant cannot be obtained. Further, if the overall wiring resistance of the enable lines GWE1 and GWE2 is large, the load applied to each of the plurality of pixels PX becomes large. Therefore, from the viewpoint of increasing the adjustment margin of the wiring resistance of the enable lines GWE1 and GWE2, the enable lines GWE1 and GWE2 use the wiring layer WL1 in the area superposed on the extending portion EXT1 and the area superposed on the extending portion EXT2. It is preferable not to go through.

Further, the drive circuit GD2 has a circuit block (second C circuit block) GBC2 and a circuit block (second D circuit block) GBD2. The circuit block GBC1 and the circuit block GBC2 are connected to the same scanning signal line GLC. Further, the circuit block GBD1 and the circuit block GBD2 are connected to the same scanning signal line GLD. Here, the enable line GWE1 passes through the wiring layer WL1 and the wiring layer WL2 between the circuit block GBC1 and the circuit block GBD1. On the other hand, the enable line GWE2 passes between the circuit block GBC2 and the circuit block GBD2 via the wiring layer WL2 and does not pass through the wiring layer WL1. In the example shown in FIG. 8, the circuit block GBC2 is superimposed on the bent portion BEN2, and the circuit block GBD2 is superimposed on the extending portion EXT2. The circuit block GBC2 is arranged in the vicinity of the extending portion EXT2, and is arranged on an extension line of the arrangement line of a plurality of circuit blocks GDB2 arranged at positions overlapping with the extending portion EXT2. In this case, if the enable line GWE1 passes through the wiring layer WL1 and the wiring layer WL2 between the circuit block GBC1 and the circuit block GBD1, the enable line GWE2 becomes the pixel PX even if it does not pass through the wiring layer WL1. It is possible to adjust the applied load.

Further, a part of the enable line GWE1 overlaps with the extending portion EXT1. The enable line GWE1 passes through the wiring layer WL2 and does not pass through the wiring layer WL1 in the region overlapped with the extending portion EXT1. Thereby, for example, the load applied to the pixel PXE connected to the scanning signal line GLE can be reduced.

However, even when a part of the enable lines GWE1 and GWE2 passes through the wiring layer WL1 in the area superposed on the extending portion EXT1 and the region superposed on the extending portion EXT2, the wiring layer WL1 is restricted due to space restrictions. The distance via is not long. Therefore, as a modification with respect to FIG. 8, a part of the enable lines GWE1 and GWE2 may pass through the wiring layer WL1 in the region superposed on the extending portion EXT1 and the region superposed on the extending portion EXT2.

Further, in the present embodiment, drive circuits are connected to both ends of each of the plurality of scanning signal lines GL. In other words, each of the plurality of scanning signal lines GL is driven by a double-sided drive system. In this way, when a plurality of scanning signal lines GL are driven by the two-sided drive method, if a part of the plurality of scanning signal lines GL is driven by the one-side drive method, the plurality of scanning signal lines This causes the in-plane distribution of the load applied to the GL to become uneven. That is, from the viewpoint of improving the image quality, it is preferable that all the scanning signal lines GL are driven by the double-sided drive method.

If the plane shape of the display area DA is square or rectangular, it is easy to make the lengths of the plurality of scanning signal lines GL uniform and the lengths of the plurality of video signal lines SL uniform. Therefore, it is relatively easy to make the value of the load applied to each of the plurality of pixels PX arranged so as to overlap the display area DA substantially constant. However, in the case of the display device DSP1 having the irregular display area DA as in the present embodiment, the in-plane distribution of the load values applied to each of the plurality of pixels PX tends to be non-uniform.

Therefore, in the case of the display device DSP1 of the present embodiment, as shown in FIG. 3, the drive circuit GD1 straddles the region overlapping with the bent portion BEN1 (see FIG. 1), and the bent portion BEN2 (see FIG. 2). It extends to the vicinity. In other words, in plan view, the bent portion BEN2 is between the end portion of the drive circuit GD1 and the end portion of the drive circuit GD2. As a result, the drive circuit GD is connected to both ends of the scanning signal line GL1 arranged on the Y2 side most in the Y direction among the plurality of scanning signal lines GL. In other words, each of the plurality of scanning signal lines GL including the scanning signal line GL1 is driven by the two-sided driving method. As a result, it is possible to suppress deterioration in image quality caused by driving a part of the plurality of scanning signal lines GL by the one-side drive method.

The above configuration can also be expressed as follows using the clock lines GWC1 and GWC2 shown in FIG. FIG. 9 is an enlarged plan view showing an example of a wiring layout for supplying a clock signal to a drive circuit in the same portion as the display device shown in FIG. In FIG. 9, for the sake of easy viewing of the circuit layout of the drive circuits GD1 and GD2, the clock line GWC for transmitting the clock signal is typically shown among the plurality of control wiring GWs shown in FIG.

As shown in FIG. 9, that is, the display device DSP1 connects the control circuit CTC and the drive circuit GD1, and the clock line (first clock) to which the clock signal (first clock signal) GCL1 (see FIG. 6) is supplied. Line) GWC1 is connected to the control circuit CTC and the drive circuit GD1, and a clock line (second clock line) GWC2 to which a clock signal (second clock signal) GCL2 (see FIG. 6) is supplied is provided. .. Further, in a plan view, the bent portion BEN1 is superimposed on the clock line GWC1, and the bent portion BEN2 is located between the end portion of the clock line GWC1 and the end portion of the clock line GWC2. As shown in FIG. 9, the end portion of the clock line GWC1 is between the bent portion BEN1 and the bent portion BEN2. In the example shown in FIG. 9, the end portion of the clock line GWC2 overlaps with the bent portion BEN2, and the end portion of the clock line GWC1 does not overlap with the bent portion BEN2. On one hypotenuse of the display device DSP1 having a trapezoidal planar shape, that is, the side along the extending portion EXT3 shown in FIG. 9, the drive circuit GD1 can be arranged along the hypotenuse. Thereby, the two-sided drive system of the scanning signal line GL can be applied to the terminal portion of the drive circuit GD1 and the terminal portion of the drive circuit GD2, that is, the terminal portion of the clock line GWC1 and the terminal portion of the clock line GWC2.

Next, among the load factors applied to each of the plurality of pixels PX shown in FIG. 7, the load caused by the parasitic capacitance C1 (see FIG. 7) between the scanning signal line GL and the video signal line SL will be examined. FIG. 10 is an enlarged plan view of a display device which is a modification of FIG. 8. Further, FIG. 11 is an enlarged plan view showing a circuit layout around the circuit block shown in FIG. Further, FIG. 12 is an enlarged plan view showing a modification of FIG. 11. In FIGS. 11 and 12, in order to distinguish the boundary between the wiring portion (main wiring portion) GLPM and the wiring portion (secondary wiring portion) GLPS of the scanning signal line GL, the scanning signal line GL is shown with hatching. .. Although the wiring portion GLPM and the wiring portion GLPS are provided with different types of hatching, the wiring portion GLPM and the wiring portion GLPS are continuously formed on the wiring layer WL1 (see FIG. 2) with the same conductive material. It is a conductor pattern.

When the shape of the display area DA is not square or rectangular, the plurality of scanning signal lines GL include those having different numbers of intersecting video signal lines SL. For example, in the example shown in FIG. 8, in a plan view, the number of video signal lines SL where the scanning signal lines GLA intersect in the display area DA and the video signal line SL where the scanning signal lines GLE intersect in the display area DA. The number is different from each other. Specifically, the number of video signal lines SL where the scanning signal lines GLA intersect is smaller than the number of video signal lines SL where the scanning signal lines GLE intersect in the display area DA. In other words, the number of parasitic capacitances C1 (see FIG. 7) connected to the signal transmission path for transmitting the scan signal Gsi (see FIG. 6) to the pixel PXE shown in FIG. 8 is the signal for transmitting the scan signal Gsi to the pixel PXA. It is larger than the number of parasitic capacitances C1 connected to the transmission path. Therefore, when only the parasitic capacitance C1 shown in FIG. 7 is taken into consideration, the load applied to the pixel PXE is larger than the load applied to the pixel PXA. As described above, in order to improve the display quality, it is preferable to reduce the in-plane difference of the load applied to each of the plurality of pixels PX.

Therefore, in the display device DSP2 shown in FIG. 10, a part of the plurality of video signal lines SL extends over the display area DA to the area where it overlaps with the extending portion EXT3 of the peripheral area SA. Then, in the extending portion EXT3, the scanning signal line GL and the video signal line SL intersect. In this case, the number of video signal lines SL at which the scanning signal line GL (for example, the scanning signal line GLA) superposed on the extending portion EXT3 intersects is larger than that of the display device DSP1 shown in FIG. That is, among the loads applied to the pixels PXA connected to the scanning signal line GLA, the load corresponding to the parasitic capacitance C1 shown in FIG. 7 increases. As a result, it is possible to reduce the in-plane difference of the load applied to each of the plurality of pixels PX.

Specifically, as shown in FIG. 11, in a plan view, the scanning signal line GLA is a wiring portion (main wiring portion) between the drive circuit (first drive circuit) GD1 and the display area DA and in the display area DA. It has a GLPM and a wiring portion (sub-wiring portion) GLPS which is connected to the wiring portion GLPM and is located between the drive circuit GD1 and the outer edge of the peripheral region SA. In a plan view, the wiring portion GLPS intersects the video signal line SL. The wiring portion GLPS is on an extension line of the wiring portion GLPM and extends along the X direction. In the example shown in FIG. 11, each of the plurality of scanning signal lines GL has a wiring unit GLPM and a wiring unit GLPS. Further, each of the plurality of video signal lines SL has a wiring unit (main wiring unit) SLPM in the display area DA in a plan view and a wiring unit (sub wiring unit) SLPS in a peripheral region SA in a plan view. doing. Then, in the peripheral region SA, specifically, in the region overlapping with the extending portion EXT3, the wiring portion GPLS of the scanning signal line GL and the wiring portion SLPS of the plurality of video signal lines SL intersect with each other.

Parasitic capacitance C1 (see FIG. 7) is assigned to each portion of the peripheral region SA where the scanning signal line GLA and the plurality of video signal lines SL intersect. Each of the parasitic capacitances C1 at the plurality of intersecting portions is included as a load applied to the pixel PXA (see FIG. 10) connected to the scanning signal line GLA. As a result, the difference between the load applied to the pixel PXE and the load applied to the pixel PXA shown in FIG. 10 can be reduced.

Further, in the example shown in FIG. 10, the plurality of scanning signal lines GL including the scanning signal line GLA intersect with the video signal line SL in the region overlapping with the bent portion BEN2. In this case, the number of video signal lines SL where the scanning signal lines GLA intersect in the peripheral region can be further increased. However, on the extension line of the scanning signal line GLA, the length of the region superimposing on the extending portion EXT3 is longer than the length of the region superimposing on the bending portion BEN2. Therefore, the number of video signal lines SL intersecting with the scanning signal line GLA is larger in the region overlapping with the extending portion EXT3 than in the region overlapping with the bending portion BEN2.

By the way, when the wiring portion GLPS of the scanning signal line GL and the wiring portion SLPS of the video signal line SL are arranged in the peripheral area SA as in the display device DSP2, the control wiring GW arranged in the peripheral area SA (FIG. 6). Depending on the layout of (see), the control wiring GW and the scanning signal line GL, or the control wiring GW and the video signal line SL may intersect. However, it is preferable that each of the scanning signal line GL and the video signal line SL and the control wiring GW do not intersect in a plan view. For example, in the example shown in FIG. 11, the wiring portion GLPS of the scanning signal line GL does not intersect the enable line GWE1 in a plan view. Further, the wiring portion SLPS of the video signal line SL does not intersect the enable line GWE1 in a plan view. Although not shown in FIG. 11, it is preferable that each of the clock line GWC and the start pulse line GWS shown in FIG. 6 does not intersect the scanning signal line GL and the video signal line SL in the peripheral region SA.

Further, as shown in FIG. 10, the plurality of scanning signal lines GL include those that do not have the wiring portion GLPS (see FIG. 11). For example, the scanning signal line GLE shown in FIG. 10 does not have a wiring portion GLPS. In a plan view, the number of video signal lines SL where the scanning signal lines GLA intersect in the display area DA is smaller than the number of video signal lines SL where the scanning signal lines GLE intersect. In the case of the display device DSP2, the wiring portion GLPS is selectively provided for the scanning signal line GL in which the number of intersecting video signal lines SL is relatively small among the plurality of scanning signal line GLs. In particular, the scanning signal line GLE has one end superposed on the extending portion EXT1 and the other end superposed on the extending portion EXT2. Therefore, the number of video signal lines SL where the scanning signal lines GLE intersect in the display area DA is larger than that of the other scanning signal lines GL. From the viewpoint of reducing the in-plane difference of the load applied to the plurality of pixels PX, the scanning signal line GL that maximizes the number of intersecting video signal lines SL in the display area DA, such as the scanning signal line GLE. In this case, it is preferable not to have the wiring portion GLPS.

The display device DSP2 shown in FIGS. 10 and 11 is the same as the display device DSP1 shown in FIG. 8 except that the video signal line SL and the scanning signal line intersect in the peripheral region SA. Therefore, overlapping description of the common parts of the display device DSP1 and the display device DSP2 will be omitted.

Further, when one scanning signal line GL and one video signal line SL intersect at a plurality of points in the peripheral region SA as in the display device DSP3 shown in FIG. 12, the scanning signal line GL is assigned to one scanning signal line GL. The number of parasitic capacitances C1 can be further increased. The display device DSP3 differs from the display device DSP2 shown in FIG. 11 in the shape of the wiring portion GLPS. In the case of the display device DSP3, the wiring unit GLPS of the scanning signal line GL (including at least the scanning signal line GLA) is connected to the wiring unit (first wiring unit) GLP1 connected to the wiring unit GLPM and the wiring unit GLPS. It has a wiring unit (second wiring unit) GLP2 that extends at a position different from that of the wiring unit GLP1. The wiring portion GLP1 is on an extension line of the wiring portion GLPM and extends along the X direction. One end of the wiring portion GLP1 is connected to the wiring portion GLPM. The other end of the wiring portion GLP1 is connected to the wiring portion GLP2 via a wiring portion GLPJ extending along the Y direction. Further, the wiring portion GLP2 is not on the extension line of the wiring portion GLPM, but extends along the X direction. Each of the wiring portion GLP1 and the wiring portion GLP2 intersects a plurality of video signal lines SL in the peripheral region SA (specifically, the region superimposing on the extending portion EXT3). In other words, at least a part of the plurality of video signal lines SL shown in FIG. 12 intersects the wiring portion GLPS at a plurality of points. In the example of the scanning signal line GLA shown in FIG. 12, each of the six video signal lines SL intersects the wiring unit GLP1 and the wiring unit GLP2 of the wiring unit GLPS.

In the case of the display device DSP3, the number of video signal lines SL intersecting the scanning signal line GLA in the peripheral region SA is the same as that of the display device DSP2 shown in FIG. However, the number of places where the scanning signal line GLA and the video signal line SL intersect is larger in the case of the display device DSP3 than in the case of the display device DSP2. In the example shown in FIG. 12, the scanning signal line GLA intersects each of the plurality of video signal lines SL at two points. In this case, in the case of the display device DSP3, the number of parasitic capacitances C1 (see FIG. 7) given to the scanning signal line GLA can be increased as compared with the display device DSP2. In addition, in FIG. 12, as an example in which one scanning signal line GL and one video signal line SL intersect at a plurality of points in the peripheral region SA, an embodiment in which they intersect at two points is shown as an example. "Multiple locations" may be three or more locations.

Further, in the example shown in FIG. 12, the length of the wiring portion GLP2 (length in the X direction) is shorter than the length of the wiring portion GLP1 (length in the X direction). Therefore, the plurality of video signal lines SL that intersect with the wiring unit GLP1 include those that do not intersect with the wiring unit GLP2. In the example of the scanning signal line GLA shown in FIG. 12, each of the two video signal lines SL intersects the wiring portion GLP1 and does not intersect the wiring portion GLP2. According to this embodiment, the difference in wiring resistance between the scanning signal lines GL can be alleviated.

The display device DSP3 shown in FIG. 12 is the same as the display device DSP2 shown in FIG. 11 except for the above-mentioned differences. For example, similarly to the display device DSP2 shown in FIG. 10, in the case of the display device DSP3, a part of the plurality of scanning signal lines GL (for example, the scanning signal line GL) does not have the wiring portion GLPS. Overlapping description of the common parts of the display device DSP3 and the display device DSP2 will be omitted.

Next, among the load factors applied to each of the plurality of pixels PX shown in FIG. 7, the load caused by the parasitic capacitance C4, which is the parasitic capacitance between the scanning signal line GL and the common electrode CE, will be examined. FIG. 13 is an enlarged plan view of a display device which is another modification of FIG. 10. Further, FIG. 14 is an enlarged plan view showing a circuit layout around the circuit block shown in FIG. FIG. 15 is an enlarged plan view showing a circuit layout around a circuit block different from the circuit block shown in FIG. 14 among the plurality of circuit blocks shown in FIG. In FIGS. 13 to 15, a dot pattern is attached to the region overlapping with the common electrode CE. In the following, the differences between the display device DSP4 and the display device DSP10 shown in FIG. 10 will be mainly described, and duplicate description will be omitted.

When the shape of the display area DA is not square or rectangular, the plurality of scanning signal lines GL include those having different lengths superposed on the common electrode CE. For example, in the example shown in FIG. 13, the length of the scanning signal line GLA superimposing on the common electrode CE is shorter than the length of the scanning signal line GLE superimposing on the common electrode CE in a plan view. In other words, the number of parasitic capacitances C4 (see FIG. 7) connected to the signal transmission path for transmitting the scan signal Gsi (see FIG. 6) to the pixel PXE shown in FIG. 13 is the signal for transmitting the scan signal Gsi to the pixel PXA. It is larger than the number of parasitic capacitances C4 connected to the transmission path. Therefore, when only the parasitic capacitance C4 shown in FIG. 7 is taken into consideration, the load applied to the pixel PXE is larger than the load applied to the pixel PXA. As described above, in order to improve the display quality, it is preferable to reduce the in-plane difference of the load applied to each of the plurality of pixels PX.

The display device DSP4 shown in FIGS. 13 to 15 has a part of the common electrode CE in the peripheral region SA, and the scanning signal line GL and the common electrode CE are superimposed in the peripheral region SA. For example, in the portion shown in FIG. 14, the wiring portion GLPS of the scanning signal line GL overlaps with the common electrode CE in the region of the peripheral region SA that overlaps with the extending portion EXT3. In this case, the length of the scanning signal line GL (for example, the scanning signal line GLA) overlapping with the common electrode CE is longer than that of the display device DSP1 (see FIG. 8) and the display device DSP2 (see FIG. 10). That is, among the loads applied to the pixels PXA connected to the scanning signal line GLA, the load corresponding to the parasitic capacitance C4 shown in FIG. 7 increases. As a result, it is possible to reduce the in-plane difference of the load applied to each of the plurality of pixels PX.

Further, in the case of the display device DSP4, the length of the wiring portion GLPS of the scanning signal line GL overlapping with the common electrode CE is not constant. The length at which the wiring portion GLPS of the scanning signal line GL overlaps with the common electrode CE is different depending on the number of video signal lines SL at which the scanning signal line GL intersects. As the number of intersecting video signal lines SL increases, the load caused by the parasitic capacitance C1 shown in FIG. 7 increases, so that the load caused by the parasitic capacitance C4 may be small. Therefore, the larger the number of video signal lines SL intersecting the scanning signal line GL, the shorter the distance overlapped with the common electrode CE. On the other hand, when the number of intersecting video signal lines SL is small, the load caused by the parasitic capacitance C1 shown in FIG. 7 is small. Therefore, it is necessary to increase the overall load by increasing the load caused by the parasitic capacitance C4. is there. Therefore, it is preferable that the smaller the number of intersecting video signal lines SL, the longer the distance overlapped with the common electrode CE.

For example, as shown in FIG. 15, in the region overlapping with the bending portion BEN1, the wiring portion GLPS of the scanning signal line GL overlaps with the common electrode CE. Comparing the scanning signal line GLA shown in FIG. 14 and the scanning signal line GLD shown in FIG. 15, the number of video signal lines SL at which the scanning signal lines GLA intersect in the display area DA in the plan view is the scanning signal line GLD. Is less than the number of video signal lines SL that intersect. In this case, in the peripheral region SA, the length of the wiring portion GLPS of the scanning signal line GLA overlapping with the common electrode CE is longer than the length of the wiring portion GLPS of the scanning signal line GLD overlapping with the common electrode CE. Further, similarly to the display device DSP2 described with reference to FIG. 10, the scanning signal line that maximizes the number of video signal lines SL intersecting in the display area DA, for example, the scanning signal line GLE (see FIG. 13). In the case of GL, it does not have a wiring portion GLPS. As described above, when the length of the wiring portion GLPS of the scanning signal line GL superimposed on the common electrode CE is a plurality of lengths depending on the number of video signal lines SL where the scanning signal line GL intersects. Of the loads applied to each of the pixels PX, the in-plane difference of the load due to the parasitic capacitance C4 shown in FIG. 7 can be reduced.

Further, the technique described in the display device DSP4 shown in FIGS. 13 to 15 may be combined with the technique described in the display device DSP3 shown in FIG. FIG. 16 is an enlarged plan view showing a circuit layout around a circuit block of a display device, which is a modification of FIGS. 12 and 14. In the case of the display device DSP5 shown in FIG. 16, the wiring unit GLPS of the scanning signal line GL (including at least the scanning signal line GLA) includes the wiring unit (first wiring unit) GLP1 connected to the wiring unit GLPM and the wiring unit GLPS. It has a wiring unit (second wiring unit) GLP2 which is connected to and extends to a position different from that of the wiring unit GLP1. The wiring portion GLP1 is on an extension line of the wiring portion GLPM and extends along the X direction. One end of the wiring portion GLP1 is connected to the wiring portion GLPM. The other end of the wiring portion GLP1 is connected to the wiring portion GLP2 via a wiring portion GLPJ extending along the Y direction. Further, the wiring portion GLP2 is not on the extension line of the wiring portion GLPM, but extends along the X direction. Each of the wiring portion GLP1 and the wiring portion GLP2 overlaps with the common electrode CE in the peripheral region SA (specifically, the region superimposing on the extending portion EXT3). In the case of the display device DSP5, the distance on which the scanning signal line GLA overlaps with the common electrode CE is further longer than that in the display device DSP4 shown in FIG.

Next, the circuit layout in the peripheral region SA on the Y1 side located opposite to the Y2 side in the Y direction shown in FIG. 1 will be described. A switch circuit SWS is arranged on the other hypotenuse of the display device DSP1 having a trapezoidal planar shape, that is, on the side along the extending portion EXT4 (see FIG. 1), and a plurality of video signal lines SL are placed in the display area DA. It extends toward. Therefore, it is difficult to arrange the drive circuit GD1 or the drive circuit GD2 along the extending portion EXT4. Therefore, a circuit layout different from that on the Y2 side is applied to the side on the Y1 side in the Y direction shown in FIG.

FIG. 17 is an enlarged plan view showing details of the circuit configuration on the lower side of the display device shown in FIG. Further, FIG. 18 is an enlarged plan view showing an example of the layout of the common electrodes in the plane shown in FIG. As shown in FIG. 17, the display device DSP1 includes a switch circuit (selection circuit) SWS between the display area DA and the driver chip DRC1 in which the control circuit CTC (see FIG. 6) is formed. Further, in a plan view, there are no drive circuits GD1 and GD2 between the switch circuit SWS and the display area DA. In this case, each of the plurality of video signal lines SL does not have a bent portion in the middle and extends linearly from the switch circuit SWS along the Y direction. The total number of video signal lines SL is larger than the total number of scanning signal lines GL. Therefore, it is preferable that each of the plurality of video signal lines SL does not bend and extends linearly.

On the other hand, the plurality of scanning signal lines GL include scanning signal lines GL having a bent portion, such as the scanning signal line GLn1 and the scanning signal line GLn2 shown in FIG. Specifically, the scanning signal line GLn1 and the scanning signal line GLn2 passing between the display region DA and the switch circuit SWS have a bent portion in the peripheral region SA. Each part of the scanning signal line GLn1 and the scanning signal line GLn2 extends between the display area DA and the switch circuit SWS (in other words, between the display area DA and the control circuit CTC of the driver chip DRC1). However, each of the plurality of scanning signal lines GL extends along the X direction in the display area DA (in other words, the section overlapping the display area DA). Further, in the display area DA, each of the plurality of scanning signal lines GL is arranged at equal intervals.

When the two-sided drive method is applied to each of the plurality of scanning signal lines GL, the number of circuit blocks GDB1 constituting the drive circuit GD1 and the number of circuit blocks GDB2 constituting the drive circuit GD2 are equal. However, since the extension portion EXT1 and the extension portion EXT2 have different lengths as described above, the arrangement spaces of the circuit blocks GDB1 and GDB2 are different. That is, as described above, the extending portion EXT2 is longer than the extending portion EXT1 in the Y direction. In this case, the region overlapping with the extending portion EXT2 can secure a wide space for arranging the plurality of circuit blocks GDB2 constituting the drive circuit GD2. Therefore, the plurality of circuit blocks GDB2 are linearly arranged along the Y direction. In other words, the plurality of circuit blocks GDB2 constituting the drive circuit GD2 can be easily arranged so as to avoid the space between the switch circuit SWS and the display area DA.

On the other hand, the area superimposing on the extending portion EXT1 is a space for arranging a plurality of circuit blocks GDB1 constituting the drive circuit GD1, but the area is smaller than the area of the area superimposing on the extending portion EXT2. As a result, the plurality of circuit blocks GDB1 constituting the drive circuit GD1 are arranged not only in the region superposed on the extending portion EXT1 but also in the region superimposing on the bent portion BEN3. The circuit block GDB1 that overlaps with the bent portion BEN3 is arranged at a narrower pitch than the circuit block GDB2 that overlaps with the extending portion EXT2. Therefore, in the region on the Y2 side, the circuit blocks GDB1 and the circuit blocks GDB2 arranged at different positions in the Y direction may be connected via one scanning signal line GL. For example, one end of the scanning signal line GLN1 and the scanning signal line GLn2 shown in FIG. 17 is connected to the circuit block GDB1, and the other end is connected to the circuit block GDB2. And. In the Y direction, the positions of the circuit block GDB1 and the circuit block GDB2 are different from each other.

Further, as shown in FIG. 17, in the display area DA, the number of the plurality of video signal lines SL where the scanning signal lines GLn1 intersect is the same as the number of the plurality of video signal lines SL where the scanning signal lines GLn2 intersect. It's different. In the example shown in FIG. 17, in the plan view, the number of the plurality of video signal lines SL where the scanning signal lines GLn1 intersect is greater than the number of the plurality of video signal lines where the scanning signal lines GLn2 intersect in the display area DA. There are few. In the pixel PX shown in FIG. 7, since the scanning signal line GL and the video signal line SL are provided at each intersection, the relationship between the scanning signal line GLn1 and the scanning signal line GLn2 shown in FIG. 17 is expressed as follows. it can. That is, the number of pixel PXs connected to the scanning signal line GLn1 is smaller than the number of pixel PXs to which the scanning signal line GLn2 is connected. Further, since the pixel PX includes a transistor (pixel transistor) Tr1, it can be expressed as follows. The number of transistors Tr1 connected to the scanning signal line GLn1 is smaller than the number of transistors Tr1 connected to the scanning signal line GLn2.

In the example shown in FIG. 17, in a plan view, the number of the plurality of video signal lines SL where the scanning signal lines GLn1 intersect is the same as the number of the plurality of video signal lines SL where the scanning signal lines GLn2 intersect. Therefore, among the load factors applied to each of the plurality of pixels PX shown in FIG. 7, the load caused by the parasitic capacitance C1 is made uniform. However, the load caused by the parasitic capacitance C3 may have a large in-plane difference due to the following reasons.

That is, the parasitic capacitance C3 changes according to the number of transistors Tr1 connected to the scanning signal line GL. As shown in FIG. 17, when the number of transistors Tr1 (see FIG. 7) connected to the scanning signal line GLn1 is smaller than the number of transistors Tr1 to which the scanning signal line GLn2 is connected, the scanning signal line GLn1 is assigned. The load is relatively small. As a method of reducing the in-plane difference of the load caused by the parasitic capacitance C3, a transistor having the same structure as the transistor Tr1 (such as a transistor of a dummy pixel) is arranged in the peripheral region SA, and the scanning signal lines GL have a plurality of scanning signal lines. There is also a method of reducing the difference in the number of connected transistors Tr1. However, as shown in FIG. 17, in the region between the display region DA and the switch circuit SWS, a part of the scanning signal line GL is pulled out to the Y1 side from the connection position with the circuit block GDB1, and the outer edge of the display region DA. It is arranged along a portion (outer peripheral side) at a narrower arrangement pitch than other regions. Further, in this region, since the arrangement pitch itself of the plurality of circuit blocks GDB1 is narrowed, there is an area in which the arrangement density of the scanning signal line GL is locally increased. In FIG. 17, in the region between the display region DA and the switch circuit SWS, a portion where the plurality of scanning signal lines GL and the plurality of video signal lines SL intersect at an angle other than orthogonal with a portion orthogonal to each other in a plan view. Is included. The arrangement density of the scanning signal lines GL is relatively high in the portion where the plurality of scanning signal lines GL and the plurality of video signal lines SL intersect at angles other than orthogonal. As described above, it is difficult to arrange the transistor Tr1 in the region where the arrangement density of the scanning signal line GL is high.

Therefore, for the scanning signal line GL passing between the display area DA and the switch circuit SWS, it is preferable to compensate for the load variation caused by the parasitic capacitance C3 with another load. For example, as shown in FIG. 18, the length at which the scanning signal line GLn1 overlaps with the common electrode CE is longer than the length at which the scanning signal line GLn2 overlaps with the common electrode CE. Therefore, considering the parasitic capacitance C4 (see FIG. 7), the load caused by the parasitic capacitance C4 applied to the scanning signal line GLn1 is larger than the load caused by the parasitic capacitance C4 applied to the scanning signal line GLn2. .. In this case, the variation in the load caused by the parasitic capacitance C3 can be compensated for by the load caused by the parasitic capacitance C4, and the variation in the load as a whole can be reduced.

Further, as shown in FIGS. 17 and 18, the scanning signal line GLn1 is arranged closer to the switch circuit SWS than the scanning signal line GLn2, in other words, closer to the control circuit CTC of the driver chip DRC1. Further, the length of the scanning signal line GLn1 is longer than the length of the scanning signal line GLn2. Therefore, considering the load caused by the wiring resistance of the scanning signal line GL, the load caused by the wiring resistance of the scanning signal line GLn1 is larger than the load caused by the wiring resistance of the scanning signal line GLn2. In this case, the variation in the load caused by the parasitic capacitance C3 can be compensated for by the load caused by the wiring resistance, and the variation in the load as a whole can be reduced.

Next, among the load factors applied to each of the plurality of pixels PX shown in FIG. 7, the load caused by the parasitic capacitance C2 between the video signal line SL and the transistor Tr1 will be examined. The capacitance caused by the parasitic capacitance C2 shown in FIG. 7 changes according to the number of transistors Tr1 connected to the video signal line SL. Therefore, when the number of transistors Tr1 connected to each of the plurality of video signal lines SL is different from each other, the load caused by the parasitic capacitance C2 applied to the plurality of video signal lines SL varies. Further, as shown in FIG. 3, each of the plurality of video signal lines SL extends in the Y direction and has different lengths overlapping with the display area DA. For example, in the example shown in FIG. 3, the length of the video signal line SLm on the X2 side of the video signal line SL1 overlapping the display area DA is longer than the length of the video signal line SL1 overlapping the display area DA. Further, in the example shown in FIG. 17, the display device DSP1 has a video signal line (first video signal line) SLd1 and a video signal line (second video signal line) SLd2. The length of the video signal line SLd2 overlapping with the display area DA is longer than the length of the video signal line SLd1 overlapping with the display area DA. In this case, in a plan view, the number of transistors Tr1 (see FIG. 7) connected to the video signal line SLd1 is smaller than the number of transistors Tr1 connected to the video signal line SL. Therefore, the load caused by the parasitic capacitance C2 applied to the video signal line SLd1 is smaller than the load caused by the parasitic capacitance C2 applied to the video signal line SLd2.

The peripheral region SA located between the display region DA and the switch circuit SWS shown in FIG. 18 includes a region that overlaps with the common electrode CE and a region that does not overlap with the common electrode CE. At least the video signal line SLd2 has a portion that does not overlap with the common electrode CE in the peripheral region SA. In the peripheral region SA, the length of the video signal line SLd1 overlapping with the common electrode CE is longer than the length of the video signal line SLd2 overlapping with the common electrode CE. Here, among the load factors applied to each of the plurality of pixels PX shown in FIG. 7, the load caused by the parasitic capacitance C5 between the video signal line SL and the common electrode CE is the load caused by the video signal line SL and the common electrode CE. It increases in proportion to the length in which and Therefore, the load caused by the parasitic capacitance C5 applied to the video signal line SLd1 in the peripheral region SA is larger than the load caused by the parasitic capacitance C5 applied to the video signal line SLd2. Therefore, the variation in the load caused by the parasitic capacitance C2 can be compensated for by the load caused by the parasitic capacitance C5, and the variation in the load as a whole can be reduced.

The above-mentioned expression "in the peripheral region SA, the length at which the video signal line SLd1 overlaps with the common electrode CE is longer than the length at which the video signal line SLd2 overlaps with the common electrode CE" is expressed as a video signal line. In addition to a mode in which each of SLd1 and the video signal line SLd2 overlaps with the common electrode CE in the peripheral region SA, a mode in which the video signal line SLd2 does not overlap with the common electrode CE in the peripheral region SA is also included.

Further, in the example shown in FIG. 17, each of the plurality of video signal lines SL has a different length from the switch circuit SWS to the display area DA. The plurality of video signal lines SL have a video signal line (third video signal line) SLd3 and a video signal line (fourth video signal line) SLd4. In a plan view, the length of the video signal line SLd4 from the switch circuit SWS to the display area DA is longer than the length of the video signal line SLd3 from the switch circuit SWS to the display area DA. As shown in FIG. 17, among the plurality of scanning signal lines GL, the scanning signal line GLn1 arranged at the position closest to the switch circuit SWS intersects the video signal line SLd3 in the display area DA. Since the video signal line SLd3 does not need to intersect the scanning signal line GL outside the display area DA (that is, the peripheral area SA), the length to the switch circuit SWS can be shortened. On the other hand, the scanning signal line GLn1 intersects the video signal line SLd4 outside the display area DA (specifically, between the display area DA and the switch circuit SWS). If the length of the video signal line SLd4 from the switch circuit SWS to the display area DA is long, a plurality of scanning signal lines GL and the video signal line SLd4 can be crossed in the peripheral area SA.

In this way, by crossing a part of the plurality of scanning signal lines GL and the video signal line SLd4 outside the display area DA, the plurality of video signal lines SL and the plurality of scanning signal lines GL are mutually aligned. The number of intersections can be made uniform. As described with reference to FIG. 7, the parasitic capacitance C1 between the scanning signal line GL and the video signal line SL is one of the load factors given to the pixel PX. Therefore, by equalizing the number of intersecting the plurality of video signal lines SL and the plurality of scanning signal lines GL, it is possible to reduce the variation in the in-plane distribution of the load applied to the pixel PX.

Further, in the example shown in FIG. 18, the length of the video signal line SLd3 overlapping with the common electrode CE is longer than the length of the video signal line SLd4 overlapping with the common electrode CE. On the other hand, in the peripheral region SA, the length of the video signal line SLd4 overlapping with the common electrode CE is longer than the length of the video signal line SLd3 overlapping with the common electrode CE. The video signal line SLd4 is on the X1 side of the video signal line SLd3, and the overall length is short. Therefore, in the display area DA, the length of the video signal line SLd3 overlapping with the common electrode CE is longer than the length of the video signal line SLd4 overlapping with the common electrode CE. In this case, the load caused by the parasitic capacitance C5 described with reference to FIG. 7 varies. As shown in FIG. 18, in the peripheral region SA, the length at which the video signal line SLd4 overlaps with the common electrode CE is caused by the parasitic capacitance C5 when the length at which the video signal line SLd3 overlaps with the common electrode CE is longer. It is possible to reduce the variation in the load to be applied.

The technique found by the inventor of the present application has been specifically described above based on the embodiment as an example, but the present invention is not limited to the above embodiment and is variously modified without departing from the gist thereof. It is possible.

For example, in the above embodiment, the case of a liquid crystal display device is illustrated as a disclosure example, but as another application example, an organic EL display device, another self-luminous display device, an electronic paper having an electrophoresis element, or the like is used. All flat panel type display devices such as type display devices can be mentioned. In addition, it can be applied from small to medium size to large size without any particular limitation.

Further, for example, as an example of a display device having a display area having a deformed shape other than a square or a rectangle, a display device having a trapezoidal display area has been taken up and described. However, the shape of the display area DA may be other than the trapezoid. For example, the shape of the display area DA may be a parallelogram.

Further, for example, in the above embodiment, as shown in FIG. 3, both ends of each of the plurality of scanning signal lines GL are connected to the drive circuit GD1 and the drive circuit GD2, and the entire display area DA is driven on both sides. An embodiment of driving by a method has been described. However, as a modification, the entire display area DA may be driven by a one-sided drive method. In this case, for example, the drive circuit GD1 shown in FIG. 3 may not be provided, and all the scanning signal lines GL may be driven by the drive circuit GD2 in a one-sided drive system. Alternatively, each of the plurality of scanning signal lines GL may be connected to one of the drive circuit GD1 and the drive circuit GD2, and may not be connected to the other.

Further, for example, in each diagram for explaining the relationship between the drive circuit GD and the scanning signal line GL connected to the drive circuit GD, such as FIG. 6, a circuit block in which one switch circuit GSW is connected to one shift register circuit GSR. An example in which one scanning signal line GL is connected to each of the GDBs is shown. The switch circuit GSW and the scanning signal line GL need to have a one-to-one correspondence, but as shown in the modified example shown in FIG. 19, a plurality of switch circuits GSW are connected to one shift register circuit GSR. Is also good. FIG. 19 is a circuit block diagram showing a modified example of the circuit block shown in FIG. In the example shown in FIG. 19, four switch circuits GSW are connected to each of the plurality of shift register circuits GSR. A circuit block is composed of a set of one shift register circuit GSR and four switch circuits GSW. Further, one scanning signal line GL is connected to each of the plurality of switch circuits.

In the case of the modification shown in FIG. 19, enable lines GWE independent of each other are connected to each of the switch circuits GSW included in one circuit block GDB. In this case, by combining the pulse signal supplied from the shift register circuit GSR and the pulse signal supplied from the enable line GWE, the scanning signal Gsi (see FIG. 6) is sequentially generated for each of the plurality of scanning signal lines GL. Can be transmitted. In the case of the modified example shown in FIG. 19, the number of shift register circuits GSR can be reduced as compared with the example described with reference to FIG. Further, assuming that the number of scanning signal lines GL is the same, as shown in FIG. 19, each of the plurality of scanning signal lines GL is connected to one of a plurality of enable lines GWE independent of each other. The configuration is advantageous in the following points. That is, since the number of GS switch circuits GSW connected to the enable line GWE is reduced (1/4 in the example of the figure), the load capacitance of the enable GWE line can be reduced.

Further, in the present specification, various embodiments based on the technical idea have been described by dividing them into a plurality of modifications, but in the plurality of embodiments (mods), duplicate explanations are omitted for common parts. There is. Therefore, two or more of the above-mentioned plurality of modifications may be applied in combination.

Within the scope of the idea of the present invention, those skilled in the art can come up with various modified examples and modified examples, and it is understood that these modified examples and modified examples also belong to the scope of the present invention.

For example, a person skilled in the art appropriately adds, deletes, or changes the design of each of the above-described embodiments, or adds, omits, or changes the conditions of the process of the present invention. As long as it has a gist, it is included in the scope of the present invention.

The present invention is effective when applied to an input device or a display device having an input detection function.

10,20 Insulation substrate 11,12,13,14 Insulation film AL1, AL2 Alignment film BEN1, BEN2, BEN3, BEN4 Bending part BL Backlight unit BM Light-shielding layer C1, C2, C3, C4, C5 Parasitic capacitance CD Common electrode drive Circuit CDF Conductive CE Common electrode CFB, CFG, CFR Color filter CML Common line CS Retention capacitance CTC Control circuit D1, D2, D3, D4 Distance DA display area DE Drain electrode DRC1 Driver chip (semiconductor chip)
DRA area (first area)
DS display surface DSC internal circuit DSP1, DSP2, DSP3, DSP4, DSP5 Display device ENB enable signal EXT1, EXT2, EXT3, EXT4 Extended part FDW, FW, PLH, PLL Wiring FWB1 Wiring board GBA1, GBA2, GBB1, GBB2, GBC1 , GBC2, GBD1, GBD2, GBE1, GBE2, GDB, GDB1, GDB2 Circuit block GBU Buffer circuit GCL, GCL1, GCL2 Clock signal GD, GD1, GD2 Drive circuit GE Gate electrode GL, GL1, GL2, GLA, GLC, GLD, GLE, GLn, GLn1, GLn2 scanning signal line GLP, GLP1, GL22, GLPJ, GLPM, GLPS wiring unit Gsi, Gsi1, Gsi2, Gsin scanning signal GSP start pulse signal GSR shift register circuit GSW switch circuit GW control wiring GWC, GWC1, GWC2 Clock line GWE, GWE1, GWE2 Enable line GWS Start pulse line LQ Liquid crystal layer NDA2 area OCL Overcoat layer OD1, OD2 Optical element PD1, PD2, PD3 terminal PE pixel electrode PL, PL1, PL2 Power supply wiring PNL1 Display panel PSC power supply circuit PSW pixel switch element PX, PXA, PXE pixel SA peripheral area SCL video signal connection line SD video signal line drive circuit SE source electrode SL, SL1, SL2, SLd1, SLd2, SLd3, SLd4, SLm video signal line Spic video signal SUB1, SUB2 board SWS switch circuit T1, T2, T3, X, Y direction TM1 terminal part Tr1 transistor VD power supply potential VDH, VDL potential WL1, WL2, WL3 wiring layer

Claims (10)

The display area where the first pixel is arranged and
Overlapping with the light-shielding layer, the peripheral area outside the display area,
A plurality of scanning signal lines and a plurality of video signal lines in the display area,
The first drive circuit and the second drive circuit that supply the scan signal,
A first potential supply line that supplies a potential to the plurality of scanning signal lines via the first drive circuit, and
A first wiring layer and a second wiring layer formed of a material having a resistivity lower than that of the first wiring layer are provided.
The plurality of video signal lines extend in the first direction and extend.
The light-shielding layer includes a first extending portion and a second extending portion extending along the first direction, and a first bending portion and a first bending portion between the first extending portion and the second extending portion. It has a second bent portion and a third extending portion between the first bent portion and the second bent portion.
The first extending portion is connected to the first bending portion, and the second extending portion is connected to the second bending portion.
The first potential supply line overlaps with the third extending portion,
The plurality of scanning signal lines include a first scanning signal line and a second scanning signal line.
A part of the first scanning signal line is superimposed on the third extending portion, and a part of the second scanning signal line is superimposed on the first extending portion.
In a plan view, the number of the plurality of video signal lines intersecting the first scanning signal lines and the number of the plurality of video signal lines intersecting the second scanning signal lines in the display area are different.
A display device in which the first potential supply line passes through the first wiring layer and the second wiring layer in a region superimposed on the third extending portion. The first drive circuit has a first A circuit block, a first B circuit block, a first C circuit block, and a first D circuit block.
The first potential supply line passes through the first wiring layer at a first distance between the first A circuit block and the first B circuit block, and the first C circuit block and the first D circuit block. Via the first wiring layer at a second distance to and from
The display device according to claim 1, wherein the second distance is shorter than the first distance. A second potential supply line for supplying a potential to the scanning signal line via the second drive circuit is provided.
The first drive circuit has a first A circuit block and a first B circuit block.
The first potential supply line passes through the first wiring layer at a first distance between the first A circuit block and the first B circuit block.
The second drive circuit has a second A circuit block and a second B circuit block.
The second potential supply line passes through the first wiring layer at a third distance between the second A circuit block and the second B circuit block.
The first A circuit block and the second A circuit block are connected to the same scanning signal line among the plurality of scanning signal lines.
The display device according to claim 1 or 2, wherein the first distance is longer than the third distance. A second potential supply line that supplies a potential to the plurality of scanning signal lines via the second drive circuit is provided.
The first drive circuit has a first C circuit block and a first D circuit block.
The first potential supply line passes between the first C circuit block and the first D circuit block via the first wiring layer and the second wiring layer.
The second drive circuit has a second C circuit block and a second D circuit block.
The second potential supply line passes between the second C circuit block and the second D circuit block via the second wiring layer and does not pass through the first wiring layer.
The display device according to any one of claims 1 to 3, wherein the first D circuit block and the second D circuit block are connected to the same scanning signal line among the plurality of scanning signal lines. A part of the first potential supply line overlaps with the first extending portion,
Any one of claims 1 to 4, wherein the first potential supply line passes through the second wiring layer and does not pass through the first wiring layer in the region superposed on the first extending portion. The display device described in. In a plan view, the first scanning signal line is connected to the main wiring section between the first drive circuit and the display area, and in the display area, and the first drive circuit. It has an auxiliary wiring portion between the outer edge of the peripheral region and the peripheral region.
The display device according to any one of claims 1 to 5, wherein the sub-wiring portion intersects the video signal line in a plan view. In a plan view, the sub-wiring portion is connected to the first wiring portion connected to the main wiring portion and the second wiring portion connected to the first wiring portion and extends to a position different from the first wiring portion in the peripheral region. Has a wiring part,
The display device according to claim 6, wherein the sub-wiring portion intersects the video signal line at a plurality of locations in the peripheral region. The second scanning signal line does not have the sub-wiring portion.
In a plan view, the number of the plurality of video signal lines intersecting the first scanning signal lines in the display area is smaller than the number of the plurality of video signal lines intersecting the second scanning signal lines. The display device according to claim 6. Electro-optic layer and
A plurality of first electrodes for driving the electro-optical layer and a second electrode facing the plurality of first electrodes are provided.
The display device according to claim 6, wherein the sub-wiring portion is superimposed on the second electrode. The display device according to any one of claims 1 to 9, wherein the length of the second extending portion is longer than the length of the first extending portion.

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