WO2013002229A1

WO2013002229A1 - Shift register, scanning signal line drive circuit, display panel, and display device

Info

Publication number: WO2013002229A1
Application number: PCT/JP2012/066302
Authority: WO
Inventors: 村上　祐一郎; 成古田; 真横山; 佐々木　寧; 業天　誠二郎
Original assignee: シャープ株式会社
Priority date: 2011-06-30
Filing date: 2012-06-26
Publication date: 2013-01-03

Abstract

In a holding circuit (11a) of each stage of a shift register, when a clock signal (CK) is at a high level, the input terminal of an inverter INV1 and the output terminal of an inverter INV2 are electrically connected to each other, and the output terminal of the inverter INV1 and the input terminal of the inverter INV2 are electrically connected to each other. The size of the shift register circuit can thus be reduced.

Description

Shift register, scanning signal line drive circuit, display panel, and display device

The present invention relates to a shift register used in a display device.

In recent years, in order to narrow the frame of a liquid crystal display device, there has been a demand for downsizing a display driving circuit that drives a liquid crystal panel. Since the scale of the display driving circuit greatly affects the number of transistors included in the circuit, it is important to reduce the number of transistors.

Here, as an example of a conventional display driving circuit, a signal holding circuit (hereinafter referred to as a holding circuit) constituting a shift register used in a scanning signal line driving circuit (gate driver) is cited (for example, Patent Document 1). FIG. 59 is a block diagram showing a schematic configuration of a conventional shift register, and FIG. 60 is a circuit diagram of a holding circuit constituting the shift register shown in FIG.

60 is configured as a D-type flip-flop. This D-type flip-flop DFF has a clocked inverter INV1 connected in series, an inverter INV2, an output terminal of the inverter INV2 connected to the input terminal, and an output terminal connected to the input terminal of the inverter INV2. INV5. The inverters INV1, INV2, and INV5 are composed of CMOS transistors. The clock signal / C is input to the clock input terminal on the PMOS side of the clocked inverter INV1, while the clock signal C is input to the clock input terminal on the NMOS side, and the clock signal C is input to the clock input terminal on the PMOS side of the clocked inverter INV5. The clock signal / C is input to the clock input terminal on the NMOS side.

As described above, the D-type flip-flop DFF is composed of one inverter and two clocked inverters, and clock signals having opposite phases are input to the two clocked inverters, respectively. The adjacent D-type flip-flops DFF are input with clock signals having opposite phases.

FIG. 61 is a timing chart when the shift register shown in FIG. 59 operates. When the start signal ST is input, the shift register sequentially outputs the output signal O from each holding circuit while shifting in synchronization with the rising edges of the clock signals CK and CKB.

Japanese Patent Publication “JP 2001-216696 (published August 10, 2001)”

In the above conventional holding circuit, in order to properly latch the input signal in the D-type flip-flop, when receiving the signal from the input terminal IN, it is necessary to release the latch by setting the output of the clocked inverter INV5 to the floating state. There is. There is a problem that the number of elements increases by the circuit for releasing the latch.

Accordingly, an object of the present invention is to reduce the circuit scale of the shift register.

In order to solve the above problems, the shift register of the present invention provides
A shift register having a holding circuit in each stage,
The holding circuit includes a data input unit that captures a retention target signal in response to an enable signal, and a first inverter and a second inverter that retain the captured retention target signal, and the first inverter or the second inverter. Based on the output of the inverter, it outputs a high level or low level signal,
When the enable signal is active, the input terminal of the first inverter and the output terminal of the second inverter are electrically connected to each other, and the output terminal of the first inverter and the input of the second inverter The terminals are electrically connected to each other.

The shift register of the present invention has a configuration in which the output of the first inverter and the input of the second inverter are electrically connected when an enable signal (for example, a clock signal) is active. With this configuration, the circuit scale of the shift register can be reduced.

Here, even if the input signal and the power supply VDD are short-circuited, there is no problem if the second inverter can be operated (reversed) normally. In the above configuration, for example, the channel of the transistor constituting the first inverter By providing a configuration in which the length is increased and a configuration in which a resistor is provided in the first inverter, a signal input to the second inverter at the time of a short circuit can be drawn into the potential level of the input signal. It can be operated (inverted) (details will be described later). Therefore, there is no problem in operation due to the reduction in circuit scale.

As described above, in the shift register of the present invention, when the enable signal is active, the input terminal of the first inverter and the output terminal of the second inverter are electrically connected to each other. The output terminal of one inverter and the input terminal of the second inverter are electrically connected to each other. Thereby, the circuit scale of the shift register can be reduced.

FIG. 3 is a circuit diagram of a unit circuit included in the shift register according to the first embodiment. 1 is a block diagram illustrating a schematic configuration of a shift register according to a first embodiment. 4 is a timing chart during operation of the shift register according to the first embodiment. FIG. 6 is a diagram schematically illustrating a timing chart during operation of the shift register according to the first embodiment. 6 is a circuit diagram of a unit circuit included in a shift register according to Embodiment 2. FIG. FIG. 10 is a circuit diagram of a unit circuit included in a shift register according to a third embodiment. FIG. 10 is a circuit diagram of a unit circuit included in a shift register according to a fourth embodiment. FIG. 10 is a circuit diagram of a unit circuit included in a shift register according to a fifth embodiment. FIG. 10 is a block diagram illustrating a schematic configuration of a shift register according to a fifth embodiment. FIG. 10 is a circuit diagram of a unit circuit included in a shift register according to a sixth embodiment. FIG. 10 is a circuit diagram of a unit circuit included in a shift register according to a seventh embodiment. FIG. 10 is a circuit diagram of a unit circuit included in a shift register according to an eighth embodiment. FIG. 20 is a circuit diagram of a unit circuit included in a shift register according to Embodiment 9. FIG. 20 is a circuit diagram of a unit circuit included in a shift register according to the tenth embodiment. FIG. 22 is a circuit diagram of a unit circuit included in a shift register according to an eleventh embodiment. FIG. 22 is a circuit diagram of a unit circuit included in a shift register according to a twelfth embodiment. 18 is a timing chart at the time of operation of the shift register according to the twelfth embodiment. FIG. 23 is a circuit diagram of a unit circuit included in a shift register according to a thirteenth embodiment. 14 is a timing chart of the operation of the shift register according to the thirteenth embodiment. FIG. 22 is a circuit diagram of a unit circuit included in a shift register according to Embodiment 14; FIG. 20 is a circuit diagram illustrating a connection relationship between a switching circuit and a k-th unit circuit included in a shift register according to a fourteenth embodiment. It is a block diagram which shows schematic structure of the shift register provided with the switching circuit. 6 is a timing chart during operation of a shift register including a switching circuit. It is a block diagram which shows schematic structure of the shift register provided with the switching circuit. FIG. 6 is a block diagram illustrating a schematic configuration of a liquid crystal display device according to a second embodiment. FIG. 26 is an equivalent circuit diagram illustrating an electrical configuration of a pixel of the liquid crystal display device of FIG. 25. FIG. 20 is a block diagram illustrating a schematic configuration of a shift register according to a fifteenth embodiment. FIG. 22 is a circuit diagram of odd-numbered unit circuits included in a shift register according to a fifteenth embodiment. FIG. 22 is a circuit diagram of a unit circuit of an even number stage included in a shift register according to the fifteenth embodiment. 18 is a timing chart at the time of operation of the shift register according to the fifteenth embodiment. 18 is a timing chart at the time of operation of the shift register according to the fifteenth embodiment. FIG. 20 is a block diagram illustrating a schematic configuration of a shift register according to a sixteenth embodiment. FIG. 22 is a circuit diagram of an SR unit circuit constituting a shift register according to Embodiment 16; 18 is a timing chart at the time of operation of the shift register according to the sixteenth embodiment. 18 is a timing chart at the time of operation of the shift register according to the sixteenth embodiment. FIG. 30 is a circuit diagram illustrating another configuration of a unit circuit included in a shift register according to Embodiment 16; FIG. 18B is a circuit diagram of an odd-numbered SR unit circuit constituting the shift register according to the seventeenth embodiment. FIG. 20 is a circuit diagram of an SR unit circuit of an even number stage configuring a shift register according to Embodiment 17; 18 is a timing chart during operation of the shift register according to the seventeenth embodiment. FIG. 28 is a circuit diagram of an odd-numbered SR unit circuit constituting a shift register according to Embodiment 18; FIG. 22 is a circuit diagram of even-numbered SR unit circuits constituting a shift register according to Embodiment 18; 19 is a timing chart at the time of operation of the shift register according to the eighteenth embodiment. FIG. 40 is a circuit diagram of an SR unit circuit constituting a shift register according to Embodiment 19; FIG. 23 is a timing chart of the operation of the shift register according to the nineteenth embodiment. FIG. FIG. 38 is a circuit diagram illustrating another configuration of the SR unit circuit constituting the shift register according to the nineteenth embodiment. FIG. 22 is a circuit diagram of a unit circuit included in a shift register according to the fifteenth embodiment. FIG. 30 is a circuit diagram of an SR unit circuit constituting a shift register according to Embodiment 20; 24 is a timing chart at the time of operation of the shift register according to the twentieth embodiment. FIG. 38 is a circuit diagram of a first-stage SR unit circuit constituting a shift register according to Embodiment 21; FIG. 32 is a circuit diagram of a second-stage SR unit circuit constituting the shift register according to the twenty-first embodiment. FIG. 22 is a circuit diagram of an SR unit circuit constituting a shift register according to a twenty-second embodiment. FIG. 25 is a block diagram illustrating a schematic configuration of a shift register according to a twenty-third embodiment. FIG. 38 is a circuit diagram of a second-stage SR unit circuit constituting the shift register according to the twenty-third embodiment. 23 is a timing chart at the time of operation of the shift register according to the twenty-third embodiment. 54 is a timing chart for explaining a potential change of a node N1 in the SR unit circuit of FIG. 53. FIG. 54 is a circuit diagram of an SR unit circuit showing a modification of the SR unit circuit of FIG. 53. 57 is a timing chart at the time of operation of the shift register according to FIG. 56. 57 is a timing chart for explaining a potential change of a node N1 in the SR unit circuit of FIG. 56. It is a block diagram which shows schematic structure of the conventional shift register. It is a circuit diagram of the holding circuit which comprises the conventional shift register. It is a timing chart at the time of operation | movement of the conventional shift register.

[Embodiment 1]
Embodiment 1 according to the present invention will be described below. FIG. 2 is a block diagram showing a schematic configuration of the shift register according to the first embodiment.

As shown in FIG. 2, the shift register 10 includes n (n is an integer of 2 or more) unit circuits 11a (holding circuits) connected in multiple stages. The unit circuit 11a has a clock terminal (CKa terminal, CKb terminal), an input terminal (IN terminal), and an output terminal (OUT terminal). Hereinafter, a signal input / output via each terminal is referred to by the same name as the terminal (for example, a signal input via the clock terminal CK is referred to as a clock signal CK).

The shift register 10 is supplied with a start pulse ST and two-phase clock signals CK and CKB (inverted signal of CK) (enable signal) from the outside. The start pulse ST is given to the IN terminal of the first stage unit circuit 11a. The clock signal CK is supplied to the CKa terminal of the odd-numbered unit circuit 11a and to the CKb terminal of the even-numbered unit circuit 11a. The clock signal CKB is supplied to the CKb terminal of the odd-numbered unit circuit 11a and to the CKa terminal of the even-numbered unit circuit 11a. The output signal O of the unit circuit 11a is output from the OUT terminal to the outside and is input to the IN terminal of the next stage unit circuit 11a.

Specifically, as shown in FIG. 2, in the second stage unit circuit 11a of the shift register 10, the output signal O1 of the first stage unit circuit 11a is input to the IN terminal, and the clock signal CKB is input to the CKa terminal. The clock signal CK is supplied to the CKb terminal. The output signal O2 of the second stage unit circuit 11a is output from the OUT terminal to the outside and is input to the IN terminal of the third stage unit circuit 11a. Thus, the shift register 10 sequentially outputs the output signals O1 to On by the shift operation.

Hereinafter, a detailed configuration of the shift register 10 will be described.

Example 1
FIG. 1 is a circuit diagram of a unit circuit 11a of the shift register 10 according to the first embodiment. As shown in FIG. 1, the unit circuit 11a includes a latching inverter INV1 (first inverter) / INV2 (second inverter), a data input unit SW1, and an output inverter INV3. In the latch inverter INV2, the connection point between the output terminal of the latch inverter INV1 and the input terminal of the latch inverter INV2 is a node N1 (first connection point), and the input terminal of the latch inverter INV1 and the latch inverter INV2 A connection point with the output terminal is referred to as a node N2.

The data input unit SW1 includes an N-channel transistor T1 (first transistor) and a P-channel transistor T2. The transistor T1 has a gate terminal connected to the CKa terminal, a source terminal connected to the IN terminal, and a transistor T2. The gate terminal is connected to the CKb terminal and the source terminal is connected to the IN terminal. The output signal O of the shift register unit circuit 11a is input to the IN terminal.

The latching inverter INV2 includes a P-channel transistor T3 (fourth transistor) and an N-channel transistor T4 (fifth transistor). The latching inverter INV2 has an input terminal (the gate terminal of the transistor T3 and the gate of the transistor T4). A connection point with the terminal (node N1) is connected to an output terminal of the data input section SW1 (drain terminals of the transistors T1 and T2). The power supply voltage Vdd (high potential) is applied to the source terminal of the transistor T3, and the drain terminal of the transistor T3 is the connection point (node) between the output terminal of the latch inverter INV2 (the drain terminal of the transistor T3 and the drain terminal of the transistor T4). N2)), the power supply voltage Vss (low potential) is applied to the source terminal of the transistor T4, and the drain terminal of the transistor T4 is connected to the output terminal (node N2) of the latching inverter INV2. The node N2 is connected to the OUT terminal via the output inverter INV3, and is also connected to the input terminal of the latching inverter INV1 (gate terminals of the transistors T5 and T6).

The latching inverter INV1 includes a P-channel transistor T5 (second transistor) and an N-channel transistor T6 (third transistor). The input terminal of the latching inverter INV1 (the gate terminals of the transistors T5 and T6) is latched. Connected to the output terminal (node N2) of the inverter INV2. The source voltage Vdd is applied to the source terminal of the transistor T5, and the drain terminal of the transistor T5 is connected to the output terminal of the latching inverter INV1 (the connection point between the drain terminal of the transistor T5 and the drain terminal of the transistor T6). The source voltage Vss is applied to the source terminal of the transistor T6, and the drain terminal of the transistor T6 is connected to the output terminal of the latching inverter INV1. The output terminal of the latching inverter INV1 is connected to the input terminal (node N1) of the latching inverter INV2. The output terminal (node N2) of the latching inverter INV2 is connected to the input terminal of the output inverter INV3, and the output terminal of the output inverter INV3 is connected to the output terminal OUT of the unit circuit 11a.

Accordingly, the output signal O (k−1) of the (k−1) th unit circuit 11a is input to the IN terminal of the kth unit circuit 11a, and the output terminal of the kth unit circuit 11a. An output signal Ok is output from OUT.

Here, the channel lengths L of the transistors T5 and T6 are set to be longer than the channel lengths L of the transistors T3 and T4 so that the driving capabilities of the transistors T5 and T6 are smaller than those of the transistors T3 and T4. That is, the latching inverter INV1 is set to have a driving capability lower than that of the input signal O (output inverter INV3) (holding target signal).

Hereinafter, unless otherwise specified, the internal signal of the unit circuit 11a including the clock signals CK, CKB, CK1, and CK2 and the potential of the input / output signal are assumed to be Vdd when the signal is high and Vss when the signal is low. The “high level” in the input signal O input to the IN terminal is higher than the inversion potential of the latching inverter INV2, and the “low level” is lower than the inversion potential of the latching inverter INV2.

(About operation)
The operation of the shift register 10 will be described with reference to FIGS. FIG. 3 is a timing chart at the time of operation of the shift register 10, and FIG. 4 is a diagram schematically showing a timing chart at the time of operation of the shift register 10. In FIG. 3, input / output in the first stage unit circuit 11a, the second stage unit circuit 11a, the third stage unit circuit 11a, the (n-1) th stage unit circuit 11a, and the nth stage unit circuit 11a. The signal is shown.

CK is a clock signal supplied to the CKa terminal of the odd-numbered unit circuit 11a and to the CKb terminal of the even-numbered unit circuit 11a, and CKB is connected to the CKb terminal of the odd-numbered unit circuit 11a. The clock signal is supplied to the CKa terminal of the even-numbered unit circuit 11a. ST is a start pulse input to the IN terminal of the first stage unit circuit 11a. O1, O2, O3, O (n-1), On are the outputs of the first, second, third, (n-1) th, and nth stage unit circuits 11a of the shift register, respectively. It shows the potential of the signal.

First, the operation of the unit circuit 11a at the first stage will be described.

First, after the start pulse ST (high level (active)) is input to the IN terminal of the first stage unit circuit 11a, the clock signal CK is at the high level at time t1 (hereinafter referred to as t1). Then, the data input unit SW1 is turned on, and the start pulse ST (high level; Vdd) is input to the node N1.

Here, immediately before the clock signal CK becomes high level, the potential of the node N1 is held at Vss (low level), and the transistor T6 is turned on. Therefore, when the clock signal CK becomes high level (t1) ), Vdd (high level) of the start pulse ST and the power source VSS (low level) (low potential side power source) are short-circuited. In this respect, since the transistor T6 of the latching inverter INV1 is set to have a long channel length L and has a low driving capability, the potential of the node N1 is drawn to the start pulse ST side and becomes the Vdd (high level) of the start pulse ST. It rises to a near potential (a potential higher than the inversion potential of the latching inverter INV2) (see FIG. 4).

Thereafter, the transistor T4 is turned on, and the output of the latching inverter INV2 (node N2; Vss (low level)) is fed back to the input terminal of the latching inverter INV1, so that the transistor T6 is turned off, and the transistor T5 is turned on. As a result, the potential of the node N1 rises from a potential close to Vdd of the start pulse ST to Vdd (see FIG. 4).

When the potential of the node N1 becomes close to Vdd (high level) or Vdd (high level), the transistor T4 of the latching inverter INV2 is turned on and the transistor T3 is turned off. When the transistor T4 is turned on, the potential of the node N2 becomes Vss (low level), and Vss (low level) is output from the latching inverter INV2. Then, an output signal O1 of Vdd (high level) is output via the output inverter INV3.

Subsequently, when the clock signal CK changes from the high level to the low level (t2), the data input unit SW1 is turned off, the input of the start pulse ST is cut off, and the node N1 is latched by the latch inverters INV1 and INV2. Thus, the potential (Vdd (high level)) held immediately before is held, and the output signal O1 maintains Vdd (high level).

Next, when the clock signal CK becomes high level (t3), the data input unit SW1 is turned on, and the start pulse ST (low level; Vss) is input to the node N1.

Here, immediately before the clock signal CK becomes high level, the potential of the node N1 is held at Vdd (high level), and the transistor T5 is in an on state. Therefore, when the clock signal CK becomes high level (t3 ), Vss (low level) of the start pulse ST and the power source VDD (high level) (high potential side power source) are short-circuited. In this respect, since the transistor T5 of the latching inverter INV1 has a long channel length L and a low driving capability, the potential of the node N1 is drawn to the start pulse ST side and becomes Vss (low level) of the start pulse ST. The voltage drops to a near potential (a potential lower than the inversion potential of the latching inverter INV2) (see FIG. 4).

Thereafter, the transistor T3 is turned on, and the output of the latching inverter INV2 (node N2; Vdd (high level)) is fed back to the input terminal of the latching inverter INV1, so that the transistor T5 is turned off, and the transistor T6 is turned on. As a result, the potential of the node N1 further decreases from a potential close to Vss of the start pulse ST to Vss (see FIG. 4).

When the potential of the node N1 becomes close to Vss (low level) or Vss (low level), the transistor T3 of the latching inverter INV2 is turned on and the transistor T4 is turned off. When the transistor T3 is turned on, the potential of the node N2 becomes Vdd (high level), and Vdd (high level) is output from the latching inverter INV2. Then, an output signal O1 of Vss (low level) is output via the output inverter INV3.

Subsequently, when the clock signal CK changes from the high level to the low level (t4), the data input unit SW1 is turned off, the input of the start pulse ST is cut off, and the node N1 is latched by the latch inverters INV1 and INV2. Thus, the potential (Vss (low level)) held immediately before is held, and the output signal O1 maintains Vss (low level). Thereafter, the unit circuit 11a repeats the above operations t3 and t4 until the start pulse ST becomes high level, and the output signal O1 maintains Vss (low level).

Next, the operation of the second stage unit circuit 11a will be described.

First, after the output signal O1 (high level (active)) of the first stage unit circuit 11a is input as the input signal O1 to the IN terminal of the second stage unit circuit 11a, the clock signal CKB is supplied at t2. When the level is high, the data input unit SW1 is turned on, and the input signal O1 (high level; Vdd) is input to the node N1.

Here, immediately before the clock signal CKB becomes high level, the potential of the node N1 is held at Vss (low level), and the transistor T6 is turned on. Therefore, when the clock signal CKB becomes high level (t2 ), Vdd (high level) of the input signal O1 and the power supply VSS (low level) are short-circuited. In this regard, since the transistor T6 of the latching inverter INV1 has a long channel length L and low driving capability, the potential of the node N1 is pulled to the input signal O1 side and becomes Vdd (high level) of the input signal O1. It rises to a near potential (a potential higher than the inversion potential of the latching inverter INV2) (see FIG. 4).

Thereafter, the transistor T4 is turned on, and the output of the latching inverter INV2 (node N2; Vss (low level)) is fed back to the input terminal of the latching inverter INV1, so that the transistor T6 is turned off, and the transistor T5 is turned on. As a result, the potential of the node N1 rises from a potential close to Vdd of the input signal O1 to Vdd (see FIG. 4).

When the potential of the node N1 becomes close to Vdd (high level) or Vdd (high level), the transistor T4 of the latching inverter INV2 is turned on and the transistor T3 is turned off. When the transistor T4 is turned on, the potential of the node N2 becomes Vss (low level), and Vss (low level) is output from the latching inverter INV2. Then, an output signal O2 of Vdd (high level) is output via the output inverter INV3.

Subsequently, when the clock signal CKB changes from the high level to the low level (t3), the data input unit SW1 is turned off, the input of the input signal O1 is cut off, and the node N1 is latched by the latching inverters INV1 and INV2. Thus, the potential (Vdd (high level)) held immediately before is held, and the output signal O2 maintains Vdd (high level).

Next, when the clock signal CKB becomes high level (t4), the data input unit SW1 is turned on, and the input signal O1 (low level; Vss) is input to the node N1.

Here, immediately before the clock signal CKB becomes high level, the potential of the node N1 is held at Vdd (high level), and the transistor T5 is in an on state. Therefore, when the clock signal CKB becomes high level (t4 ), Vss (low level) of the input signal O1 and the power supply VDD (high level) are short-circuited. In this respect, since the transistor T5 of the latching inverter INV1 has a long channel length L and a low driving capability, the potential of the node N1 is drawn to the input signal O1 side and becomes Vss (low level) of the input signal O1. The voltage drops to a near potential (a potential lower than the inversion potential of the latching inverter INV2).

Thereafter, the transistor T3 is turned on, and the output of the latching inverter INV2 (node N2; Vdd (high level)) is fed back to the input terminal of the latching inverter INV1, so that the transistor T5 is turned off, and the transistor T6 is turned on. As a result, the potential of the node N1 further decreases from the potential close to Vss of the input signal O1 to Vss.

When the potential of the node N1 becomes close to Vss (low level) or Vss (low level), the transistor T3 of the latching inverter INV2 is turned on and the transistor T4 is turned off. When the transistor T3 is turned on, the potential of the node N2 becomes Vdd (high level), and Vdd (high level) is output from the latching inverter INV2. Then, an output signal O2 of Vss (low level) is output via the output inverter INV3.

Subsequently, when the clock signal CKB changes from the high level to the low level (t5), the data input unit SW1 is turned off, the input of the input signal O1 is cut off, and the node N1 is latched by the latching inverters INV1 and INV2. Thus, the potential (Vss (low level)) held immediately before is held, and the output signal O2 maintains Vss (low level). Thereafter, the unit circuit 11a repeats the operations at t4 and t5 until the input signal O1 becomes high level, and the output signal O2 maintains Vss (low level).

In the unit circuit 11a of the first embodiment, the number of transistors can be reduced as compared with the conventional unit circuit (D-type flip-flop DFF) shown in FIG. Therefore, the circuit scale of the shift register 10 can be reduced. In addition, there is no problem of operation due to the reduction in circuit scale. Further, it is possible to reduce a through current generated at the moment when the input signal and the power supply are short-circuited.

Here, in the configuration shown in FIG. 1, the channel lengths L of the transistors T5 and T6 are individually increased. However, the present invention is not limited to this. For example, a plurality of stages of transistors are connected in series, and The channel length L may be substantially increased by connecting the gate terminals to each other.

Further, in order to make the drive capability of the output inverter INV3 larger than the drive capability of the inverter INV1, the channel width W of the transistors constituting the output inverter INV3 is changed to the transistor T5 without changing the channel length L of the transistors T5 and T6. , It may be larger than the channel width W of T6. According to this configuration, since the drive capability of the input signal of the unit circuit 11a can be increased, the same effect as the unit circuit 11a can be obtained. The start pulse ST is used as an output of a buffer having a channel width W larger than that of the transistors T5 and T6 of the latch inverter INV1 outside the shift register 10, or an output of an IC having a high drive capability, thereby increasing the drive capability. be able to.

Next, another form of the shift register 10 according to the first embodiment will be described. In the following description, differences from the shift register 10 according to the first embodiment will be mainly described. Components having the same functions as those described in the first embodiment have the same numbers. The description is omitted.

(Example 2)
FIG. 5 is a circuit diagram of the unit circuit 12a included in the shift register 10 according to the second embodiment. As shown in FIG. 5, in the latching inverter INV1a of the unit circuit 12a, resistors R1 (first resistor) and R2 (second resistor) are added to the latching inverter INV1 of the unit circuit 11a (see FIG. 1) according to the first embodiment. ) Has been added. The channel length L of the transistors T5 and T6 constituting the latching inverter INV1a of the unit circuit 12a is set to be the same as the channel length L of the transistors T3 and T4 constituting the latching inverter INV2.

In the latch inverter INV1a, the resistor R2 has one terminal connected to the power supply VDD, the other terminal connected to the source terminal of the transistor T5, and the resistor R1 has one terminal connected to the power supply VSS and the other terminal. Is connected to the source terminal of the transistor T6. The resistors R1 and R2 are several kΩ to several MΩ.

(About operation)
The operation of the shift register 10 will be described. The timing chart is the same as FIG. Here, the operation in the unit circuit 12a at the first stage will be described as an example, and the difference from the first embodiment will be mainly described.

First, when the start pulse ST (high level (active)) is input to the IN terminal of the first stage unit circuit 12a and the clock signal CK becomes high level (t1), the start pulse ST (high level; Vdd) is generated. Input to node N1.

Here, immediately before the clock signal CK becomes high level, the potential of the node N1 is held at Vss (low level), and the transistor T6 is turned on. Therefore, when the clock signal CK becomes high level (t1) ), Vdd (high level) of the start pulse ST and the power source VSS (low level) are short-circuited. In this regard, in the unit circuit 12a, since the resistor R1 is provided between the power supply VSS and the node N1, the potential of the node N1 is drawn to the start pulse ST side and becomes Vdd (high level) of the start pulse ST. It rises to a near potential (a potential higher than the inversion potential of the latching inverter INV2) (see FIG. 4).

Here, immediately before the clock signal CK becomes high level, the potential of the node N1 is held at Vdd (high level), and the transistor T5 is in an on state. Therefore, when the clock signal CK becomes high level (t3 ), Vss (low level) of the start pulse ST and the power supply VDD (high level) are short-circuited. In this respect, since the resistor R2 is provided between the power supply VDD and the node N1, the potential of the node N1 is drawn to the start pulse ST side and is a potential close to Vss (low level) of the start pulse ST (for latching). The potential drops to a potential lower than the inversion potential of the inverter INV2 (see FIG. 4).

Subsequently, when the clock signal CK changes from the high level to the low level (t4), the data input unit SW1 is turned off, the input of the start pulse ST is cut off, and the node N1 is latched by the latch inverters INV1 and INV2. Thus, the potential (Vss (low level)) held immediately before is held, and the output signal O1 maintains Vss (low level). Thereafter, the unit circuit 11 repeats the operations of t3 and t4 until the start pulse ST becomes high level, and the output signal O1 maintains Vss (low level).

Thereby, the same effect as in the first embodiment can be obtained. In the second embodiment, a resistor is used. Since the shape of the resistors can be freely deformed, the resistors can be laid out efficiently and the circuit scale can be further reduced. Further, it is possible to reduce a through current generated at the moment when the input signal and the power supply are short-circuited.

(Example 3)
FIG. 6 is a circuit diagram of the unit circuit 13a included in the shift register 10 according to the third embodiment. As shown in FIG. 6, in the latching inverter INV1b of the unit circuit 13a, the positions of the resistors R1 and R2 are different from those of the latching inverter INV1a of the unit circuit 12a according to the second embodiment (see FIG. 5). .

Specifically, in the latch inverter INV1b, the resistor R2 has one terminal connected to the drain terminal of the transistor T5, the other terminal connected to the node N1, and the resistor R1 having one terminal connected to the drain of the transistor T6. The other terminal is connected to the node N1.

According to this configuration, even when the clock signal CK becomes high level and the input signal Vdd (high level) and the power source VSS (low level) are short-circuited, as in the second embodiment, the power source VSS Since the resistor R1 is provided between the node N1 and the node N1, the potential of the node N1 is drawn to the input signal side and is close to Vdd (high level) (potential higher than the inversion potential of the latch inverter INV2) And then rises to Vdd by feedback of the output (Vss) of the latching inverter INV2. Even if the input signal Vss (low level) and the power supply VDD (high level) are short-circuited, since the resistor R2 is provided between the power supply VDD and the node N1, the potential of the node N1 Is pulled to the input signal side and drops to a potential close to Vss (a potential lower than the inversion potential of the latching inverter INV2), and then lowered to Vss by feedback of the output (Vdd) of the latching inverter INV2.

Thereby, the same effect as in the second embodiment can be obtained. In FIG. 6, a resistor may be added to the source terminal side of the transistors T5 and T6 (see FIG. 5).

(Example 4)
FIG. 7 is a circuit diagram of the unit circuit 14a included in the shift register 10 according to the fourth embodiment. As shown in FIG. 7, in the unit circuit 14a, between the output terminal of the latch inverter INV1 of the unit circuit 11 (see FIG. 1) according to the first embodiment and the input terminal (node N1) of the latch inverter INV2. A resistor R3 is added. The channel length L of the transistors T5 and T6 constituting the latching inverter INV1 of the unit circuit 14a is set to be the same as the channel length L of the transistors T3 and T4 constituting the latching inverter INV2.

Specifically, one terminal of the resistor R3 is connected to the output terminal of the latching inverter INV1 (the connection point between the drain terminal of the transistor T5 and the drain terminal of the transistor T6), and the other terminal is connected to the latching inverter INV2. To the input terminal (node N1). The resistor R3 is several kΩ to several MΩ.

According to this configuration, similarly to the second and third embodiments, even when the clock signal CK becomes high level and the input signal Vdd (high level) and the power source VSS (low level) are short-circuited, Since the resistor R3 is provided between the power supply VSS and the node N1, the potential of the node N1 is drawn to the input signal side and is close to Vdd (high level) (higher than the inverted potential of the latch inverter INV2) Potential), and then increases to Vdd by feedback of the output (Vss) of the latching inverter INV2. Even if the input signal Vss (low level) and the power supply VDD (high level) are short-circuited, since the resistor R3 is provided between the power supply VDD and the node N1, the potential of the node N1 Is pulled to the input signal side and drops to a potential close to Vss (a potential lower than the inversion potential of the latching inverter INV2), and then lowered to Vss by feedback of the output (Vdd) of the latching inverter INV2.

Thereby, the same effect as in the second embodiment can be obtained.

(Example 5)
FIG. 8 is a circuit diagram of the unit circuit 15a included in the shift register 10 according to the fifth embodiment, and FIG. 9 is a block diagram illustrating a schematic configuration of the shift register 10 according to the fifth embodiment.
As shown in FIG. 8, in the unit circuit 15a, in the unit circuit 12a according to the second embodiment (see FIG. 5), the data input unit SW1a is configured by only the N-channel transistor T1.

Specifically, the transistor T1 of the data input unit SW1a has a gate terminal connected to the CK terminal (see FIG. 9) of the unit circuit 15a, a source terminal connected to the IN terminal of the unit circuit 15a, and a drain terminal connected to the node N1. It is connected to the.

In this configuration, when the clock signal CK becomes high level, the data input unit SW1a is turned on.

When the input signal is at a high level (Vdd), the potential of the node N1 becomes Vdd−Vth (threshold). Here, even if the input signal Vdd−Vth and the power supply VSS (low level) are short-circuited, the resistor R1 is provided between the power supply VSS and the node N1, so the potential of the node N1 is Then, it is pulled to the input signal side and rises to a potential close to Vdd−Vth (potential higher than the inversion potential of the latching inverter INV2), and then rises to Vdd by feedback of the output (Vss) of the latching inverter INV2.

On the other hand, when the input signal is at a low level (Vss), the potential of the node N1 is Vss. Here, even if the low level (Vss) of the input signal and the power supply VDD (high level) are short-circuited, since the resistor R2 is provided between the power supply VDD and the node N1, the node N1 The potential is drawn to the input signal side and drops to a potential close to Vss (low level) (potential lower than the inversion potential of the latching inverter INV2), and then Vss is obtained by feedback of the output (Vdd) of the latching inverter INV2. To drop.

Here, when the input signal is at the high level (Vdd), the output of the data input unit SW1a becomes Vdd-Vth, and thus the transistor T1 has a relatively high resistance. For this reason, the potential of the node N1 is difficult to rise, and the operation delay and the operation margin are reduced. Therefore, in the unit circuit 15a, the resistance value of the resistor R1 is increased (or the channel length L of the transistor T6 of the latching inverter INV1a is increased to reduce the driving capability), and the latching is performed to lower the inversion potential of the latching inverter INV2. It is preferable that the size of the transistor T4 of the inverter INV2 is increased.

When an inverted signal of the clock signal CK is input, for example, in FIG. 9, when the clock signals CK and CKB of FIG. 3 are inverted and input (replaced), the data input unit SW1a is set to P What is necessary is just to comprise by channel type transistor T2 (refer FIG. 5).

Thereby, the same effect as in the second embodiment can be obtained. In the fifth embodiment, since the data input unit SW1a is composed of only the transistor T1, the number of elements can be further reduced, and the circuit scale can be further reduced.

(Example 6)
FIG. 10 is a circuit diagram of the unit circuit 16a included in the shift register 10 according to the sixth embodiment. As shown in FIG. 10, in the latch inverter INV1b of the unit circuit 16a, the positions of the resistors R1 and R2 are different from those of the latch inverter INV1a of the unit circuit 15a according to the fifth embodiment (see FIG. 8). .

According to this configuration, similarly to the fifth embodiment, even when the clock signal CK becomes a high level and the input signal Vdd−Vth and the power supply VSS (low level) are short-circuited, the power supply VSS and the node Since the resistor R1 is provided between N1 and N1, the potential of the node N1 is drawn to the input signal side and rises to a potential close to Vdd−Vth (potential higher than the inversion potential of the latch inverter INV2), Thereafter, the voltage rises to Vdd by feedback of the output (Vss) of the latching inverter INV2.

Even if the low level (Vss) of the input signal and the power supply VDD (high level) are short-circuited, since the resistor R2 is provided between the power supply VDD and the node N1, the potential of the node N1 Is pulled to the input signal side and drops to a potential close to Vss (low level) (potential lower than the inversion potential of the latching inverter INV2), and then to Vss by feedback of the output (Vdd) of the latching inverter INV2. descend.

Thereby, the same effect as in the fifth embodiment can be obtained.

(Example 7)
FIG. 11 is a circuit diagram of the unit circuit 17a included in the shift register 10 according to the seventh embodiment. As shown in FIG. 11, the unit circuit 17a has a configuration in which an N-channel transistor T9 and a capacitor C1 are added to the data input unit SW1a of the unit circuit 15a according to the fifth embodiment (see FIG. 8). Yes.

Specifically, in the data input unit SW1b of the unit circuit 17a, the power supply voltage Vdd is applied to the gate terminal of the transistor T9, the source terminal is connected to the CK terminal, and the drain terminal is connected to the gate terminal of the transistor T1. . The capacitor C1 is provided between the gate terminal and the drain terminal of the transistor T1. Note that a connection point between the capacitor C1 and the gate terminal of the transistor T1 is a node N3.

In this configuration, when the clock signal CK becomes high level, the potential of the node N3 is charged to Vdd-Vth, and then the transistor T9 is turned off. At the node N1, the transistor T1 is turned on by the clock signal CK (high level), the input signal Vdd (high level) is input, and starts to rise from Vss (low level) to Vdd (high level). Then, the potential of the node N3 is pushed up to Vdd−Vth + α through the capacitor C1 due to the potential fluctuation of the node N1. As a result, the input signal (Vdd) is input without dropping the threshold value (Vth), and the potential of the node N1 becomes Vdd (bootstrap operation).

Here, in the unit circuit 15a of the fifth embodiment, when the input signal is at the high level (Vdd), the potential of the node N1 becomes Vdd−Vth until the output (Vss) of the latching inverter INV2 is fed back. On the other hand, in the unit circuit 17a of the seventh embodiment, the potential of the node N1 can be set to Vdd by the bootstrap operation, so that an operation margin can be ensured. Operations other than those described above are the same as those of the unit circuit 15a of the fifth embodiment.

Note that when an inverted signal of the clock signal CK is input, for example, in FIG. 9, when the clock signals CK and CKB of FIG. What is necessary is just to comprise a channel type transistor and to fix a power supply to VSS.

(Example 8)
FIG. 12 is a circuit diagram of the unit circuit 18a included in the shift register 10 according to the eighth embodiment. As shown in FIG. 12, in the latch inverter INV1b of the unit circuit 18a, the positions of the resistors R1 and R2 are different from those of the latch inverter INV1a of the unit circuit 17a according to the seventh embodiment (see FIG. 11). .

Specifically, in the latch inverter INV1b, the resistor R2 has one terminal connected to the drain terminal of the transistor T5, the other terminal connected to the node N1, and the resistor R1 having one terminal connected to the drain of the transistor T6. The other terminal is connected to the node N1. The operation of the unit circuit 18a is the same as that of the unit circuit 17a of the seventh embodiment.

Example 9
FIG. 13 is a circuit diagram of the unit circuit 19a included in the shift register 10 according to the ninth embodiment. As shown in FIG. 13, in the latching inverter INV1c of the unit circuit 19a, a resistor R1 and a P-channel transistor T10 are added to the latching inverter INV1 of the unit circuit 11a (see FIG. 1) according to the first embodiment. . The channel length L of the transistors T5, T6, and T10 that constitute the latching inverter INV1c of the unit circuit 19a is set to be the same as the channel length L of the transistors T3 and T4 that constitute the latching inverter INV2.

In the latch inverter INV1c, the transistor T10 has a gate terminal connected to the CK terminal and a source terminal connected to the power supply VDD. The transistor T5 has a gate terminal connected to the node N2, a source terminal connected to the drain terminal of the transistor T10, and a drain terminal connected to the node N1. One terminal of the resistor R1 is connected to the power supply VSS. The transistor T6 has a gate terminal connected to the node N2, a source terminal connected to the other terminal of the resistor R1, and a drain terminal connected to the node N1, and the resistor R1 is several kΩ to several MΩ. .

In this configuration, when the clock signal CK goes high, the data input unit SW1 is turned on and the transistor T10 is turned off.

When a high level (Vdd) input signal is input in this state, the input signal (Vdd) and the power supply VSS are short-circuited, but a resistor R1 is provided between the power supply VSS and the node N1. Therefore, the potential of the node N1 is drawn to the input signal side, rises to a potential close to Vdd (potential higher than the inversion potential of the latching inverter INV2), and then feedback of the output (Vss) of the latching inverter INV2 Rises to Vdd.

On the other hand, when a low level (Vss) input signal is input, the potential of the node N1 held at Vdd is disconnected from the power supply VDD by turning off the transistor T10, and thus the input signal and the power supply VDD are short-circuited. Without being reduced to Vss.

(Example 10)
FIG. 14 is a circuit diagram of the unit circuit 20a included in the shift register 10 according to the tenth embodiment. As shown in FIG. 14, in the latching inverter INV1d of the unit circuit 20a, a resistor R2 and an N-channel transistor T11 are added to the latching inverter INV1 of the unit circuit 11 (see FIG. 1) according to the first embodiment. . The channel length L of the transistors T5, T6, and T11 that constitute the latching inverter INV1d of the unit circuit 20a is set to be the same as the channel length L of the transistors T3 and T4 that constitute the latching inverter INV2.

In the latch inverter INV1d, the resistor R2 has one terminal connected to the power supply VDD, the transistor T5 has a gate terminal connected to the node N2, a source terminal connected to the other terminal of the resistor R2, and a drain terminal connected to the node. Connected to N1. The transistor T11 has a gate terminal connected to the CKB terminal and a source terminal connected to the power supply VSS. The transistor T6 has a gate terminal connected to the node N2, a source terminal connected to the drain terminal of the transistor T11, and a drain terminal connected to the node N1. The resistor R1 is several kΩ to several MΩ.

In this configuration, when the clock signal CK is at a high level and the clock signal CKB is at a low level, the data input unit SW1 is turned on and the transistor T11 is turned off.

When a high level (Vdd) input signal is input in this state, the potential of the node N1 held at Vss is disconnected from the power supply VSS by turning off the transistor T11. It rises to Vdd without short-circuiting.

On the other hand, when a low level (Vss) input signal is input, the input signal (Vss) and the power supply VDD are short-circuited, but a resistor R2 is provided between the power supply VDD and the node N1. The potential of the node N1 is drawn to the input signal side and drops to a potential close to Vss (potential higher than the inversion potential of the latching inverter INV2), and then Vss by feedback of the output (Vdd) of the latching inverter INV2. To drop.

(Example 11)
FIG. 15 is a circuit diagram of the unit circuit 21a included in the common electrode driving circuit 200 according to the eleventh embodiment. In the inverter INV1 of the unit circuit 21a, the sizes (channel length L, channel width W) of the transistors T5, T6 constituting the inverter INV1 are the same as the sizes (channel length L, channel width W) of the transistors T3, T4 constituting the inverter INV2. Are set the same. That is, all the transistors constituting the inverters INV1 and INV2 are set to the same size. In the unit circuit 21a, the driving capability of the input signal input to the IN terminal is set to be high. Specifically, for example, in order to increase the driving capability, the channel width W of the inverter INV3 (buffer) is configured to be larger than the channel width W size of the inverter INV1.

According to this configuration, even if the clock signal CK becomes high level (active) and the input signal Vss (low level) and the power supply VDD (high level) are short-circuited, the input signal drive capability Therefore, the potential of the node N1 is drawn to the input signal side, drops to a potential close to Vss (low level) of the input signal (potential lower than the inversion potential of the inverter INV2), and then the output of the inverter INV2 ( Vdd) is reduced to Vss by feedback. Even if the input signal Vdd (high level) and the power source VSS (low level) are short-circuited, the input signal drive capability is similarly high, so that the potential of the node N1 is pulled to the input signal side. Then, it rises to a potential close to Vdd of the input signal (potential higher than the inversion potential of the inverter INV2), and then rises to Vdd by feedback of the output (Vss) of the inverter INV2.

Thereby, it is possible to obtain the same effect as in the first embodiment. Further, the configuration of the present embodiment can also be applied to the above-described embodiments.

Example 12
FIG. 16 is a circuit diagram of the unit circuit 22a of the shift register 10 according to the twelfth embodiment, and FIG. 17 is a timing chart when the shift register 10 operates.

In the unit circuit 22a, the output inverter INV3 is omitted in the unit circuit 11a of the first embodiment, and the output of the inverter INV2 is connected to the OUT terminal. Thereby, since the number of elements can be reduced, the circuit scale of the shift register 10 can be further reduced. In the unit circuit 33, since the output inverter INV3 is omitted, as shown in FIG. 17, the polarity of the output signal O is reversed between the odd and even stages.

The configuration in which the output inverter INV3 in this embodiment is omitted can be applied to the above-described embodiments.

(Example 13)
FIG. 18 is a circuit diagram of the unit circuit 23a included in the shift register 10 according to the thirteenth embodiment. FIG. 19 is a timing chart when the shift register 10 operates.

In the unit circuit 23a, instead of omitting the output inverter INV3 in the unit circuit 11a of the first embodiment, an inverter INV4 is provided, the input terminal of the inverter INV4 is connected to the CK terminal, and the output terminal of the inverter INV4 is It is connected to the gate terminal of the transistor T2. CK1 is a clock signal supplied to the CK terminal of the odd-numbered unit circuit 23a, and CK2 is a clock signal supplied to the CK terminal of the even-numbered unit circuit 23a. The clock signals CK1 and CK2 each have a duty ratio smaller than 50% and are set so that the active periods (high periods) do not overlap each other.

Here, when each of the clock signals CK1 and CK2 has a duty ratio of 50% (that is, in the case of CK and CKB), both of the clock signals CK1 and CK2 are affected by the influence of the wiring load during the switching period of CK and its inverted signal CKB. In some cases, the transistor is in an active state where it is turned on. In this case, there is a possibility that the data input unit SW1 is switched on at all stages of the shift register and erroneous input of data called latch through occurs. In this respect, according to the configuration of the present embodiment, the active periods of the clock signals CK1 and CK2 do not overlap each other, so that the latch-through phenomenon can be prevented.

In the unit circuit 23a, in order to make the driving capability of the latching inverter INV2 larger than that of the inverter INV1, the transistor T3 constituting the latching inverter INV2 without changing the channel length L of the transistors T5 and T6. , T4 has a channel width W larger than that of the transistors T5, T6. Further, the start pulse ST is output from a buffer having a channel width W larger than that of the transistors T5 and T6 of the latching inverter INV1 outside the shift register 10 or from an IC having a high driving capability. As a result, the drive capability of the input signal of the unit circuit 23a is enhanced, and the same effect as the unit circuit 11a and the like can be obtained. The above configuration can be applied to the following unit circuits.

(Example 14)
FIG. 20 is a circuit diagram of the unit circuit 24a of the shift register 10 according to the fourteenth embodiment.

In the unit circuit 24a, in the unit circuit 23a of the thirteenth embodiment, the inverter INV4 and the transistor T2 are omitted, and a transistor T9 and a capacitor C1 (bootstrap function shown in FIG. 11) are added.

This eliminates the need to generate inverted signals of the clock signals (CK1, CK2) in the unit circuit 24a, so that power consumption can be reduced compared to the unit circuit 13a of the thirteenth embodiment.

(Example 15)
FIG. 46 is a circuit diagram of the unit circuit 25a of the shift register 10 according to the fifteenth embodiment. Compared with the unit circuit 11a according to the first embodiment (see FIG. 1), the unit circuit 25a has the input terminal of the output inverter INV3 connected to the node N1, and the output signal OB (inverted signal of O) is input to the input terminal INc. The other configurations are the same as those of the unit circuit 11a.

According to this configuration, even when the clock signal CK becomes high level and the Vss (low level) of the input signal OB and the power supply VDD (high level) are short-circuited, the transistor T5 of the inverter INV1 is connected to the channel. Since the length L is set to be long and the driving capability is low, the potential of the node N1 is drawn to the input signal OB side and is a potential close to Vss (low level) of the input signal OB (a potential lower than the inversion potential of the inverter INV2). ) And then to Vss by feedback of the output (Vdd) of the inverter INV2. Even if Vdd (high level) of the input signal OB and the power supply VSS (low level) are short-circuited, the transistor T6 of the inverter INV1 is set to have a long channel length L and has a low driving capability. The potential of the node N1 is drawn to the input signal OB side, rises to a potential close to Vdd of the input signal OB (potential higher than the inversion potential of the inverter INV2), and then Vdd is fed back by feedback of the output (Vss) of the inverter INV2. To rise.

(Switching scanning direction)
Each unit circuit described above may include a switching circuit UDSW that switches the scanning direction (shift direction) of the shift register. FIG. 21 is a circuit diagram illustrating a connection relationship between the switching circuit UDSW and the k-th unit circuit 24a included in the shift register 10 according to the fourteenth embodiment. FIG. 22 illustrates a shift register including the switching circuit UDSW. 10 is a block diagram showing a schematic configuration of 10. FIG.

The switching circuit UDSW includes N-channel transistors Tu1 and Tu2. The transistor Tu1 has a source terminal connected to the input terminal INa, a drain terminal connected to the output terminal OUT, and a switching signal UD supplied to the gate terminal. The transistor Tu2 has a source terminal connected to the input terminal INb, a drain terminal connected to the output terminal OUT, and a gate signal supplied with a switching signal UDB (inverted signal of UD). The output terminal of the switching circuit UDSW is connected to the IN terminal of the unit circuit 24a. In the k-th unit circuit 24a, the output signal O (k-1) of the (k-1) -th unit circuit 24a of the shift register is input to the INa terminal of the switching circuit UDSW, and the INb terminal of the switching circuit UDSW The output signal O (k + 1) of the unit circuit 24a at the (k + 1) -th stage of the shift register is input.

Since the switching signals UD and UDB are signals whose polarities are reversed, when the switching signal UD is at a high level (the switching signal UDB is at a low level), the transistor Tu1 is turned on and the output signal O (k−1) ) Is input from the switching circuit UDSW to the k-th unit circuit 24a, the shift direction of the shift register 10 is the first from the first stage to the n-th stage as shown in FIG. Direction.

On the other hand, when the switching signal UDB is at a high level (the switching signal UD is at a low level), the transistor Tu2 is turned on and the output signal O (k + 1) is input from the switching circuit UDSW to the k-th unit circuit 24a. Therefore, the scanning direction of the shift register 10 is the second direction from the nth stage to the first stage, as shown in FIG. Thus, the scanning direction can be switched by the switching signals UD and UDB.

Note that, as shown in FIG. 24, the switching circuit UDSW may be composed of N-channel transistors Tu1, Tu2 and P-channel transistors Tu3, Tu4. The switching circuit UDSW can be applied to the above-described embodiments.

[Embodiment 2]
Embodiment 2 of the present invention will be described below with reference to the drawings. For convenience of explanation, members having the same functions as those shown in the first embodiment are given the same reference numerals, and explanation thereof is omitted. In addition, the terms defined in Embodiment 1 are used in accordance with the definitions in this example unless otherwise specified.

FIG. 25 is a block diagram illustrating a schematic configuration of the liquid crystal display device 1 according to the second embodiment, and FIG. 26 is an equivalent circuit diagram illustrating an electrical configuration of a pixel of the liquid crystal display device 1.

First, a schematic configuration of the liquid crystal display device 1 will be described with reference to FIGS. 25 and 26. FIG. The liquid crystal display device 1 includes a scanning signal line driving circuit 100 (gate driver), a data signal line driving circuit 300 (source driver), and a display panel 400. Further, the liquid crystal display device 1 includes a control circuit (not shown) that controls each drive circuit. Note that each drive circuit may be monolithically formed on the active matrix substrate.

The display panel 400 is configured by sandwiching a liquid crystal between an active matrix substrate (not shown) and a counter substrate, and has a large number of pixels P (FIG. 26) arranged in a matrix.

The display panel 400 includes a scanning signal line 41 (GLn), a data signal line 43 (SLi), a thin film transistor (hereinafter also referred to as “TFT”) 44, and a pixel electrode 45 on an active matrix substrate. A common line (common electrode wiring) 42 (CMLn) is provided on the counter substrate. I and n are integers of 2 or more.

One scanning signal line 41 is formed in each row so as to be parallel to each other in the row direction (lateral direction), and the data signal line 43 is arranged in each column so as to be parallel to each other in the column direction (vertical direction). One by one. As shown in FIG. 26, the TFT 44 and the pixel electrode 45 are formed corresponding to each intersection of the scanning signal line 41 and the data signal line 43, and the gate electrode g of the TFT 44 is connected to the scanning signal line 41 and the source. The electrode s is connected to the data signal line 43, and the drain electrode d is connected to the pixel electrode 45. Further, the pixel electrode 45 forms a capacitance Clc (including a liquid crystal capacitance) between the common line 42.

As a result, the gate of the TFT 44 is turned on by the gate signal (scanning signal) supplied to the scanning signal line 41, the source signal (data signal) from the data signal line 43 is written to the pixel electrode 45, and the pixel electrode 45 is written in the above-described manner. It is possible to realize gradation display according to the source signal by setting the potential according to the source signal and applying a voltage according to the source signal to the liquid crystal interposed between the common line 42. it can.

The display panel 400 having the above configuration is driven by the scanning signal line driving circuit 100, the data signal line driving circuit 300, and a control circuit for controlling them.

In this embodiment, in the active period (effective scanning period) in the vertical scanning period that is periodically repeated, the horizontal scanning period of each row is sequentially assigned, and each row is sequentially scanned.

Therefore, the scanning signal line driving circuit 100 sequentially outputs a gate signal for turning on the TFT 44 to the scanning signal line 41 of the row in synchronization with the horizontal scanning period of each row.

The data signal line driving circuit 300 outputs a source signal to each data signal line 43. This source signal is a signal obtained by assigning a video signal supplied to the data signal line driving circuit 300 from the outside of the liquid crystal display device 1 through the control circuit to each column in the data signal line driving circuit 300 and performing boosting or the like. is there.

The control circuit controls the scanning signal line driving circuit 100 and the data signal line driving circuit 300 described above to output a gate signal, a source signal, and a common signal from each of these circuits.

The scanning signal line driving circuit 100 includes the shift register 10 according to the first embodiment. The shift register 10 is configured by connecting n (n is an integer of 2 or more) SR unit circuits in multiple stages. The SR unit circuit has a clock terminal (CKa terminal, CKb terminal), an input terminal (IN terminal), and an output terminal (OUT1 terminal, OUT2 terminal).

The liquid crystal display device 1 according to the present embodiment has a configuration in which the circuit area is reduced and a stable operation is performed by preventing the potential level of the output signal of the scanning signal line driving circuit 100 from being lowered. Hereinafter, a specific configuration of the shift register included in the scanning signal line driver circuit 100 will be described.

(Example 15)
FIG. 27 is a block diagram illustrating a schematic configuration of the shift register 10 according to the fifteenth embodiment. In FIG. 27, a switching circuit UDSW is included. FIG. 28 is a circuit diagram of a first stage unit circuit (hereinafter referred to as SR unit circuit SR1) constituting the shift register 10, and FIG. 29 is a second stage unit circuit (hereinafter referred to as SR unit circuit SR1) constituting the shift register 10. It is a circuit diagram of SR unit circuit SR2.

SR unit circuit includes a latch circuit and a pulse output circuit. The unit circuit shown in each example of the first embodiment can be applied to the latch circuit.

In FIG. 28 and FIG. 29, the unit circuit 24a according to Example 14 of the first embodiment is shown as the latch circuit 24a. However, the present invention is not limited to this, and each unit circuit shown in the first embodiment is shown. A unit circuit can be applied. The pulse output circuit 24b includes a P-channel transistor Tr1 and N-channel transistors Tr2 and Tr3, but the connection relationship is different between the odd-numbered stage (FIG. 28) and the even-numbered stage (FIG. 29).

As shown in the SR unit circuit SR1 of FIG. 28, in the odd-numbered pulse output circuit 24b, the gate terminals of the transistors Tr1 and Tr3 and the output out (node N2) of the inverter INV2 are connected to each other, and the transistors Tr1, Tr2, Tr3 Is connected to the OUT2 terminal. The gate terminal of the transistor Tr2 is connected to the input (node N1) of the inverter INV2, the source terminals of the transistors Tr1 and Tr2 are connected to the CKb terminal, and the power supply voltage Vss is applied to the source terminal of the transistor Tr3.

As shown in the SR unit circuit SR2 of FIG. 29, in the even-numbered pulse output circuit, the gate terminals of the transistors Tr1 and Tr3 and the input (node N1) of the inverter INV2 are connected to each other, and the drains of the transistors Tr1, Tr2, and Tr3 The terminal is connected to the OUT2 terminal. The gate terminal of the transistor Tr2 is connected to the output out (node N2) of the inverter INV2 and the OUT1 terminal, the source terminals of the transistors Tr1 and Tr2 are connected to the CKb terminal, and the power supply voltage Vss is applied to the source terminal of the transistor Tr3. It is done.

The start pulse ST and the two-phase clock signals CK1 and CK2 are supplied to the shift register 10 from the outside (see FIGS. 25 and 27). The start pulse ST is applied to the IN terminal of the first-stage SR unit circuit SR1 via the first-stage switching circuit UDSW. The clock signal CK1 is supplied to the CKa terminal of the odd-numbered SR unit circuit (see FIG. 28) and to the CKb terminal of the even-numbered SR unit circuit (see FIG. 29). The clock signal CK2 is supplied to the CKb terminal of the odd-numbered SR unit circuit and to the CKa terminal of the even-numbered SR unit circuit. The output signal O1 of the first-stage latch circuit 24a is input to the pulse output circuit 24b and also output from the OUT1 terminal of the SR unit circuit SR1, and is output from the second-stage switching unit UDSW to the second-stage SR unit. The signal is input to the IN terminal of the circuit SR2. The output signal CKO1 output from the OUT2 terminal is supplied to the first-stage scanning signal line GL1 as SROUT1 (gate signal).

That is, as shown in FIG. 25, the (k−1) th SR unit circuit SR (k) is connected to the IN terminal of the SR unit circuit SRk of the kth stage (k is an integer of 1 to n) of the shift register 10. -1) output signal CKO (k-1) is input, and the k-th SR unit circuit SRk outputs the output signal CKOk (SROUTk) to the scanning signal line GLk. As described above, the shift register 10 sequentially outputs the output signals SROUT1 to SROUTn to the scanning signal lines GL1 to GLn by the shift operation.

(About operation)
The operation of the shift register 10 will be described with reference to FIG. FIG. 30 is a timing chart when the shift register 10 operates. In FIG. 30, the first SR unit circuit SR1, the second SR unit circuit SR2, the third SR unit circuit SR3, the (n−1) th SR unit circuit SR (n−1), n The input / output signals in the SR unit circuit SRn at the stage are shown.

The clock signal CK1 is supplied to the CKa terminal of the odd-numbered SR unit circuit and the CKb terminal of the even-numbered SR unit circuit, and the clock signal CK2 is supplied to the CKb terminal of the odd-numbered SR unit circuit. It is given to the CKa terminal of the SR unit circuit of the even-numbered stage. The clock signals CK1 and CK2 each have a duty ratio smaller than 50% and are set so that the active periods (high periods) do not overlap each other. ST is a start pulse input to the first-stage SR unit circuit SR1. O1, O2, O3, O (n-1), On are the SR unit circuits of the first, second, third, (n-1) th, and nth stages of the shift register 10, respectively. This indicates the potential of the output signal output from the OUT1 terminal, and CKO1, CKO2, CKO3, CKO (n−1), and CKOn are the first, second, third, and (n− 1) The potential of the output signal output from the OUT2 terminal of the SR unit circuit at the stage and the n-th stage is shown.

First, the operation of the first-stage SR unit circuit SR1 will be described.

First, after the start pulse ST (high level (active)) is input to the IN terminal of the SR unit circuit SR1, when the clock signal CK1 becomes high level at t1, the data input unit SW1 is turned on. A start pulse ST (high level; Vdd) is input to the node N1 (bootstrap operation).

Here, immediately before the clock signal CK1 becomes high level, the potential of the node N1 is held at Vss (low level), and the transistor T6 is turned on. Therefore, when the clock signal CK1 becomes high level (t1) ), Vdd (high level) of the start pulse ST and the power source VSS (low level) are short-circuited. In this regard, if the drive capability of the start pulse ST is high, the potential of the node N1 is drawn to the start pulse ST side and is close to Vdd (high level) of the start pulse ST (higher than the inversion potential of the latch inverter INV2). (See FIG. 4). The start pulse ST is used as an output of a buffer having a channel width W larger than that of the transistors T5 and T6 of the latch inverter INV1 outside the shift register 10, or an output of an IC having a high drive capability, thereby increasing the drive capability. be able to.

When the potential of the node N1 becomes close to Vdd (high level) or Vdd (high level), the transistor T4 of the latching inverter INV2 is turned on and the transistor T3 is turned off. When the transistor T4 is turned on, the potential of the node N2 becomes Vss (low level), and O1 becomes low level (Vss).

Further, since the node N1 is Vdd and the node N2 is Vss, the transistors Tr1 and Tr2 are turned on and the transistor Tr3 is turned off, and the low level (Vss) of CK2 is output as CKO1 from the OUT2 terminal.

Subsequently, when the clock signal CK1 changes from the high level to the low level (t2), the data input unit SW1 is turned off, the input of the start pulse ST is cut off, and the node N1 is latched by the latch inverters INV1 and INV2. Thus, the potential (Vdd (high level)) held immediately before is held, and O1 and CKO1 maintain Vss (low level).

Subsequently, when the clock signal CK2 becomes high level (t3), the transistors Tr1 and Tr2 are turned on, so that CKO1 becomes high level (Vdd) and when the clock signal CK2 becomes low level (t4). CKO1 becomes low level (Vss).

Next, when the clock signal CK1 becomes high level (t5), the data input unit SW1 is turned on again, and the start pulse ST (low level; Vss) is input to the node N1.

Here, immediately before the clock signal CK1 becomes high level, the potential of the node N1 is held at Vdd (high level), and the transistor T5 is turned on. Therefore, when the clock signal CK1 becomes high level (t5 ), Vss (low level) of the start pulse ST and the power supply VDD (high level) are short-circuited. In this respect, since the drive capability of the start pulse ST is high, the potential of the node N1 is drawn to the start pulse ST side and is close to Vss (low level) of the start pulse ST (lower than the inversion potential of the latch inverter INV2). (See FIG. 4).

When the potential of the node N1 becomes close to Vss (low level) or Vss (low level), the transistor T3 of the latching inverter INV2 is turned on and the transistor T4 is turned off. When the transistor T3 is turned on, the potential of the node N2 becomes Vdd (high level), and O1 becomes high level (Vdd).

Further, since the node N1 is Vss and the node N2 is Vdd, the transistors Tr1 and Tr2 are turned off, the transistor Tr3 is turned on, and CKO1 is set to a low level (Vss).

Subsequently, when the clock signal CK1 changes from the high level to the low level (t6), the data input unit SW1 is turned off, the input of the start pulse ST is cut off, and the node N1 is latched by the latch inverters INV1 and INV2. Holds the potential (Vss (low level)) held immediately before, O1 maintains Vdd (high level), and CKO1 maintains Vss (low level). Thereafter, the SR unit circuit SR1 maintains Odd at Vdd (high level) and CKO1 at Vss (low level) until the start pulse ST becomes high level.

Next, the operation of the second-stage SR unit circuit SR2 will be described.

First, after the output O1 (low level) of the first stage SR unit circuit SR1 is input to the IN terminal of the second stage SR unit circuit SR2, when the clock signal CK2 becomes high level at t3, the data The input unit SW1 is turned on, and O1 (low level; Vss) is input to the node N1.

Thereby, when the potential of the node N1 becomes close to Vss (low level) or Vss (low level), the transistor T3 of the latching inverter INV2 is turned on, and the transistor T4 is turned off. When the transistor T3 is turned on, the potential of the node N2 becomes Vdd (high level), and O2 becomes Vdd (high level).

Further, since the node N1 is Vss and the node N2 is Vdd, the transistors Tr1 and Tr2 are turned on and the transistor Tr3 is turned off, and the CK1 low level (Vss) is output as CKO1 from the OUT2 terminal.

Subsequently, when the clock signal CK2 changes from the high level to the low level (t4), the data input unit SW1 is turned off, the input of O1 is cut off, and the node N1 is immediately before the latch operation by the latch inverters INV1 and INV2. Is held at the potential (Vss (low level)), O2 is maintained at Vdd (high level), and CKO2 is maintained at Vss (low level) of CK1.

Subsequently, when the clock signal CK1 becomes high level (t5), CKO2 becomes high level (Vdd), and when the clock signal CK1 becomes low level (t6), CKO2 becomes low level (Vss).

Next, when the clock signal CK2 becomes high level (t7), the data input unit SW1 is turned on again, and O1 (high level; Vdd) is input to the node N1.

Thereby, when the potential of the node N1 becomes close to Vdd (high level) or Vdd (high level), the transistor T4 of the latching inverter INV2 is turned on, and the transistor T3 is turned off. When the transistor T4 is turned on, the potential of the node N2 becomes Vss (low level), and O2 becomes low level (Vss).

Further, since the node N1 is Vdd and the node N2 is Vss, the transistors Tr1 and Tr2 are turned off, the transistor Tr3 is turned on, and CKO2 is at a low level (Vss).

Subsequently, when the clock signal CK2 changes from the high level to the low level (t8), the data input unit SW1 is turned off, the input of O1 is cut off, and the node N1 is immediately before the latch operation by the latch inverters INV1 and INV2. Is held at the potential (Vdd (high level)), and O2 and CKO2 maintain Vss (low level). Thereafter, the SR unit circuit SR2 maintains Vss (low level) for O2 and Vss (low level) for CKO2 until O1 becomes high level.

The SR unit circuit SR1 is operated in the odd-numbered SR unit circuits after the third stage, and the SR unit circuit SR2 is operated in the even-numbered SR unit circuit.

Here, in the above operation, the scanning direction of the shift register 10 is the first direction (switching signal UD: high level, switching signal UDB: low level) from the first stage to the nth stage, but from the nth stage. In the case of the second direction toward the first stage, the switching signal UDB may be set to a high level (the switching signal UD is set to a low level). FIG. 31 is a timing chart when the shift direction is the second direction.

(Example 16)
FIG. 32 is a block diagram illustrating a schematic configuration of the shift register 10 according to the sixteenth embodiment. FIG. 33 is a circuit diagram of the SR unit circuit constituting the shift register 10.

32, n (n is an integer of 2 or more) SR unit circuits and two dummy SR unit circuits SRa and SRb are provided. The SR unit circuit has an IN1, IN2, UD, CK, OUT1, and OUT2 terminals. As shown in FIG. 33, in the k-th SR unit circuit SRk, the previous (k−1) -th stage output signal CKO (k−1) is input to the IN1 terminal, and the previous (k + 1) to the IN2 terminal. The output signal CKO (k + 1) at the stage is input, the switching signal UD is input to UD, the clock signal CK1 or CK2 is input to the CK terminal, the output signal Ok is output from the OUT1 terminal, and the output signal CKOk is output from the OUT2 terminal. Is output. The output signal CKOk is input to the IN1 terminal of the (k + 1) -th stage SR unit circuit SR (k + 1).

FIG. 34 is a timing chart when the shift register 10 operates. According to the above configuration, the polarity of the output signal Ok at the OUT1 terminal is equal between the odd-numbered stage and the even-numbered stage. When the output signal CKO (k + 1) of the next stage OUT2 terminal is input to the IN2 terminal, the node N2 becomes Vdd (high level) and the output signal Ok becomes Vss (low level) by the bootstrap operation. Note that the latch inverters INV1 and INV2 can exceed the inversion potential of the inverter constituting the latch if the drive capability is lower than that of the switching signal UD.

In this case, the switching signal UD needs only to have a higher driving capability than the latching inverters INV1 and INV2, and is driven by a buffer having a channel width W larger than that of the latching inverters INV1 and INV2 outside the shift register, or has a higher driving capability. It is preferable to use the output of the IC.

Further, since the SR unit circuit of this embodiment requires two inputs, it is necessary to arrange a dummy stage at the final stage in the scanning direction. In this configuration, the output CKOb of the dummy stage is delayed via an inverter. After that, it feeds back to its own IN2 terminal to make the latch state inactive.

In the above operation, the shift direction is the first direction (switching signal UD: high level, switching signal UDB: low level). However, when the second direction is set, the switching signal UDB is switched to high level (switching signal UD may be set to a low level). FIG. 35 is a timing chart when the shift direction is the second direction.

Also, the circuit configuration of FIG. 33 may be the configuration of FIG. In FIG. 36, the inverted signal UDB of the switching signal UD is input to the data input unit SW2b.

(Example 17)
FIG. 37 is a circuit diagram of the SR unit circuit constituting the shift register 10. The SR unit circuit of FIG. 37 has a configuration in which an initialization signal is input instead of the power supply of the latching inverter in the SR unit circuit of FIGS. FIG. 37 is a circuit diagram of the first-stage SR unit circuit SR1 that constitutes the shift register 10, and FIG. 38 is a circuit diagram of the second-stage SR unit circuit SR2 that constitutes the shift register 10.

37. As shown in the SR unit circuit SR1 in FIG. 37, the initialization signal INIT is input to the source terminal of the transistor T4 of the latching inverter INV2. As shown in the SR unit circuit SR2 of FIG. 38, the initialization signal INIT is input to the source terminal of the transistor T6 of the latching inverter INV1.

FIG. 39 is a timing chart when the shift register 10 operates.

In the odd-numbered SR unit circuit (SR1) (for example, FIG. 37), when the node N1 is Vdd (high level) in an undefined state before initialization, the transistor T4 is turned on and the output O is the initialization signal INIT. The output CKO becomes Vss (low level) when the transistor Tr3 is turned on. On the other hand, when the node N1 is Vss (low level) in an indefinite state before initialization, the transistor T3 is turned on and the output O is high level, and the output CKO is turned on and the transistor Tr3 is turned on to Vss (low level). become.

In the even-numbered SR unit circuit (SR2) (for example, FIG. 38), when the node N1 is Vdd (high level) in an undefined state before initialization, the transistor T4 is turned on and the output O becomes low level. The output CKO becomes Vss (low level) when the transistor Tr3 is turned on. On the other hand, when the node N1 is Vss (low level) in an indeterminate state before initialization, the transistor T6 is on, and when the initialization signal INIT goes high, N1 goes from low level to high level. Therefore, the transistor T4 is turned on and the output O becomes low level, and the output CKO becomes Vss (low level) when the transistors Tr1 and Tr2 are turned off and Tr3 is turned on.

(Example 18)
In the SR unit circuit of the seventeenth embodiment, the output CKO is inactive (low level) at the time of initialization. However, as shown in FIGS. 40 and 41, the output CKO is active (high level) at the time of initialization. It is good also as composition which becomes. In this embodiment, an initialization signal INIT is input to the source terminal of the transistor Tr3 in addition to the configurations of FIGS.

FIG. 42 is a timing chart when the shift register 10 operates.

In the odd-numbered SR unit circuit (SR1) (for example, FIG. 40), when the node N1 is Vdd (high level) in an undefined state before initialization, the transistor T4 is turned on and the output O is the initialization signal INIT. The output CKO becomes high level of the initialization signal INIT when the transistor Tr3 is turned on. On the other hand, when the node N1 is Vss (low level) in an indefinite state before initialization, the transistor T3 is turned on and the output O becomes high level, and the output CKO is turned on by the transistor Tr3 and the initialization signal INIT. Become a high level.

In the even-numbered SR unit circuit (SR2) (for example, FIG. 41), when the node N1 is Vdd (high level) in an undefined state before initialization, the transistor T4 is turned on and the output O becomes low level. The output CKO becomes high level of the initialization signal INIT when the transistor Tr3 is turned on. On the other hand, when the node N1 is Vss (low level) in an indeterminate state before initialization, the transistor T6 is on, and when the initialization signal INIT goes high, N1 goes from low level to high level. Therefore, the transistor T4 is turned on and the output O is at the low level, and the output CKO is turned on at the high level of the initialization signal INIT with the transistor Tr3 turned on.

The initialization signal INIT input to the transistor Tr3 may be the all-on signal AON. In this case, a high level may be input if the output is to be activated during initialization, and a low level may be input if the output is to be inactive during initialization.

(Example 19)
FIG. 43 is a circuit diagram of the SR unit circuit constituting the shift register 10. The SR unit circuit of FIG. 43 has a configuration in which an initialization signal INIT is input instead of the VSS power supply of the latching inverter in the SR unit circuit of FIG.

43. As shown in the SR unit circuit of FIG. 43, the initialization signal INIT is input to the source terminal of the transistor T4 of the latching inverter INV2. FIG. 44 is a timing chart during operation of the shift register 10 according to the present embodiment.

Here, the circuit configuration of FIG. 43 may be the configuration of FIG. In FIG. 45, an inverted signal UDB of the switching signal UD is input.

(Example 20)
FIG. 47 is a circuit diagram of the SR unit circuit constituting the shift register 10. In the SR unit circuit of FIG. 47, the output inverter INV3 and resistors R1 and R2 are provided in the SR unit circuit of FIG. In the SR unit circuit of FIG. 47, the clock signals CK1 and CK2 input to the CK terminal are signals inverted from the clock signals CK1 and CK2 of FIG.

FIG. 48 is a timing chart during operation of the shift register 10 according to the present embodiment.

(Example 21)
49 and 50 are circuit diagrams of the SR unit circuit constituting the shift register 10. 49 shows the first-stage SR unit circuit SR1 constituting the shift register 10, and FIG. 50 shows the second-stage SR unit circuit SR2 constituting the shift register 10. The SR unit circuits of FIGS. 49 and 50 are the same as the SR unit circuits of FIGS. 37 and 38 except for the configuration of the pulse output circuit 24b.

As shown in the SR unit circuit SR1 of FIG. 49, the pulse output circuit 24b in the odd-numbered stage includes a transistor Tr4a whose gate terminal is connected to the power supply VDD and whose source terminal is connected to the node N1, and whose gate terminal is the drain of the transistor Tr4a. A transistor Tr2a connected to the terminal, a source terminal connected to the CKb terminal, a gate terminal connected to the node N2 and the OUT1 terminal, a source terminal connected to the power supply VSS, a gate terminal and a drain of the transistor Tr2a And a capacitor C2a connected to the terminal. Further, the drain terminal of the transistor Tr2a, the drain terminal of the transistor Tr3a, and the OUT2 terminal are connected.

As shown in the SR unit circuit SR2 of FIG. 50, the even-numbered pulse output circuit 24b includes a transistor Tr4b whose gate terminal is connected to the power supply VDD and whose source terminal is connected to the node N2, and whose gate terminal is the drain of the transistor Tr4b. The transistor Tr2b is connected to the terminal, the source terminal is connected to the CKb terminal, the gate terminal is connected to the node N1, the transistor Tr3b is connected to the power source VSS, and the gate terminal and the drain terminal of the transistor Tr2b are connected. Capacitance C2b. Further, the drain terminal of the transistor Tr2b, the drain terminal of the transistor Tr3b, and the OUT2 terminal are connected.

49 and 50, Vdd−Vth + α (push-up voltage) can be supplied to the gate terminals of the transistors Tr2a and Tr2b by the bootstrap operation by the transistors Tr4a and Tr4b and the capacitors C2a and C2b. Therefore, an appropriate output signal CKO can be output.

(Example 22)
FIG. 51 is a circuit diagram of the SR unit circuit constituting the shift register 10. The SR unit circuit of FIG. 51 is the same as the SR unit circuit of FIG. 43 except for the configuration of the pulse output circuit 24b.

As shown in FIG. 51, the pulse output circuit 24b includes a transistor Tr4 having a gate terminal connected to the power supply VDD, a source terminal connected to the node N1, a gate terminal connected to the drain terminal of the transistor Tr4, and a source terminal connected to the node Tr1. A transistor Tr2 connected to the CK terminal; a transistor Tr3 having a gate terminal connected to the node N2; a source terminal connected to the power supply VSS; and a capacitor C2 connected to the gate terminal and the drain terminal of the transistor Tr2. Yes. Further, the drain terminal of the transistor Tr2, the drain terminal of the transistor Tr3, and the OUT terminal are connected.

According to the configuration of the SR unit circuit of FIG. 51, Vdd−Vth + α (push-up voltage) can be supplied to the gate terminal of the transistor Tr2 by the bootstrap operation by the transistor Tr4 and the capacitor C2. Can be output.

(Example 23)
FIG. 52 is a block diagram illustrating a schematic configuration of the shift register 10 according to the twenty-third embodiment. 53 is a circuit diagram of the second-stage SR unit circuit (SR unit circuit SR2) constituting the shift register 10, and FIG. 54 is a timing chart when the shift register 10 operates. FIG. 55 is a timing chart for explaining the potential change of the node N1.

In the shift register 10 shown in FIG. 52, the output signal CKO of the preceding SR unit circuit is input to the IN terminal of each SR unit circuit. For example, in the SR unit circuit SR2 of FIG. 53, the output signal CKO1 of the SR unit circuit SR1 is input to the IN terminal. In the SR unit circuit of FIG. 53, the source terminal of the transistor Tr3 of the pulse output circuit 24b is connected to the power supply VDD, and further includes a buffer BF including transistors Tr9 and Tr10. Note that the initialization signal INIT input to the source terminal of the transistor Tr10 may be the all-on signal AON.

Here, the potential of the node N1 is determined by a signal (CKO1 in FIG. 53) input to the IN terminal when the clock signal CK2 (enable signal) becomes inactive. Therefore, in order to operate the SR unit circuit normally, it is necessary that CKO1 is at the high level at the rising timing of the clock signal CK2, as shown in FIG. However, in actuality, as shown in FIG. 55 (b), there is a possibility that CKO1 becomes low level at the rising timing of the clock signal CK2 due to the influence of the turning of the clock signal CK2. In this case, since the potential of the node N1 is held at a low level, the SR unit circuit causes a malfunction.

In this regard, in the SR unit circuit of FIG. 53, since the output signal CKO1 of the SR unit circuit SR1 in the previous stage is input to the IN terminal of the SR unit circuit SR2 through the buffer BF, it is compared with the case where the output signal CKO1 is not passed through the buffer BF. Thus, the potential change of the output signal CKO1 can be delayed. Therefore, as shown in (c) of FIG. 55, CKO1 can be reliably maintained at a high level at the rising timing of the clock signal CK2, so that the malfunction can be prevented.

53 may be configured as shown in FIG. 56. 57 is a timing chart at the time of operation of the shift register 10 according to the configuration of FIG. 56, and FIG. 58 is a timing chart for explaining a potential change of the node N1.

In the SR unit circuit of FIG. 56, the buffer BF of FIG. 53 is omitted, but since CKO2 is connected to the gate line, the output signal as shown in FIG. The potential change of CKO1 can be delayed. Therefore, CKO1 can be reliably maintained at the high level at the falling timing of the clock signal CK2, so that the malfunction can be prevented as in the SR unit circuit of FIG. Note that the initialization signal INIT input to the source terminal of the transistor Tr3 constituting the pulse output circuit 24b may be the all-on signal AON.

As in this embodiment, in the shift register 10, a signal obtained by delaying the output signal of the pulse output circuit (24b) in the previous SR unit circuit is input to the data input unit (SW1a) of the SR unit circuit (holding circuit). It can be set as the structure to do.

In the shift register according to the embodiment of the present invention, the potential level of the signal held at the first connection point that is the connection point between the output terminal of the first inverter and the input terminal of the second inverter is the enable signal. When becomes active, it may be configured to change so as to approach the potential level of the hold target signal.

In the shift register according to the embodiment of the present invention, the potential level of the signal held at the first connection point is such that the enable signal is active and the output signal of the second inverter is the first inverter. Can be configured to be equal to the potential level of the hold target signal.

The shift register according to the embodiment of the present invention may be configured such that the output signal of the first inverter or the second inverter is supplied to the holding circuit in the next stage through a buffer.

In the shift register according to the embodiment of the present invention, the transistor constituting the first inverter provided between the first connection point and the input terminal of the first inverter has the channel length of the second register. It can also be set as the structure set so that it may become larger than the channel length of the transistor which comprises an inverter.

In the shift register according to the embodiment of the present invention, the transistor constituting the second inverter is configured such that the channel width thereof is set larger than the channel width of the transistor constituting the first inverter. You can also.

In the shift register according to the embodiment of the present invention, the output signal of the first inverter or the second inverter is supplied to the holding circuit of the next stage through the buffer, and the transistor constituting the first inverter is A configuration in which the channel width is set to be smaller than the channel width of the transistors constituting the buffer may be employed.

The shift register according to the embodiment of the present invention may have a configuration in which a resistor is provided between the first connection point and the output terminal of the first inverter.

In the shift register according to the embodiment of the present invention, the holding circuit includes first to fifth transistors, the first inverter includes the second and third transistors, and the second inverter includes the fourth and fourth transistors. The first transistor includes the fifth transistor, the gate terminal is supplied with the enable signal, the source terminal is input with the output signal of the previous holding circuit, the gate terminals of the second and third transistors, and the first transistor The drain terminals of the fourth and fifth transistors are connected, and the drain terminals of the second and third transistors, the gate terminals of the fourth and fifth transistors, and the drain terminals of the first transistor are connected. It can also be set as the structure which has.

In the shift register according to the embodiment of the present invention, the source terminal of the third transistor is connected to the low-potential side power supply via the first resistor, and the source terminal of the second transistor is connected to the high potential via the second resistor. A low potential signal is input to the source terminal of the fifth transistor, and a high potential signal is input to the source terminal of the fourth transistor.

In the shift register according to the embodiment of the present invention, a first resistor is provided between the drain terminal of the third transistor and the output terminal of the first inverter, and the drain terminal of the second transistor and the first inverter are provided. The second resistor may be provided between the output terminal and the output terminal.

The shift register according to the embodiment of the present invention may be configured such that an initialization signal is input to any one of the source terminals of the second to fifth transistors.

A scanning signal line driving circuit according to an embodiment of the present invention includes the shift register, and an output signal of the holding circuit is supplied as a scanning signal to a scanning signal line corresponding to the holding circuit. .

The display panel according to the embodiment of the present invention is characterized in that the scanning signal line driving circuit and the pixel circuit are formed monolithically.

A display device according to an embodiment of the present invention includes the scan signal line driving circuit.

The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

The present invention is suitable for each drive circuit of a display device.

1 Liquid crystal display device (display device)
10 Shift Register 11 Shift Register Unit Circuit 41 Scan Signal Line (Gate Line)
42 Common electrode wiring (common line)
43 Data signal line (source line)
44 TFT
45 Pixel electrode 100 Scanning signal line drive circuit (gate driver)
300 Data signal line drive circuit (source driver)
400 Display panel T1 transistor (first transistor)
T3 transistor (4th transistor)
T4 transistor (5th transistor)
T5 transistor (second transistor)
T6 transistor (third transistor)
INV1 inverter (first inverter)
INV2 inverter (second inverter)
R1 resistance (first resistance)
R2 resistance (second resistance)

Claims

A shift register having a holding circuit in each stage,
The holding circuit includes a data input unit that captures a retention target signal in response to an enable signal, and a first inverter and a second inverter that retain the captured retention target signal, and the first inverter or the second inverter. Based on the output of the inverter, it outputs a high level or low level signal,
When the enable signal is active, the input terminal of the first inverter and the output terminal of the second inverter are electrically connected to each other, and the output terminal of the first inverter and the input of the second inverter A shift register characterized in that terminals are electrically connected to each other.
The potential level of the signal held at the first connection point, which is the connection point between the output terminal of the first inverter and the input terminal of the second inverter, is the potential level of the signal to be held when the enable signal becomes active. The shift register according to claim 1, wherein the shift register changes so as to approach.
The potential level of the signal held at the first connection point is such that when the enable signal becomes active and the output signal of the second inverter is input to the first inverter, the potential of the signal to be held is held. The shift register according to claim 2, wherein the shift register is equal to the level.
2. The shift register according to claim 1, wherein an output signal of the first inverter or the second inverter is supplied to a holding circuit in the next stage through a buffer.
The transistor constituting the first inverter provided between the first connection point and the input terminal of the first inverter has a channel length larger than the channel length of the transistor constituting the second inverter. The shift register according to claim 2, wherein the shift register is set as follows.
4. The shift register according to claim 2, wherein the transistor constituting the second inverter has a channel width set to be larger than a channel width of the transistor constituting the first inverter. .
The output signal of the first inverter or the second inverter is supplied to the holding circuit of the next stage through the buffer,
4. The shift register according to claim 2, wherein the transistor constituting the first inverter has a channel width set to be smaller than a channel width of the transistor constituting the buffer.
4. The shift register according to claim 2, wherein a resistor is provided between the first connection point and the output terminal of the first inverter.
The holding circuit includes first to fifth transistors, the first inverter includes the second and third transistors, the second inverter includes the fourth and fifth transistors,
In the first transistor, the enable signal is given to the gate terminal, and the output signal of the previous holding circuit is inputted to the source terminal,
The gate terminals of the second and third transistors and the drain terminals of the fourth and fifth transistors are connected;
2. The shift register according to claim 1, wherein drain terminals of the second and third transistors, gate terminals of the fourth and fifth transistors, and drain terminals of the first transistor are connected. .
The source terminal of the third transistor is connected to a low potential side power source via a first resistor, and the source terminal of the second transistor is connected to a high potential side power source via a second resistor,
The shift register according to claim 9, wherein a low potential signal is input to a source terminal of the fifth transistor, and a high potential signal is input to a source terminal of the fourth transistor.
A first resistor is provided between the drain terminal of the third transistor and the output terminal of the first inverter, and a second resistor is provided between the drain terminal of the second transistor and the output terminal of the first inverter. The shift register according to claim 9, wherein the shift register is provided.
12. The shift register according to claim 9, wherein an initialization signal is input to any one of the source terminals of the second to fifth transistors.
A scanning signal line driving circuit comprising the shift register according to any one of claims 1 to 12,
An output signal of the holding circuit is supplied as a scanning signal to a scanning signal line corresponding to the holding circuit.
14. A display panel, wherein the scanning signal line driving circuit and the pixel circuit according to claim 13 are monolithically formed.
A display device comprising the scanning signal line driving circuit according to claim 13.