JPH01243296A - Shift register circuit - Google Patents

Abstract

PURPOSE:To reduce a layout area and to reduce the charge/discharge current of gate capacity by performing desired connection by using a few number of transistors, and performing the input/output of data with an adjacent register in the H period of a control signal. CONSTITUTION:In the period of a clock signal CK=H (Vcc positive level), the transistor Tn1 is turned on and output data in a register at a preceding stage is written on a latch circuit consisting of inverters INV1 and INV2. Simultaneously, data held at the latch circuit consisting of inverters INV3 and INV4 is outputted to an output signal Di via transistors Tn2, Tn3, and Tn4. In the period of the clock CK=L, a transistor Tp1 is turned on, and the data in the latch circuit (INV1 and INV2) is written on the latch circuit (INV3 and INV4). At this time, when potential at a point A is set at an L, the Tn3 is turned on, and the L of the CK appears at a Di, then, the Di goes to the L. Also, when the potential at the point A is set at the H, the Tn3 is turned off, and the Tn4 is turned on, therefore, it is goes to Di=L. In the constitution, the number of the transistors can be reduced remarkably.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention is directed to a CM consisting of a plurality of cascade-connected registers.
In the shift register (b) path of O5, the control signal that controls the shift of data between registers is +1 H11 (
In addition, during the period when id is "L"), a data signal is output from each stage register, and during the period when the control signal is P or 11 H11), the output signal from each stage register is 11 L or 11.
(or fl H11).

<Conventional technology> First, a conventional shift register circuit will be explained.

FIG. 5 is an example of a conventional shift register circuit. C
K is a clock signal, and Di is a data signal for each stage register, which serves as a chip input to a subsequent stage register. In the figure,
1'n6. Tn7 (N channel MO5) transistor, T
p6. Tp7 is P channel MO5) 7 register, INV
9. -, INVI4u inverter, NANDI is a Nant gate. A timing chart is shown in FIG. C
During the period when K="H", transistors Tn6 and Tp6 are turned on, and the output data of the previous stage register is written to the latch circuit composed of INVIO and INVll.

At the same time, the data held in the latch circuit composed of IN=v12 and INVI3 is output to DilC through the NAND INV14 and CK=”L.
”, transistors Tn7 and Tp7 are turned on,
The data of the latch circuit composed of INVIO and INVll is written to the latch circuit composed of INVIO and INVll. At the same time, one of the inputs of NAND] becomes "L", so the output of INVI4 becomes "H", and Di="Ln".

<Problems to be Solved by the Invention> An example of a conventional shift register has been described, but in the conventional shift register described above, each stage has two registers.
The shift register is configured with zero transistors, and there is a problem in that the layout area of the shift register increases when a plurality of registers are connected in cascade. Furthermore, since the clock CK controls multiple registers, it is necessary to increase its driving capability, and the layout area of the clock CK generation circuit also becomes large. There is a problem in that the current consumption is large due to charging and discharging the gate capacitance of NAND I.

The present invention has been made in view of the above-mentioned conventional problems, and has an advantage in reducing the number of components of each register, in reducing the layout area of the shift register itself, and in reducing the load on the clock CK. , clock C
The purpose is to reduce the layout area of the K generation circuit and reduce the charging and discharging current of the gate capacitance.

<Means for Solving the Problem> In a shift register circuit consisting of a plurality of cascade-connected registers, in which shifting of data between registers is controlled by a control signal, each stage register is
The source is connected to the data output signal line from the previous stage register, the gate is connected to the control signal, and the first
a first inverter having an input connected to the drain of the first transistor; and a second inverter having an input connected to the output of the first inverter and having an output input to the first inverter and connected to the drain of the first transistor. an inverter and a source connected to the output of the first inverter and the second inverter;
a P-channel second transistor connected to the input of the inverter and having its gate connected to the control signal; a third inverter having its input connected to the drain of the second transistor; and its input connected to the output of the third impark; a fourth inverter whose output is connected to the input of the third inverter and the drain of the second transistor, and whose source is connected to the third inverter.
a third N-channel transistor connected to the output of the inverter and the input of the fourth inverter, its gate connected to the positive potential power supply line; its drain connected to the self-control signal; its gate connected to the drain of the third transistor; The source is connected to the data input signal line of the subsequent register, and the drain is connected to the source of the fourth transistor and the data input signal line of the subsequent register, and the gate is connected to the input of the third inverter and the 4 N connected to the inverter output and the source connected to the GND line
- a fifth transistor of the channel. Each stage register receives the data signal from the previous stage register while the control signal is "H", and simultaneously outputs the data signal to the next stage register, and the control signal is u L +
During the + period, each stage register outputs L"'.

In the shift register circuit, among the components of each stage register, the first transistor is a P-channel, the second transistor is N-channel, the third, fourth,
The fifth transistor is changed to a P-channel, and the gate of the third transistor is connected to the negative potential power supply line.

Each stage register has a period in which the control signal is u L 11,
It accepts a data output signal from a previous stage register, simultaneously outputs a data signal to a subsequent stage register, and the control signal is
During the period H11, each stage register outputs Hn.

(VcLV), the number of transistors constituting each stage of registers has been reduced by 7 to 13.

<Function> In addition to reducing the layout area of the shift register itself, the load on the clock CK is also reduced, and the layout area of the clock CK generation circuit can also be reduced.
The charging and discharging current of the gate capacitor can also be reduced.

<Example> The present invention will be explained below based on Examples.

FIG. 1 shows an embodiment of the invention according to claim 1. C.K.
The U clock signal and Dl are data output signals of each stage register, and serve as data inputs of the first succeeding stage register. In the figure, Tnl+..., Tn4 are N-channel M'O3) transistors, Tplil''11.P-channel MOS transistors, INVl,..., INV4U inverters.

A timing chart is shown in FIG. CK=“H”(V
CC (positive) level), transistor Tnl is turned on, and the output data of the previous stage resistor gate is input to INVl.
1 is written to the latch circuit consisting of 2. At the same time, I
The data held in the latch circuit made up of NVB INV4 is transferred to transistors Tn2. TnLTn4
It is output to Di through.

f That is, when the potential at point A is “H”, transistor Tn3 is turned off and Tn4 is turned on, so Di = “L”
(GND level). When the potential at point A is “L”, the potential at point B is “H”, and point C is at (VCC-
VTR) is at the potential (Vcc [positive power supply potential, V
TH [threshold voltage of N-channel transistor). When CK rises in this state, transistor Tn
Due to the source-gate coupling of 3, the potential at point C becomes a potential higher than (Vc c +VTR), Tn2 is cut off and Tn8 is turned on, so D1=゛H
” (Vcc level).

During the period of CK-“Ln, the transistor Tpl is turned on,
The data of the latch circuit composed of INVI and INV2 is written to the latch circuit composed of INV4 after INVB. At this time, when the potential at point A is uL'',
The potential at point B is 11H11, and the potential at point C is (Vc
c-VTR), Tn8 turns on,
The "L" level of CK is applied to Dl, and becomes Dl-"L". On the other hand, when the potential at point A is "H", transistor Tn3 is turned off and Tn4 is turned on, so Di="L"
becomes.

FIG. 3 shows an embodiment of the invention according to claim 2. C.K.
The U clock signal and Dl are data output signals of each stage register, and serve as data output signals of subsequent stage registers. In the figure, Tn5 is an N-channel MOS transistor, Tp2 .・
..., Tp5 is a P channel MOS transistor, IN
V5. ..., INV8 is an inverter. A timing chart is shown in FIG. During the period of CK 'L' (Vcc (negative) level), transistor Tp2 is turned on and the output data of the previous stage register becomes INV.
5 The data is written to the latch circuit made up of INV6. At the same time, the data held in the latch circuit composed of INV7 and INV8 is transferred to the transistor Tpa,
Tp4. The level is output to Di through Tp5). When the potential at point E is ++H11, the potential at point F is ++L++, and the potential at point G is (Vce=VTI
The potential is ('). (Vcc ~ negative power supply potential, V
TH'i'JP channel transistor threshold voltage)
. In this state, when CK falls, the potential at point G becomes lower than (vcc + vTH) due to the source-gate coupling of transistor Tp4, and Tp8 is cut off and Tp4 is turned on. Di==“L” (Vccm level).

During the period when CK="H", transistor Tn5 is turned on and I
The data in the latch circuit made up of NV5, INV6, and INV7 is written to the latch circuit made up of INV7 and INV8. At this time, when the potential at point E is "H+1",
The potential at point F is "L+', and the potential at point G is (vcc'
-VTR') Tp4 turns on,
The “H” level of CK is applied to Di, and D i = ”
H".On the other hand, when the potential at point E is flL",
Since transistor Tp4 is turned off and Tp5 is turned on,
D i −”H″′.

<Effects of the invention> This has been explained above. l: According to the present invention, the number of transistors constituting the shift register can be reduced, and as a result, the layout area of the shift register itself can be reduced, and the load on the clock CK is reduced, so that the clock CK generation circuit can be The layout area can also be reduced, and the charging/discharging current for one gate capacitor can also be reduced.

[Brief explanation of the drawing]

1 and 3 are circuit diagrams showing embodiments of the present invention,
2 and 4 are time charts, and FIG. 5 is a circuit diagram of a conventional example. Explanation of symbols CK: Clock signal Di = Mini data Tnl. -Tn7: N-channel MO3) lunge, 1. Evening Tpl
. ..., Tp7: P channel MO5) transistor INV
1. −． INVI4: Invar! NAND I
: Nando Gate.

Claims (1)

[Claims] 1. In a shift register circuit consisting of a plurality of cascade-connected registers, in which shifting of data between registers is controlled by a control signal, each stage register has a source a first N-channel transistor connected to a data output signal line from a previous stage register and having a gate connected to the control signal; a first inverter having an input connected to the drain of the first transistor; and a first inverter having an input connected to the first inverter. a second inverter having an output connected to the input of the first inverter and a drain of the first transistor; a second inverter having a source connected to the output of the first inverter and an input of the second inverter and having a gate connected to the control signal; a third inverter having an input connected to the drain of the second transistor; an input connected to the output of the third inverter and an output connected to the input of the third inverter and the second inverter; a fourth inverter connected to the drain of the transistor; and an N-channel third inverter having a source connected to the output of the third inverter and an input of the fourth inverter and a gate connected to a positive potential power supply line.
a fourth N-channel transistor having a drain connected to the control signal, a gate connected to the drain of the third transistor, and a source connected to the data input signal line of the subsequent register; The N is connected to the source and the data input signal line of the subsequent register, the gate is connected to the input of the third inverter and the output of the fourth inverter, and the source is connected to the GND line.
- a fifth transistor of the channel, and each stage register receives a data output signal from the previous stage register while the control signal is "H", and simultaneously outputs a data signal to the next stage register, and the control signal is A shift register circuit characterized in that during an "L" period, each stage register outputs "L". 2. In the shift register circuit according to claim 1, among the components of each stage register, the first transistor is connected to P-
The channel and the second transistor are changed to N-channel, the third, fourth, and fifth transistors are changed to P-channel, and the gate of the third transistor is connected to a negative potential power supply line,
During the period when the control signal is "L", each stage register accepts the data output signal from the previous stage register, and simultaneously outputs the data signal to the subsequent stage register, and during the period when the control signal is "H", each stage register receives A shift register circuit characterized by outputting "H".