GB2035723A - Voltage boosting circuit - Google Patents

Abstract

A voltage boosting circuit comprises a first electronic switch device (G10) one side of which is arranged to be connected to a source of a reference voltage (-VssI). A first capacitor (C10) has one side connected to the other side of the first switch device and to a pulse output circuit (TP10, TN10), the pulse output circuit being arranged, in operation, to receive, at an input signal, the voltage appearing at one side of the first capacitor and to produce an output signal which is applied to the first switch device. A second capacitor (C20) has one side connected to one side of a second electronic switch device (G20), the other side of which is connected to the other side of the first switch device so that the second capacitor is charged to a voltage which is higher than the reference voltage. A level shifting circuit (TP30, TP40, TN30, TN40) is connected to receive, at an input signal the voltage appearing on the second capacitor, and to control the second switch device (G20). A clock arrangement produces two clock signals ( PHI 10, PHI 20) differing in phase and pulse width but of the same frequency. One clock signal ( PHI 10) is applied to the pulse output circuit and the other clock signal is applied to the level shifting circuit. A plurality of such voltage boosting circuits may be connected in series. <IMAGE>

Description

SPECIFICATION Voltage boosting circuit This invention relates to voltage boosting circuits, for example, for electronic watches with liquid crystal display devices.

According to the present invention there is provided a voltage boosting circuit comprising: first switch means one side of which is arranged to be connected to a source of a reference voltage; a first capacitor one side of which is connected to the other side of the first switch means and to a pulse output circuit, the pulse output circuit being arranged, in operation, to receive, as an input signal, the voltage appearing at said one side of the first capacitor and to produce an output signal which is applied to the first switch means; a second capacitor having one side connected to one side of a second switch means, the other side of which is connected to said other side of the first switch means so that, in operation, the second capacitor is charged to a voltage which is higher than the reference voltage; and a level shifting circuit connected to receive, as an input signal, the voltage appearing at said one side of the second capacitor.

Preferably the voltage boosting circuit includes clock means for producing two clock signals differing in phase and pulse width but of the same frequency, one clock signal being applied, in operation, to the pulse output circuit and the other clock signal being applied, in operation, to the level shifting circuit. Said clock means may comprise a frequency divider circuit arranged to receive, as an input, a relatively high frequency signal and to produce, as outputs, said clock signals.

In the preferred embodiment each said switch means is an N-channel gate.

The invention is illustrated, merely by way of example, in the accompanying drawings, in which: Figure 1 is a circuit diagram of a conventional voltage boosting circuit; Figure 2 are waveforms illustrating the operation of the voltage boosting circuit of Figure 1; Figure 3 is a circuit diagram of one embodiment of a voltage boosting circuit according to the present invention; Figure 4 shows waveforms illustrating the operation of the voltage boosting circuit of Figure 3; Figure 5 is a graph showing the relationship between the characteristics of the conventional voltage boosting circuit of Figure 3; and Figure 6 illustrates another embodiment of a voltage boosting circuit according to the present invention.

Conventionally, a liquid crystal display device is used in a digitai electronic timepiece because it has relatively low power consumption and it can be adapted to CMOSIC serving as logic circuitry of the electronic timepiece. However, a liquid crystal display device requires a driving voltage which is higher than the saturation voltage of the liquid crystal material.

Thus an electronic timepiece with a liquid crystal display device requires a voltage boosting circuit to produce, from the voltage of a battery, the required drive voltage to drive the liquid crystal display device so that the latter has a relatively quick response in the low temperature range, and can maintain sufficient contrast display.

A multiplex driving system has been proposed for liquid crystal display devices to reduce the number of electrode terminals. A reduction of the number of electrode terminals makes it possible to display various types of data in a small area and also enables an electronic wristwatch to be made thin and of small size. The multiplex driving system requires a reference voltage level of -Vssl, a voltage level of -2Vssl and a voltage level of -3Vssl. Thus a generating circuit for producing the various voltage levels is required and also a voltage higher than the saturation voltage of the liquid crystal material has to be applied to the liquid crystal material to obtain good contrast.

Figure 1 shows a conventional voltage boosting circuit having a capacitor C1 which is charged to a voltage of (VDD -Vssl) via an N-channel gate G1 which is in the ON condition when an input signal 4in has a voltage VDD. At this time a capacitor C2, which is charged by a boosted voltage does not discharge since an N-channel gate G2 is in the OFF condition.

Next, the capacitor C2 is charged and a point P between both capacitors is at a voltage (-Vssl) x 2 because the gate G1 does to the OFF condition and the gate G2 goes to the ON condition when the input signal in has a voltage -Vssl.

This conventional voltage boosting circuit is disadvantageous in that current flows which is not concerned with the voltage boosting action. A stray capacitance Ca exists which is the sum of the gate capacitance of an N-channel transistor TN2, the gate capacitance of the gate G2 and the drain capacitance of a P-channel transistor TP1, and a stray capacitance Cb exists which is the sum of the gate capacitance of an N-channel transistor TN1,the gate capacitance of the gate G1 and the drain capacitance of a P-channel transistor TP2.The stray capacitance Ca is charged and the stray capacitance Cb is discharge, when the input signal < in has a voltage VOID. In the transient period where the input signal Oin becomes voltage -Vssl, an electric charge (Qa) on the stray capacitance Ca is discharged through the conduction resistance (RP1 ) of the transistor TP1 since the latter is changed from the OFF condition to the ON condition.The time constant (laD) of this discharge is given by: RP1 Ca As the stray capacitance Ca is discharging the stray capacitance Cb is charging through the conduction resistance RN2 of the transistor TN2 with a time constant IbC of RN2.Cb At the transient period when the input signal in changes from voltage -Vssl to voltage VDD the stray capacitanct Ca is charged. In this case the time constant (zaC) of charging is RN1Ca where RN1 is the conduction resistance of the transistor TN1. At the same time the stray capacitance Cb is discharging with a time contant zbD of RP2-Cb where RP2 is the conduction resistance of the transistor TP2.It can be assumed that Ca*Cb as the transistors TP1, TP2, the transistors TN1, TN2 and the gates G1, G2 are of respective equal areas.

However, the relation between the conduction resistances of the transistors TP1, TP2 and the conduction resistances of the transistors TN 1, TN3 is such that RP1vRP2 < RN1=RN2.

Accordingly, aD=bD < laCvlbC that is the charging time of each stray capacitance is longer than its discharge time.

The relationship between a signal 1 applied to the gate G1,the input signal 4)in and a signal 2 is applied to the channel G2 are as shown in Figure 2.

As will be seen, the signals 1, 2 are both at a voltage VDD as the input signal 4)in changes from the voltage -Vssl to the voltage V00 i.e. during period t1 and as the input signal in changes from the voltage VDD to the voltage -Vssl, i.e. during period t2.

Accordingly, both the gates G1, G2 are in the ON condition during periodst1,t2.

The voltage -2Vssl charged by the boosting voltage is discharged to -Vssl and this discharge current is the through-current (the current in the conduction state of the gates G1, G2) when both gates G1, G2 are in the ON condition. Thus the conventional boosting circuit has poor efficiency since it produces current loss.

The through-circuit increases as the frequency of the input signal in increases in the case of high load capacitance. Also, the through-current is apt to increase since a multiplex driving system requires a plurality of voltage levels to be produce from the battery voltage. Thus to increase the life of a battery driving an electronic timepiece it is necessary to reduce this through-current.

Referring to Figure 3 there is shown an embodiment of a voltage boosting circuit according to the present invention. An oscillating signal IN is frequency divided by a frequency divider 10. A divided signal Q2 from the divider 10 is delayed by a D-type flip-flop circuit 20, the delay time being determined by a divided signal Q1 from the divider 10 applied to a clock input. An output signal Q3 from the fli-flop circuit 20 and the divided signal Q2 are applied to inputs of a NAND gate 30 and a NOR gate 40. The output signals from the gates 30, 40 serve as the input signals to a voltage boosting circuit 50 according to the present invention.

The voltage boosting circuit 50 comprises an inverter consisting of a P-channel resistor TP20 and an N-channel transistor TN20, a pulse output circuit consisting of a P-channel transistor TP10 and an N-channel transistorTN10, an N-channel gate G10 serving as a first switching device, a capacitor C10, an N-channel gate G20 serving as a second switching device, a level shifting circuit consisting of P-channel transistors TP30, TP40 and N-channel transistors TN30, TN40 for producing a control signal for the second switching device, an inverter Ii for inverting the input signal to the level shifting circuit, and a second capacitor C20.

The operation of the voltage boosting circuit 50 will be described with reference to Figure 4. In Figure 3, an output signal 10 is produced by the gate 30 and an output signal 20 is produced by the gate 40.

The transistors TP10, TP20, TP30 are in the ON condition and the transistors TN10, TN20, TN30 are in the OFF condition, when the output signals D10, < )20 are in the "0" state and also the transistor TP40 is in the OFF condition and the transistor TN40 is in the ON condition. Accordingly, the gate G10 is in the ON condition and the gate G20 is in the OFF condition so that the capacitor C10 is charged to a voltage -Vssl.

Next, when the signal 10 changes to the "1" state the transistor TP10 goes to the OFF condition, the transistor TN10 goes to the ON condition and so the gate G10 goes to the OFF condition. At this time, the gate G20 remains in the OFF condition. As shown in Figure 4 the output signals 1 0, 20 are of different phase and pulse width but of equal frequency. Thus the output signals 10, 20 are such that there is a period when both the gates G10, G20 are in the OFF condition and are not in the ON condition at the same time.

Next, when the output signals 4)10, 20 are in the "1" state, the transistor TP40 and the transistors TN10, TN20, TN30 are in the ON condition, and the transistors TP10, TP20, TP30 and the transistor TN40 are in the OFF condition. Thus the gate G10 is in the OFF condition and the gate G20 is in the ON condition. The capacitor C10 is charged to a voltage -Vssl in the reverse direction so that the voltage at a point A is boosted to -2Vssl from -Vssl. As a result, the capacitor C20 is charged to -2Vssl.

When the output signal 10 is in the "1" state and the output signal 4)20 is the in "0" state a throughcurrent does not flow since the gates G10, G20 are both in the OFF condition as described previously.

Thus the capacitor C20 does not discharge. The switching gate G10 next is in the ON condition so that the point A is at a voltage -Vssl again when the output signals 4)10, 20 revert to the "0" state.

Accordingly, the voltages at points A, B, and C of Figure 3 have the voltage waveforms as shown in Figure 4. Waveform D of Figure 4 is a timing chart of the gates G10, G20 in the ON condition.

Figure 5 is a graphical comparison between the voltage boosting circuit of Figure 3 and the conventional voltage boosting circuit of Figure 1. In Figure 5, the horizontal axis shows the difference (R2) between the condition resistance Rn of the transis tors TN1,TN10, TN30, TN40 and the conduction resistance RP of the transistors TP1 , TP1 0, TP30, TP40. The vertical axis shows the current consumption of the voltage boosting circuit.

Curve (I), in dotted lines, shows the characteristics of the conventional voltage boosting circuit of Figure 1 and the curve (II) shows the characteristics of the voltage boosting circuit of Figure 3. As will be seen from Figure 5, the current consumption increases when the difference R2 between the conduction resistances RN, RP increases in the conventional boosting circuit. However, the current consumption is unaffected by the difference R2 in the voltage boosting circuit of Figure 3. Thus the voltage boosting circuit of Figure 3 has reduced current consumption compared with the conventional boosting circuit.

Figure 6 illustrates another embodiment of a voltage boosting circuit according to the present invention for producing a plurality of voltage levels for use in a multiplex drive system of a liquid crystal display device, Like parts in Figures 3 and 6 have been designated by the same reference numerals.

The voltage boosting circuit of Figure 6 has a voltage boosting stage 50' of the same construction as the voltage boosting circuit 50 of Figure 3. A level shifting circuit 20 amplifies the voltage level of the signal 10to -2Vssl.

A voltage boosting stage 70 again is of the same construction as the voltage boosting circuit 50 of Figure 3. The capacitor C20 of the voltage boosting stage 70 serves to smooth the voltage of [-(Vssl) x 2 + (-Vssl)].

The voltage boosting circuit of Figure 6 produces a voltage -2Vssl from a point Q and a voltage -3Vssl from a point R. No through-current flows as the switch action of the gates G10, G20 of the voltage boosting stage 70 is determined by a two pulse signal and they are never in the ON condition together.

The voltage boosting circuit according to the present invention described above has decreased through-current and so a reduced current consumption compared with the conventional voltage boosting circuit illustrated in Figure 1.

An electronic timepiece including a voltage boosting circuit according to the present invention may be made relatively small and only substantially as thick as a battery of the electronic timepiece. The battery, moreover, may be of low capacity especially since the voltage boosting circuit may be designed to produce the plurality of voltage levels required for multiplex driving system of a liquid crystal display device to enable the display of various types of data.

Claims (6)

1. A voltage boosting circuit comprising: first switch means one side of which is arranged to be connected to a source of a reference voltage; a first capacitor one side of which is connected to the othe side of the first switch means and to a pulse output circuit, the pulse output circuit being arranged, in operation, to receive, as an input signal, the voltage appearing at said one side of the first capacitor and to produce an output signal which is applied to the first switch means; a second capacitor having one side connected to one side of a second switch means, the other side of which is connected to said other side of the first switch means so that, in operation, the second capacitor is charged to a voltage which is higher than the reference voltage; and a level shifting circuit connected to receive, as an input signal, the voltage appearing at said one side of the second capacitor.

2. A voltage boosting circuit as claimed in claim 1 including clock means for producing two clock signals differing in phase and pulse width but of the same frequency, one clock signal being applied, in operation, to the pulse output circuit and the other clock signal being applied, in operation, to the level shifting circuit.

3. A voltage boosting circuit as claimed in claim 2 in which said clock means comprises a frequency divider circuit arranged to receive, as an input, a relatively high frequency signal and to produce, as outputs, said clock signals.

4. A voltage boosting circuit as claimed in any preceding claim in which each said switch means is an N-channel gate.

5. A voltage boosting circuit substantially as herein described with reference to and as shown in the accompanying drawings.

6. A voltage boosting circuit having first switch means connected to the one terminal thereof to a reference voltage, first condenser connected between another terminal of said first switching means and a pulse output terminal, second condenser connected through second condenser to the one terminal of said first switching means, said second condenser being charged the sum of second reference voltage and a pulse output voltage, wherein a signal for controlling said first switching means is the output signal of a pulse output circuit receiving the voltage derived from the one terminal of said first condenser and a signal for controlling said second switch means as the output signal of a level shifting circuit receiving the voltage derived from the one terminal of said second condenser.