JPS5925406B2 - level shift circuit - Google Patents

Description

Detailed Description of the Invention The present invention relates to an insulated gate field effect I run shifter (In5
ulated Gate Field EffectT
It relates to an integrated circuit device using an IG-FET (hereinafter simply referred to as FET), in particular, using different channel type ICs, -FETs, that is, an N-channel FET and a P-channel FET, and a reference voltage level and a first voltage. An input logic signal whose level is two logic state levels,
The present invention relates to a level shift circuit that level-shifts an output logic signal having two logic levels of a reference voltage level and a second voltage level higher than the first voltage level.

In a complementary IG-FET circuit (CMO8 circuit), an N-channel FET and a P-channel FET are arranged so that they are complementary to each other with respect to the output point, and dissimilar channel FETs that are complementary to each other are arranged in a seesaw set. Because of the on-off operation, in principle a current path cannot be formed between the output point and the ground point or the bias power supply at the same time.

Therefore, power consumption in a steady state is caused by leakage current in the semiconductor layer of the source or drain and leakage current between the source and drain, but these are extremely small and can be ignored.

Therefore, recently, efforts have been made to reduce power consumption in digital electronic equipment that particularly requires reduction in power consumption by integrating the digital circuits that make up such equipment using complementary IG-FET circuits. This is attracting attention.

By the way, digital electronic devices such as electronic wristwatch I
In C (integrated circuit devices), in order to reduce power consumption, the logic circuit section is operated at as low a voltage as possible, for example 1.
Operate at 5V.

However, in order to drive its display circuit, a wristwatch uses not only the same low voltage but also a higher voltage, e.g.
A circuit that generates an output signal that operates between 0 and 15V is required.

Therefore, a circuit that combines a circuit that operates at a low voltage with a circuit that operates at a high voltage is required, and this type of circuit is called a level shifter.

Figure 1 is a circuit diagram showing the simplest level shifter.
It is composed of one N-channel FET and one P-channel FET.

This is because when the input signal is at the reference voltage level, the N-channel type FET1 is turned off (the p-channel FET is turned on), giving the bias power supply E2 level, ie, a high logic state level, as an output.

On the other hand, when the input signal is at the El level, which is lower than the other logic state level with respect to the reference voltage level, that is, the E2 level, the N-channel FET1 is on, and at this time, the P-channel FET2 is also on, but between the output point and the ground point. The impedance RN of the current path formed by the N-channel FET is the impedance Rp between the output point and the 1E2 power supply.
Since RN<A), the output is E2
・RN/RN+Rp=0 (V) and a reference voltage level is given.

To set the above RN<<Rp, L(
Minimize the channel length) and widen W (channel width).
This can be done by minimizing W of the P-channel FET and lengthening L, or by inserting a resistor between the output point and the 1E2 power supply.

In this level shifter, if the N-channel FET is on, a current approximated by E2/Rp flows steadily, and if the rate at which the channel FET is on is α, then α・E
It consumes power of g/Rp.

This is contrary to the fact that there is no DC current in the complementary IG-FET circuit in a steady state, and it happens that the power consumption of the integrated circuit is determined by the DC current of this level shifter.

This power consumption increases in proportion to the number of level shifters used.

However, even if Rp is made thicker (even if the input signal is +E1
→O[v] of output when switching to 0[v] →+
The roundness of the switch to E2 becomes thicker in proportion to Rp (and output capacitance), and the DC current at the time of switching of the next stage circuit that uses this output as input increases, and the frequency characteristics deteriorate. , increasing Rp causes problems such as an increase in the chip occupation area, so it is not very effective to reduce the steady current by increasing Rp.

There is a flip-flop type level shifter shown in FIG. 2, which eliminates direct current in a steady state.

This level shifter is based on the level shifter shown in Fig. 1. Two circuits of the level shifter shown in Fig. 1 are prepared, each receiving two signals that are complements of each other, and a reference voltage of 0 (V) is used as the input signal. At the output terminal E2 level of one level shifter, in order to cut off the current path between the output point of the other level shifter and the 10E2 terminal, a P-channel FET is additionally placed between them, and a separate P-channel FET is placed between the output point and the ground point. A current path is formed in the circuit (configured by additionally arranging an N-channel FET).

The operation of this level shifter is such that, if the logic level of the input signal I is now at the 0 [v] level, the signal T inverted by the inverter 11 is at the 10E1 level (lower than the lowest level).

Therefore, N-channel FET 12 is turned off, FET 13 is turned on, and output point 14 is at 0 [V].

Since the output point 14 is 0 (V), the P channel F
ET15 is on (FET16 is off), and output point 17 outputs the 10E2 level (high level).

Here, FET18 is selected so that its on-resistance is extremely large even if it is initially on when the input signal I-0 (V) is applied, and immediately after that, its gate input becomes 10E2.
There is no problem because it becomes a complete off state by reaching the level.

Next, when the input signal ■ switches from 0 (V) to the 10E1 level, the N-channel FET 12 turns on, the output point 170 level changes from the 10E2 level to the 0 (V) level, and the FET 18 turns on (FET 19 turns off). becomes.

On the other hand, at this time, the signal pin becomes 0 [v] at the same time as the input signal ■ switches from 0 [■] to +E1, so the FET
13 is off, so the output point 14 is at the 10E2 level.

Here, FET15 was initially on when input signal I-+E1 was supplied, but its on-resistance was extremely large (selected), and immediately after that, its gate input was
There is no problem because it is completely turned off by reaching level 1.

However, in the flip-flop type level shifter shown in FIG. 2, the impedance RN between the output point and the ground point formed by the N-channel F'ET that is turned on in response to the input signal level 1E1 is the same as the output point at this time and 1E2. In any circuit, it is necessary that RN<<Rp as compared with the impedance Rp of the current path temporarily formed between the power supplies.

Therefore, although this level shifter can cancel the steady DC current, it has the disadvantage that the number of elements used is doubled, the interconnection between each FET is complicated, it is difficult to standardize the pattern, and it requires advanced technology for integration. be.

This may be due to the fact that the area occupied by the level shifter shown in FIG. 2 increases three to several times that of the level shifter shown in FIG. 1.

Therefore, when integrating flip-flop type level shifters, extremely sophisticated technology is required to reduce the chip size and reduce the cost of such integrated circuits. The larger the number, the more effort it takes to reduce the cost by reducing the chip size, and the time required for circuit design must be sacrificed.

3 and 4 are other examples of flip-flop type level shifters. Like the level shifters shown in FIGS. 1 to 4, N is turned on in response to the -El level of the input signal. The impedance RN of the current path between the output point and the ground point (reference voltage terminal) formed by the channel FET is RN<<Rp compared to the impedance Rp of the current path formed between the output point and the 1E2 voltage terminal.
A level shifter that is characterized by
o ) type level shifter.

In view of the above, it is required to reduce the number of ratio type level shifters in an integrated circuit in order to reduce power consumption or reduce costs by reducing chip size.

The present invention has been made in view of the above circumstances, and employs a Ratto 1ess W level shifter, which will be described later, to minimize the number of ratio type level shifters (thereby reducing power consumption and chip area). The present invention is intended to provide a level shift circuit that can reduce the design time.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5a shows an example of a level shifter used in the present invention, and FIG. 5 shows an example of its operating waveform.

The configuration of this circuit is that P-channel FETs 21 and 22 and N-channel FETs 23 and 24 are connected in series between the ground point and a terminal that supplies a high-level voltage 1E2, and clock pulses φ and φ are applied to the gates of FETs 21 and 24. ', and the reference voltage level O (V) and 10E1 level (0+E1
supplying an input signal ■ having a logic level of +E2);
The voltage of the output capacitor C8 is taken out as an output signal at the connection point between the FETs 22 and 23.

Here, when the clock pass/l/s φ' is established (at the 10E1 level), when the pulse φ is established (at the 10E2 level)
is the same as or is established while the pulse φ is established.

This circuit operation is as follows: (a) When the clock pulse φ is not established, the P-channel FET 21 is on, and since the clock pulse φ' is also not established, the N-channel FET 24 is off.

Since FET22 is on regardless of the level of input ■, the current path between the output point and the ground point is blocked by FET24, and since FET21 and 22 are on, the current path between the output point and the terminal 10E2 is cut off. Output capacitance C through
6 is charged to +E2.

(b) Even if the pulse φ is established and the FET 21 is turned off, if the clock pulse 〆 is not established, the FET 24 is also turned off, so the current path between the output point and the E2 terminal or the ground point is The output capacitance C
6 holds the charging voltage level 1E2 when the pulse φ is not established.

(/→Next, pulse φ' is also established (10E1 level)
When this happens, the FET 24 turns on.

At this time, pulse φ is established and FET21 is off, so
The current flow between the E2 terminal and the output terminal is cut off by FET21.

Therefore, if input I is not established (0 (V) level), F
ET23 is off, the current path between the output point and the ground point is cut off, and the output capacitor C8 maintains the charging voltage level of 10E2.
If input ■ is established (10E1 level), FET23
is turned on, a current path is formed by FETs 23 and 24 between the output end and the ground point, the charge in the output capacitor C6 is discharged, and the output end becomes the ground potential.

(→Next, when the pulse φ' is not established, the FET24
is turned off, the current path between the output point and the ground point is cut off, and the output capacitor C8 holds the ground potential.

Then, the pulse φ becomes a failure state, and from then on, the above (a) ~
).

In this way, the input pulse wave of O(V) and 10E1 level becomes the output pulse 0 of 10E2 level and 0 [V],
A predetermined level shift is performed.

As is clear from the above description, the current path between the output end and the 10E2 terminal and the current path between the output end and the ground point are not formed at the same time.

Therefore, no direct current flows between the 10E2 terminal and the ground point.

Also, since there is no DC current path, N-channel FET
The gm ratio of P-channel FET and P-channel FET is not required, and the FET used
It is possible to reduce the size of the

In addition, the number of FET0 used is small at 4 (FET22 shown in the figure).
Since this can be omitted, a level shifter circuit can be constructed with a minimum of three FETs.

In the above description, the high potential level of the clock pulse φ' is assumed to be 10E1, but it may be any level voltage, for example, 10E2, as long as it is higher than the threshold voltage vthN of the N-channel FET.

It is also possible to use the clock pulse φ as the mater clock pulse φ', and furthermore, the clock pulses φ' and φ may be pulses having the same pulse width and the same phase, but differing only in frequency.

Furthermore, even if the source electrode of FET 21 is not always at the E2 level, a pulse can be applied that reaches the E2 level when the clock pulse 0 at the time of
A pulse at the (V) level may be applied.

Further, although the above circuit has a positive logic circuit configuration, it can also have a negative logic circuit configuration.

These various applications can also be applied to the following circuits as appropriate.

In FIG. 6a, the level shifter of FIG. 5a strobes the level-shifted output signal 0 of the input (2) when the clock pulse φ' is established, and changes the output state of the output signal 01 to a strobe circuit 31 (which may also be a storage circuit).

The output capacitor C82 (the same applies hereafter) is held as a charge in the output capacitor C82 until the next strobe pulse is applied, and its output is output via the stabilizing circuit 32. Figure 6 shows its operating waveform diagram. be.

FIG. 7 shows a P-channel FET 41 and an N-channel FET 42, 43 between the E2 terminal and the input terminal to be level shifted.
are connected in series and FET41.

A clock pulse φ with an amplitude of +E2 is supplied to the gate of FET 42, a voltage element E1 is supplied to the gate of FET 43 for matching with the input signal ■, and the output is taken from the output capacitor C6. In operation, +E2 is applied to the output capacitor C8 at the O(V) level of the clock pulse φ.
The level of the input signal is shifted by charging the level of the input signal, and discharging the charged charge at the same time as the 10E2 level of the clock pulse φ and the establishment of the input (2).
The operation corresponds to that shown in the figure, and there is no difference in that Ratio is not required.

In FIG. 8a, a strobe circuit 51 is provided on the output side of the level shifter in FIG. 7, and the output 0' is read out with a clock pulse φ and this state is held until the next clock pulse φ is established. FIG. 8 is a diagram of its operating waveforms.

9A to 11A are application examples of the level shifter described above, but they are the same in that the level shift of the input signal is performed by charging and discharging the output capacitor, and that no ratio is required.

FIGS. 9B to 11S are respectively operational waveform diagrams of the corresponding level shifters.

Therefore, in the circuits shown in FIGS. 5 to 11, the impedance of the current path formed between the output point and the ground point and the impedance of the current path formed between the output point and the high voltage element E2 terminal are To Rati.

Since there is no particular need for
tlO1ess ) type level shifter.

This Ratio-1ess type level shifter uses not only the input signal to be level-shifted but also the output point and
A clock pulse (at least φ) is required to control the current path between the two terminals or between the output point and the ground point or other circuit point for the 1E2 terminal.

Moreover, when combining a circuit section that operates at a low voltage and a circuit section that operates at a high voltage, these circuit sections have some relationship in terms of timing, so each signal used in both circuit sections is They must be synchronized in some way.

Here, consider that digital electronic devices are clock-synchronized (and there are many other signal waveforms that are synchronized with this clock, so no matter how many signals are level-shifted, the above clock pulse (few) It should be noted that both φ) can be unified to one to several types of clock pulses.

That is, the level shift circuit of the present invention uses a Ratio type level shifter to level shift one to several kinds of clock pulses, and uses the reference voltage level obtained thereby and a clock operating at another high voltage level, for example, 10E2 level. By controlling a ratio-1ess type level shifter with pulses, it is possible to shift the levels of many other logic signals.

FIG. 12 is a circuit block diagram showing one embodiment of the present invention.

In the figure, region I is the reference voltage E. A circuit part that operates between the level (ground point level) and the lower voltage element E1 level,
Area ■ is E.

This is a circuit portion that operates between the voltage element E2 level and the voltage element E2 level, which is higher than the voltage element E1 level.

Reference numeral 61 denotes a ratio type level shifter for obtaining the first clock pulse φ (I1 is, for example, a read clock pulse) necessary for the logical operation of the area (2) from the area (2), as shown in FIG.

62 is required for the logical operation of area
Rati for obtaining the second clock pulse φ'2 (I2 is, for example, a read clock pulse) required for the -1ess type level shifter.

A type level shifter, for example, as shown in FIG.

Of course, the clock pulses φ1 and I2 before the level shift are each E.

The clock pulse φ'1. has a level of 10E1 and a level of 1E1, and is level-shifted in phase with that before the level shift. φ′2 is E respectively.

The clock pulse φ'2 and its complement clock pulse I2 are both applied to two-level shifters 63 and 64.

The level shifters 63 and 64 are Ratio-1ess type level shifters for obtaining the logic signals 1'1 and 2'2 required for the area 1 from the logic signals 11 and 12 of the area I, respectively.
For example, it is shown in FIG. 8a.

The logic signals ■'1 and 1'2 are synchronized with the clock pulse φ'2, and one cycle of the clock pulse φ'2 is the basic pulse width.

Of course, the logic signal 11. I2 and logic signals 13 to (6) to be described later are E.

level and 1E level, and the logic signal 1'1. ■'2 and the logic signals ■'3 to 1'6 described below are E.

It has a level and ten E2 levels.

Ratio 1ess W level shifter 65 and strobe circuit 66 transfer logic signal I'3 necessary for area H to area ■
The level shifter 65 shown in FIG. 7, for example, is used as this level shifter 65.

The output signal of the level shifter 65, ・I2)' and its complement signal (D, ・I3)' are sent to the level shifter 67.68.6.
It is given as a clock pulse for level shift in area 9, and is also given as the third clock pulse φ'3 necessary for area (3), which has the same phase as clock pulse φ'2,
Same pulse width (different frequency).

Signal 1'3 is synchronized with clock pulse φ'2, and this φ'
2 is the basic pulse width.

The level shifters 67, 68, and 69 supply logic signals ■'4. ■'5. '6 is the logic signal I4.
■5. (1) The level shifter shown in FIG. 8a, for example, is used as these level shifters.

Logic signal I'4. ■'5. (2)'6 are each synchronized with the clock pulse φ'3, and one period of this φ'3 is the basic pulse width.

Here, if the clock pulses of the level shifters 67, 68, and 69 are replaced with φ'2, the level shifters 63,
64, 67.

68 and 69 can be unified as level shifters that operate with the same clock pulse.

Furthermore, if the clock pulse φ'3 is obtained as an AND signal of the logic signal ■'3 and the clock pulse φ'2, the level shifter 65 and the strobe circuit 66 will also function as the level shifter 63, 64.
,67.68.

This can be unified with 69.

Note that in the above embodiment, the present invention is applied by changing the first voltage level (for example, 10E1 level) to the second voltage level (for example, 10E1 level).
Although the case where the level is shifted to 2 levels) has been described, according to the present invention, it is also possible to shift the level to a voltage level exceeding the first voltage 1/her and up to the second voltage level.

As explained above, the present invention has the following advantages.

In other words, since the level of the logic signal is shifted using a clock pulse that has been level-shifted in the ratio-type level shifter phase, the low-level logic signal is somehow synchronized with the clock pulse before the level shift, and the high-level logic signal is converted into a high-level logic signal. You can level shift to.

Furthermore, since the level of the logic signal is shifted by the clock pulse, the logic signal can be latched when the level is shifted by the clock pulse, that is, the logic signal can be level-shifted and output only at the necessary timing.

In addition, since a ratio-1ess type CMOS level shifter is used, a so-called DC current path is not formed, and g
There is no need to consider the m ratio, it is possible to reduce the integrated circuit area and the number of elements used, and it is possible to
By being able to control the -1ess type level shifter, it is possible to reduce power consumption and the number of elements used, reduce the integrated circuit area, and save design time when level shifting many logic signals. Shortening is possible.

Moreover, if the configuration of the present invention is adopted, Ratio -1ess
There is no need to provide a level shifter at the input (2) of the type CMO8 circuit.

[Brief explanation of the drawing]

FIG. 1 shows a conventional Ratio-type level shifter, and FIGS. 2 to 4 show Ratio-type level shifters used in the present invention.
Figures 5a and 6a are circuit diagrams of the ratio-1ess level shifter used in the present invention, Figures 5b and 6 are operational waveform diagrams, and Figure 7
The figure is a circuit diagram of another Ratio-1ess type level shifter used in the present invention, and FIGS.
FIG. 12 is a circuit diagram showing an embodiment of the present invention. 21.41...P channel FET, 23.24
゜42.43...N-channel FET, φ...
...Clock pulse, co...Output capacity, 6
1, 62...Ratio type level shifter 65, 67 to 69---°-°Ratjo -1es
S type level/L/S7ri.

Claims (1)

[Claims] 1. Criteria! Pressing bell E. and a clock pulse having a first voltage level E1 different from this voltage level and a second voltage level (E2, where IE2
-EoI>IE, -EOl) of a flip-flop configuration that shifts the level in the same phase to the clock pulse with -EoI>IE, -EOl)
A clock pulse from this level shifter is supplied to the gate of a voltage level E of the at jo type. one channel type IG-FET charges the output capacitance to another voltage level E2 higher than the first voltage level when the clock pulse from the level shifter is at the other level. E2, the charge charged in the output capacitor is discharged, and the voltage level of the capacitor is set to the reference voltage level E. and a plurality of Ratio-1ess type CMO8 circuits to which the other channel type I (, -FET and a reference voltage level E. or a signal ■ at the level of the first voltage level E1 is inputted. A level shift circuit featuring: