CN101561609B - Active array substrate, liquid crystal display panel and method for manufacturing active array substrate - Google Patents
Active array substrate, liquid crystal display panel and method for manufacturing active array substrate Download PDFInfo
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- CN101561609B CN101561609B CN2009101465679A CN200910146567A CN101561609B CN 101561609 B CN101561609 B CN 101561609B CN 2009101465679 A CN2009101465679 A CN 2009101465679A CN 200910146567 A CN200910146567 A CN 200910146567A CN 101561609 B CN101561609 B CN 101561609B
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Abstract
The invention provides an active array substrate, a liquid crystal display panel and a method for manufacturing the active array substrate. The active array substrate comprises a substrate, a plurality of scanning lines, a plurality of data wires and a plurality of grid electrode patch cords arranged on the substrate, wherein the grid electrode patch cords have a plurality of first parts, a plurality of patch cord parts connected with the corresponding first parts, a plurality of connection holes and a plurality of second parts. The second parts and the first parts are not arranged at the samelayer and one of the second parts is electrically connected with the corresponding first part by one of the connection holes.
Description
Technical field
The invention relates to a kind of active array substrate, display panels and make the method for active array substrate, particularly about the manufacture method of the uniform narrow frame active array substrate of a kind of video picture, display panels and the uniform narrow frame active array substrate of video picture.
Background technology
Flat-panel screens (Flat Panel Display) is at present main popular display, wherein display panels more because have that external form is frivolous, power saving and feature such as radiationless, and be widely used on the electronic products such as computer screen, mobile phone, PDA(Personal Digital Assistant), flat-surface television.The principle of work of display panels is the ordered state that the voltage difference that utilize to change the liquid crystal layer two ends changes the liquid crystal molecule in the liquid crystal layer, in order to change the light transmission of liquid crystal layer, to cooperate backlight module again the light source that provided with display image.
Fig. 1 is the synoptic diagram of known display panels.As shown in Figure 1, display panels 100 comprises active array substrate 110 and subtend substrate 190, and liquid crystal layer (not illustrating) promptly is folded between active array substrate 110 and the subtend substrate 190.Subtend substrate 190 can be colored filter.Active array substrate 110 comprises many data lines 130, many gate lines 150, many supplementary gate polar curves 155, first rim area 180, second rim area 185, image display area 195 and driver modules 101.Many data line 130 is arranged at image display area 195 with many gate lines 150.Many supplementary gate polar curve 155 is arranged at first rim area 180 and second rim area 185.Driver module 101 is electrically connected on many supplementary gate polar curves 155, is fed into many gate lines 150 in order to a plurality of signals that will be provided via many supplementary gate polar curves 155.Driver module 101 is electrically connected on many data lines 130 in addition, is fed into a plurality of pixel cell (not shown)s in order to a plurality of data-signals that will be provided via many data lines 130.Display panels 100 is promptly controlled a plurality of data-signals according to a plurality of signals and is write to a plurality of pixel cells, in order to display image.
Because in the structure of known active array substrate 110, the number of supplementary gate polar curve 155 equals the number of gate line 150 in fact, so active array substrate 110 just need provide enough wide first rim area 180 and second rim area 185, in order to many supplementary gate polar curves 155 to be set.Yet, because the display that most of portable electronic devices is installed is small-sized display panels, so how to reduce the rim area area to reduce the important topic that the infrabasal plate size is the small design display panels.
Summary of the invention
In view of aforementioned, the purpose of this invention is to provide a kind of active array substrate.
Based on above-mentioned purpose, the invention provides a kind of active array substrate, comprise substrate; The multi-strip scanning line is arranged on the described substrate; Many data lines are arranged on the described substrate also vertical with described these sweep traces substantially; And many grid patchcords (gate tracking line), be arranged on the described substrate, wherein each described grid patchcord is electrically connected with a corresponding gate line respectively, and each described grid patchcord is to be arranged in parallel with described these data lines substantially, and wherein each described grid patchcord has: a plurality of first one; A plurality of commentaries on classics line portion and described first corresponding connection; A plurality of connections hole; And a plurality of connecting portions, be with described these first one be the different layers configuration, be to connect one of holes and corresponding described first electrical connection one of in wherein said these connecting portions by described these.
Active array substrate provided by the invention more comprises: a plurality of on-off elements, each described on-off element are to be electrically connected with corresponding described data line and described sweep trace; A plurality of pixel electrodes, each described pixel electrode are to be electrically connected with corresponding described on-off element; And many shared lines, be arranged on the described substrate, substantially parallel with described these sweep traces, and form a storage capacitors with a drain electrode of corresponding described on-off element.
The described grid patchcord of each of active array substrate provided by the invention has more an auxiliary insulating layer between one of described these first one and described these data lines.
The described grid patchcord of each of active array substrate provided by the invention has more a semiconductor-assisted layer between described auxiliary insulating layer and described data line.
Based on above-mentioned purpose, the invention provides a kind of method of making active array substrate, comprising: a substrate is provided; Form one first conductive layer on described substrate; Described first conductive layer of patterning with form multi-strip scanning line, a plurality of grid, a plurality of first one and with the commentaries on classics line portion of corresponding described first connection; Form a gate insulator on described these sweep traces, grid and first one; Form semi-conductor layer on described gate insulator; The described semiconductor layer of patterning is to form a plurality of channel layers in described these corresponding grid tops; The described gate insulator of patterning connects the hole to expose described commentaries on classics line portion to form one; Form one second conductive layer on described semiconductor layer; Described second conductive layer of patterning is to form many data lines, a plurality of source electrode and drain electrode and a plurality of connecting portion, and wherein every described connecting portion is to be electrically connected with described corresponding commentaries on classics line portion by described connection hole; Form a protective seam comprehensively; The described protective seam of patterning exposes described drain electrode to form a contact hole; And form a pixel electrode on described protective seam and be electrically connected with described drain electrode by described contact hole.
Based on above-mentioned purpose, the invention provides a kind of display panels, comprise above-mentioned active array substrate, subtend substrate and liquid crystal layer, between described active array substrate and described subtend substrate.
The invention provides a kind of active array substrate and manufacture method thereof that has narrow frame or do not have frame.
The invention provides a kind of active array substrate and manufacture method thereof with low load effect.
According to technical scheme provided by the invention, can avoid the generation of uneven load effect, thereby improve display quality.
Description of drawings
Fig. 1 is the synoptic diagram of known display panels;
Fig. 2 A to Fig. 2 G is the manufacture method process flow diagram of the active array substrate of the first embodiment of the present invention;
Fig. 3 is the active array substrate of the second embodiment of the present invention;
Fig. 4 is the active array substrate of the third embodiment of the present invention; And
Fig. 5 is a display panels of the present invention.
Drawing reference numeral
1 display panels
100 display panels
101 driver modules
110 active array substrates
130 data lines
150 gate lines
155 supplementary gate polar curves
180 first rim area
185 second rim area
190 subtend substrates
195 image display areas
200 display panels
211 substrates
221 grids
240 auxiliary insulating layers
241 gate insulators
242 first protective seams
246 second protective seams
250 sweep traces
252 first ones
254 change line portion
256 connecting portions
260 pixel electrodes
270 bridging lines
272 capacitor lower electrodes
281 channel layers
282 semiconductor-assisted layers
290 data lines
292 source electrodes
294 drain electrodes
296 electric capacity top electrodes
300 liquid crystal layers
400 subtend substrates
H1, H2 connect the hole
H3 contacts the hole
Embodiment
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended accompanying drawing, be described in detail below.
First embodiment
Fig. 2 A to Fig. 2 G is the manufacture method process flow diagram of the active array substrate of the first embodiment of the present invention.
Please refer to Fig. 2 A, substrate 211 is provided earlier, form first conductive layer (indicate) on substrate 211, then patterning first conductive layer with form sweep trace 250,250a, grid 221,221a, bridging line 270, capacitor lower electrode 272, first one 252 and change line portion 254.The mode of patterning first conductive layer for example is to can be known methods such as exposure imaging etching.Changeing line portion 254 is to be connected with first one 252, for a pixel cell, first one 252 two ends can be respectively changeed line portion 254 and are connected with one, and just first one 252 and two commentaries on classics line portions 254 can constitute an anti-C word shape or I word shape substantially, but are not limited thereto.Capacitor lower electrode 272 is to be connected with bridging line 270.
Please refer to profile line A-A ' and the corresponding sectional view of B-B ' among Fig. 2 A.At the sectional view of profile line A-A ', grid 221 is the on-off elements that correspond in the pixel cell, be the thin film transistor (TFT) place for example, and capacitor lower electrode 272 is to correspond to the storage capacitors place.Sectional view at profile line B-B ', first one 252 and change the part that line portion 254 be grid patchcord (sign), if being design, the grid patchcord of pixel cell correspondence is connected with the grid 221a and the corresponding scanning line 250a at described thin film transistor (TFT) place, then grid 221a is and first one 252 or change line portion 254 and link together when the step of above-mentioned patterning first conductive layer, shown in Fig. 2 A.
Please refer to Fig. 2 B, form auxiliary insulating layer 240 on first one 252, but and the sweep trace 250 of cover part, bridging line 270 and/or commentaries on classics line portion 254, for example, auxiliary insulating layer 240 can comprehensive covering first one 252, the material of auxiliary insulating layer 240 for example is inorganic material or organic material, and inorganic material for example is silicon nitride or monox or the like.
Please refer to Fig. 2 C, comprehensive formation gate insulator 241 covers above-mentioned all elements, afterwards, form semiconductor layer (indicating) on gate insulator 241 the back patterned semiconductor layer to form channel layer 281 and semiconductor-assisted layer 282.The mode of patterned semiconductor layer for example can be known methods such as exposure imaging etching.What must pay special attention to is, channel layer 281 is positioned at grid 221 tops constituting the part of thin film transistor (TFT), semiconductor-assisted layer 282 be positioned at first one 252 and auxiliary insulating layer 240 tops and with the part of its formation grid patchcord.
Next please refer to Fig. 2 D, patterned grid insulating layer 241 makes and form connection hole H1 and H2 above changeing line portion 254, shown in Fig. 2 D, for single pixel cell, two gate insulators 241 that change the top of line portion 254 have the hole H1 of connection respectively and H2 changes line portion 254 to expose two respectively.
Please refer to Fig. 2 E, comprehensive formation second conductive layer (not indicating) is in said elements, and patterning second conductive layer is to form data line 290, source electrode 292, drain electrode 294, electric capacity top electrode 296 and connecting portion 256.Connecting hole H1 or H2 does not overlap with described these data lines 290.The mode of patterning second conductive layer for example can be known methods such as exposure imaging etching.What must pay special attention to is, data line 290 is vertical with bridging line 270 and sweep trace 250 substantially, connecting portion 256 is positioned at commentaries on classics line portion 254 tops and is electrically connected with commentaries on classics line portion 254 by connecting hole H1 and H2, therefore, single connecting portion 256 is electrically connected with the commentaries on classics line portion 254 of two adjacent pixel cells, thus, just finish the grid patchcord.Single grid patchcord comprises a plurality of first one 252, a plurality of commentaries on classics line portion 254 and a plurality of connecting portion 256, more selectivity comprise auxiliary insulating layer 240 with and/or (a plurality of) semiconductor-assisted layer 282.
Please refer to Fig. 2 F; comprehensive formation first protective seam 242 and second protective seam 246 are to cover said elements; patterning first protective seam 242 and second protective seam 246 will drain and 294 come out to form contact hole H3 then; wherein first protective seam 242 and second protective seam, 246 alternatives are selected a formation; do not limit at this, the material of first protective seam 242 and second protective seam 246 can be organic material or non-organic insulation.
At last, please refer to Fig. 2 G, corresponding each pixel cell forms pixel electrode 260.Just finish the active array substrate of present embodiment, the material of pixel electrode 260 can be reflective conductive metals or transparent conductive metal oxide.Active array substrate comprises substrate 211, multi-strip scanning line 250, many shared lines 270, many data lines 290, many grid patchcords, a plurality of on-off element and a plurality of pixel electrodes 260.Each grid patchcord has a plurality of first one 252, a plurality of commentaries on classics line portion 254, a plurality of connections hole H1, H2 and a plurality of connecting portion 256.A plurality of connecting portions 256 be with described these first one 252 be that the different layers configuration forms, be to connect one of hole H1, H2 and corresponding described first one 252 by described these to be electrically connected one of in wherein said these connecting portions 256.Described these parts of first one 252 are to overlap with one of described these data lines 290.Described these connecting portions 256 are to be identical layer with described these data lines 290.Each described grid patchcord has more auxiliary insulating layer 240 between one of described these first one 252 and described these data lines 290, and described grid patchcord has more semiconductor-assisted layer 282 between described auxiliary insulating layer 240 and described data line 290.Described these connect hole H1, H2 and do not overlap 290 with described these data lines 290.Each described on-off element is to be electrically connected with corresponding described data line 290 and described sweep trace 250, each described pixel electrode 260 is to be electrically connected with the drain electrode 294 of corresponding described on-off element, bridging line 270 is parallel with described these sweep traces 250 substantially, and forms storage capacitors with corresponding electric capacity top electrode 296.
What must pay special attention to is, because the setting of auxiliary insulating layer 240 and semiconductor-assisted layer 282, therefore the load effect that first one 252 and data line are 290 can reduce, and first one 252 be to be covered the problem that can avoid aperture opening ratio to reduce by data line 290 substantially.And because the setting of grid patchcord, the setting that can reduce or omit the supplementary gate polar curve 155 in first rim area 180 and/or second rim area 185 reaches narrow frame or does not have the purpose of frame.
Second embodiment
Fig. 3 is the active array substrate of the second embodiment of the present invention.
Please refer to Fig. 3, not existing together with first embodiment only is only a part of and first one 252 overlapping of semiconductor-assisted layer 282 and data line 290, reaches the purpose that a little reduces load effect.All the other elements parts and manufacture method are identical with first embodiment or similar, do not give unnecessary details at this.
The 3rd embodiment
Fig. 4 is the active array substrate of the third embodiment of the present invention.
Please refer to Fig. 4, not existing together with first embodiment only is that semiconductor-assisted layer 282 and data line 290 fully with first one 252 skew and do not overlap, reaches the purpose that reduces load effect.All the other elements parts and manufacture method are identical with first embodiment or similar, do not give unnecessary details at this.
The 4th embodiment
The present invention more proposes a kind of display panels, as shown in Figure 5, display panels 1 comprise in the active array substrate 200 of the various embodiments described above any, subtend substrate 400 and liquid crystal layer 300.Liquid crystal layer 300 is between described active array substrate 200 and described subtend substrate 400.Subtend substrate 400 can be colored filter substrate or electrode base board.
According to technical scheme provided by the invention, can avoid the generation of uneven load effect, thereby improve display quality.
Though the present invention discloses as above with embodiment; right its is not in order to qualification the present invention, any person of ordinary skill in the field, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when being as the criterion with claim institute confining spectrum.
Claims (16)
1. an active array substrate is characterized in that, described active array substrate comprises:
One substrate;
The multi-strip scanning line is arranged on the described substrate;
Many data lines are arranged on the described substrate also vertical with described these sweep traces substantially; And
Many grid patchcords are arranged on the described substrate, and wherein each described grid patchcord is electrically connected with a corresponding sweep trace respectively, and each described grid patchcord is to be arranged in parallel with described these data lines substantially, and wherein each described grid patchcord has:
A plurality of first one;
A plurality of commentaries on classics line portion and described first corresponding connection;
A plurality of connections hole; And
A plurality of connecting portions, be with described these first one be the different layers configuration, wherein each described connecting portion is the described connection hole and the electrical connection of corresponding described commentaries on classics line portion by correspondence.
2. active array substrate as claimed in claim 1 is characterized in that, described these parts of first one are to overlap with one of described these data lines.
3. active array substrate as claimed in claim 1 is characterized in that, described these connecting portions be with described these data lines be identical layer.
4. active array substrate as claimed in claim 1, it is characterized in that, each described grid patchcord has more an auxiliary insulating layer between one of described these first one and described these data lines, and wherein said grid patchcord has more a semiconductor-assisted layer between described auxiliary insulating layer and described data line.
5. active array substrate as claimed in claim 1 is characterized in that, it is not overlap with described these data lines that described these connect the hole.
6. active array substrate as claimed in claim 1 is characterized in that, described active array substrate more comprises:
A plurality of on-off elements, each described on-off element are to be electrically connected with corresponding described data line and described sweep trace;
A plurality of pixel electrodes, each described pixel electrode are to be electrically connected with corresponding described on-off element;
A plurality of electric capacity top electrodes; And
Many shared lines are arranged on the described substrate, and are substantially parallel with described these sweep traces, and form a storage capacitors with corresponding described electric capacity top electrode.
7. active array substrate as claimed in claim 1 is characterized in that, described these first one is to overlap with the part of described these data lines.
8. active array substrate as claimed in claim 1 is characterized in that, described these first one is not overlap with one of described these data lines.
9. active array substrate as claimed in claim 1 is characterized in that, each described grid patchcord has more a semiconductor-assisted layer between one of described these first one and described these data lines.
10. a display panels is characterized in that, described display panels comprises:
As each described active array substrate in the claim 1 to 9;
One subtend substrate; And
One liquid crystal layer is between described active array substrate and described subtend substrate.
11. a method of making active array substrate is characterized in that, described method comprises:
One substrate is provided;
Form one first conductive layer on described substrate;
Described first conductive layer of patterning with form multi-strip scanning line, a plurality of grid, a plurality of first one and with the commentaries on classics line portion of corresponding described first connection;
Form a gate insulator on described these sweep traces, grid and first one;
Form semi-conductor layer on described gate insulator;
The described semiconductor layer of patterning is to form a plurality of channel layers in described these corresponding grid tops;
The described gate insulator of patterning connects the hole to expose described commentaries on classics line portion to form one;
Form one second conductive layer on described semiconductor layer;
Described second conductive layer of patterning to be forming many data lines, a plurality of source electrode and drain electrode and a plurality of connecting portion, and wherein every described connecting portion is to be electrically connected with corresponding described commentaries on classics line portion by described connection hole;
Form a protective seam comprehensively;
The described protective seam of patterning exposes described drain electrode to form a contact hole; And
Form a pixel electrode on described protective seam and be electrically connected with described drain electrode by described contact hole, wherein: described grid and described first one or described commentaries on classics line portion link together, and described commentaries on classics line portion is connected in described first one one or both ends.
12. method as claimed in claim 11 is characterized in that, the step of the described semiconductor layer of patterning comprises that more formation one semiconductor-assisted layer is in described first top.
13. method as claimed in claim 11 is characterized in that, before the step that forms described gate insulator, more comprises forming an auxiliary insulating layer on described these first one.
14. method as claimed in claim 11 is characterized in that, the step of described first conductive layer of patterning more comprises the many shared lines of formation.
15. method as claimed in claim 11 is characterized in that, described these first one is to overlap with described these data lines to small part.
16. method as claimed in claim 11 is characterized in that, described these first one is not overlap with described these data lines.
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| CN2009101465679A CN101561609B (en) | 2009-06-08 | 2009-06-08 | Active array substrate, liquid crystal display panel and method for manufacturing active array substrate |
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| CN2009101465679A CN101561609B (en) | 2009-06-08 | 2009-06-08 | Active array substrate, liquid crystal display panel and method for manufacturing active array substrate |
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| CN101561609B true CN101561609B (en) | 2010-10-13 |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102385200B (en) * | 2010-08-27 | 2016-01-13 | 上海天马微电子有限公司 | Array base palte and preparation method thereof, display panels |
| TWI441122B (en) * | 2011-12-30 | 2014-06-11 | Au Optronics Corp | Array substrate structure of display panel and method of making the same |
| CN104731405B (en) * | 2015-03-09 | 2018-01-19 | 上海天马微电子有限公司 | A kind of touch control display apparatus and its manufacture method |
| CN107976849A (en) * | 2017-12-29 | 2018-05-01 | 深圳市华星光电技术有限公司 | Array base palte and preparation method thereof |
| CN113689785B (en) * | 2020-05-19 | 2023-04-25 | 友达光电股份有限公司 | Display device |
| CN113035888B (en) * | 2020-08-21 | 2023-06-02 | 友达光电股份有限公司 | Electronic device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5835177A (en) * | 1995-10-05 | 1998-11-10 | Kabushiki Kaisha Toshiba | Array substrate with bus lines takeout/terminal sections having multiple conductive layers |
| CN101093329A (en) * | 2006-06-21 | 2007-12-26 | Lg.菲利浦Lcd株式会社 | Array substrate for in-plane switching mode liquid crystal display device and method of fabricating the same |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5835177A (en) * | 1995-10-05 | 1998-11-10 | Kabushiki Kaisha Toshiba | Array substrate with bus lines takeout/terminal sections having multiple conductive layers |
| CN101093329A (en) * | 2006-06-21 | 2007-12-26 | Lg.菲利浦Lcd株式会社 | Array substrate for in-plane switching mode liquid crystal display device and method of fabricating the same |
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