CN112542505B

CN112542505B - Pixel array substrate

Info

Publication number: CN112542505B
Application number: CN202011607034.9A
Authority: CN
Inventors: 郑和宜; 黄馨谆
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2020-08-05
Filing date: 2020-12-30
Publication date: 2023-05-05
Anticipated expiration: 2040-12-30
Also published as: CN112542505A; TW202207200A; TWI735304B

Abstract

A pixel array substrate comprises a substrate, a plurality of pixel structures and a plurality of conductive elements. The pixel structure array is arranged on the substrate to define a plurality of first walkways and a plurality of second walkways. The pixel structures are arranged in a plurality of pixel rows. Each conductive element is electrically connected with at least one pixel row. Each conductive element comprises a first part arranged on the first pavement and a second part arranged on the second pavement. The conductive elements include a plurality of first conductive elements and a plurality of second conductive elements. The first portions of the first conductive elements and the first portions of the second conductive elements are alternately arranged in the first direction and are respectively arranged on different first walkways. The first portion of the first conductive element and the first portion of the second conductive element are disposed on the nth first aisle and the (n+1) th first aisle, respectively. The second part of the first conductive element and the second part of the second conductive element are respectively arranged on the mth second walkway and the (m+p) th second walkway, and n, m and p are positive integers.

Description

Pixel array substrate

Technical Field

The invention relates to a pixel array substrate.

Background

The light emitting diode display panel comprises an active element substrate and a plurality of light emitting diode elements transposed on the active element substrate. The LED display panel has the advantages of electricity saving, high efficiency, high brightness, quick response time and the like by inheriting the characteristics of the LEDs. In addition, compared with the organic light-emitting diode display panel, the light-emitting diode display panel has the advantages of easy color adjustment, long light-emitting service life, no image branding and the like. Therefore, the led display panel is regarded as a display technology of the next generation.

The pixel structures disposed in the active region of the led display panel are electrically connected to the driving circuit by using fan-out lines. The fan-out wires can be arranged in the peripheral area or the active area of the light-emitting diode display panel. However, the process is not limited to the above-described process,

if a plurality of fan-out wires are arranged in the peripheral area, an ultra-narrow frame or even a frame-free light-emitting diode display panel cannot be realized; if multiple fan-out wires are disposed in the active region, the fan-out wires occupy too much area of the active region, which affects the design flexibility of the pixel structure.

Disclosure of Invention

The invention provides a pixel array substrate with good performance.

The pixel array substrate comprises a substrate, a plurality of pixel structures and a plurality of conductive elements. The plurality of pixel structure arrays are arranged on the substrate to define a plurality of first walkways and a plurality of second walkways between the plurality of pixel structures, wherein the plurality of first walkways are arranged in sequence in a first direction, the plurality of second walkways are arranged in sequence in a second direction y, and the first direction and the second direction are staggered. The plurality of pixel structures are arranged in a plurality of pixel rows. The plurality of pixel structures of each pixel row are arranged in the second direction. Each conductive element is electrically connected with at least one pixel row. Each conductive element comprises a first part arranged on a first pavement and a second part arranged on a second pavement. The plurality of conductive elements comprise a plurality of first conductive elements and a plurality of second conductive elements, and a plurality of first portions of the plurality of first conductive elements and a plurality of first portions of the plurality of second conductive elements are alternately arranged in a first direction and are respectively arranged on a plurality of different first walkways. The first part of the first conductive element and the first part of the second conductive element are respectively arranged on the nth first walkway and the (n+1) th first walkway, the second part of the first conductive element and the second part of the second conductive element are respectively arranged on the mth second walkway and the (m+p) th second walkway, and n, m and p are positive integers.

Drawings

Fig. 1 is a top view of a pixel array substrate 10 according to an embodiment of the invention.

Fig. 2 schematically depicts a circuit of a pixel structure PX according to an embodiment of the invention.

Fig. 3 schematically depicts a circuit of a multiplexer MUX according to an embodiment of the invention.

Fig. 4 is a schematic layout diagram of an intersection r1 of a first portion 111a of a first conductive element 111 and a second portion 112c of a second conductive element 112 according to an embodiment of the invention.

Fig. 5 is a schematic layout diagram of an intersection r2 between a third portion 112c of a second conductive element 112 and a second portion 111b of a first conductive element 111 according to an embodiment of the invention.

Fig. 6 is a top view of a pixel array substrate 10A according to an embodiment of the invention.

Fig. 7 is a top view of a pixel array substrate 10B according to an embodiment of the invention.

Fig. 8 is a schematic layout diagram of an intersection r3 between a first portion 112a of a second conductive element 112 and a second portion 113b of a third conductive element 113 according to an embodiment of the invention.

Fig. 9 is a schematic layout diagram of an intersection r1' between a third portion 113c of a third conductive element 113 and a second portion 112b of a second conductive element 112 according to an embodiment of the invention.

Fig. 10 is a top view of a pixel array substrate 10C according to an embodiment of the invention.

Reference numerals illustrate:

10. 10A, 10B, 10C: pixel array substrate

102: substrate board

110: conductive element

110a, 111a, 112a, 113a: first part

110b, 111b, 112b, 113b: second part

110c, 111c, 112c, 113c: third part

111: first conductive element

111a-1, 112c-1, 113c-1,: a first sub-part

111a-2, 112c-2, 113c-2: a second sub-part

112: second conductive element

113: third conductive element

C1: capacitance device

C. Cm, cm+1, cm+2: second walkway

DL, DLR, DLG, DLB: data line

GPX: pixel group

in: data input terminal

Lm_ R, lm _ G, lm _b: select line

LED, led_ R, LED _ G, LED _b: light emitting diode element

A MUX: multiplexer

PX: pixel structure

PXR: pixel row

R, rn-2, rn-1, rn, rn+1, rn+2: first walkway

r1, r1', r2, r3: the intersection

SL: scanning line

SPX: sub-pixel structure

Spx_r: first sub-pixel structure

Spx_g: second sub-pixel structure

Spx_b: third sub-pixel structure

SPC: sub-pixel driving circuit

T1: first transistor

T1a, T2a, tma: first end

T1b, T2b, tmb: second end

T1c, T2c, tmc: control terminal

T2: second transistor

Tm_ R, tm _ G, tm _b: transistor with a high-voltage power supply

W: width of (L)

x: first direction

y: second direction

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that there are other elements between the two elements.

As used herein, "about," "approximately," or "substantially" includes both the values and average values within an acceptable deviation of the particular values as determined by one of ordinary skill in the art, taking into account the particular number of measurements and errors associated with the measurements in question (i.e., limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the values, or within ±30%, ±20%, ±10%, ±5%. Further, as used herein, "about," "approximately," or "substantially" may be used to select a more acceptable range of deviations or standard deviations depending on the optical, etching, or other properties, and may not be used with one standard deviation for all properties.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Referring to fig. 1, the pixel array substrate 10 includes a substrate 102 and a plurality of pixel structures PX disposed on the substrate 102. The substrate 102 is mainly used for carrying a plurality of pixel structures PX. In this embodiment, the substrate 102 may be made of glass, quartz, organic polymer, or opaque/reflective material (e.g., wafer, ceramic, or other suitable material), or other suitable material.

Referring to fig. 1 and 2, in the present embodiment, each pixel structure PX may optionally include a plurality of sub-pixel structures SPX for displaying different colors. Each sub-pixel structure SPX may include a sub-pixel driving circuit SPC and a display element electrically connected to the sub-pixel driving circuit SPC. In this embodiment, the display element is, for example, a light emitting diode element LED. In this embodiment, the light emitting diode element LED is an inorganic light emitting diode element, such as, but not limited to: micro light emitting diodes (Micro LEDs) sub-millimeter light emitting diodes (mini LEDs) or other sized inorganic light emitting diodes. However, the invention is not limited thereto, and in other embodiments, the display element may be other kinds of display elements; for example, in another embodiment, the display element may include an organic electroluminescent layer; in yet another embodiment, the display element may include a liquid crystal layer.

Referring to fig. 2, in the present embodiment, the sub-pixel driving circuit SPC of each sub-pixel structure SPX includes a first transistor T1, a second transistor T2 and a capacitor C1, wherein the first end T1a of the first transistor T1 is electrically connected to the data line DL, the control end T1C of the first transistor T1 is electrically connected to the scan line SL, the second end T1b of the first transistor T1 is electrically connected to the control end T2C of the second transistor T2, the first end T2a of the second transistor T2 is electrically connected to the power line (not shown), the capacitor C1 is electrically connected to the second end T1b of the first transistor T1 and the first end T2a of the second transistor T2, the second end T2b of the second transistor T2 is electrically connected to the first electrode of the light emitting diode element LED, and the second electrode (not shown) of the light emitting diode element LED is electrically connected to the common line (not shown).

In short, in the present embodiment, the subpixel driving circuit SPC can selectively adopt a 2T1C architecture. However, the present invention is not limited thereto, and in other embodiments, the sub-pixel driving circuit SPC may also employ other architectures, such as, but not limited to: 1T1C, 2T1C, 3T2C, 4T1C, 4T2C, 5T1C, 5T2C, 6T1C, 6T2C, 7T2C, or any possible architecture.

For example, in the present embodiment, each pixel structure PX may include a first sub-pixel structure spx_r, a second sub-pixel structure spx_g, and a third sub-pixel structure spx_b for displaying a first color, a second color, and a third color, respectively; the first sub-pixel structure spx_r, the second sub-pixel structure spx_g and the third sub-pixel structure spx_b respectively comprise a light emitting diode element led_r, a light emitting diode element led_g and a light emitting diode element led_b which can emit a first color, a second color and a third color; the sub-pixel driving circuit SPC of the first sub-pixel structure spx_r, the sub-pixel driving circuit SPC of the second sub-pixel structure spx_g, and the sub-pixel driving circuit SPC of the third sub-pixel structure spx_b are electrically connected to the data line DLR, the data line DLG, and the data line DLB, respectively; the plurality of sub-pixel driving circuits SPC of the first sub-pixel structure spx_r, the second sub-pixel structure spx_g and the third sub-pixel structure spx_b of the pixel structure PX can be electrically connected to the same scan line SL. In the present embodiment, the first color, the second color and the third color are, for example, red, green and blue, but the invention is not limited thereto.

Referring to fig. 1, the pixel array substrate 10 further includes a plurality of conductive elements 110, the plurality of pixel structures PX are arranged in a plurality of pixel rows PXR, the plurality of pixel structures PX of each pixel row PXR are arranged in the second direction y, and each conductive element 110 is electrically connected to at least one pixel row PXR.

Referring to fig. 1 and 3, for example, in the present embodiment, the pixel array substrate 10 may optionally include a plurality of multiplexers MUX disposed between a plurality of pixel structures PX, wherein each multiplexer MUX is electrically connected to a corresponding one of the conductive elements 110 and a corresponding at least one of the pixel rows PXR. In other words, in the present embodiment, each conductive element 110 is electrically connected to the corresponding at least one pixel row PXR through the multiplexer MUX. However, the present invention is not limited thereto, and in other embodiments, the pixel array substrate 10 may not include the multiplexer MUX, and the conductive element 110 may be electrically connected to the corresponding at least one pixel row PXR in other manners.

For example, in the present embodiment, each multiplexer MUX may include a plurality of transistors tm_ R, tm _ G, tm _b, each transistor tm_ R, tm _ G, tm _b has a first end Tma, a second end Tmb and a control end Tmc, the first ends Tma, tma and Tma of the transistors tm_r, tmg and Tmb are electrically connected to the same conductive element 110, the control end Tmc, tmc and Tmc of the transistors tm_r, tmc and Tmb are electrically connected to the selection line lm_r, lm_g and lm_b, respectively, the second end Tmb of the transistors tm_r, tmb and Tmb are electrically connected to a plurality of data lines DLR, DLG, DLB electrically connected to the corresponding at least one pixel row PXR, respectively.

Referring to fig. 1, a plurality of pixel structures PX are arranged on a substrate 102 to define a plurality of first tracks R and a plurality of second tracks C between the plurality of pixel structures PX. The first walkways R of the substrate 102 are sequentially arranged in the first direction x, the second walkways C of the substrate 102 are sequentially arranged in the second direction y, and the first direction x is staggered with the second direction y. For example, in the present embodiment, the first direction x and the second direction y may be substantially perpendicular. However, the present invention is not limited thereto, and in other embodiments, the first direction x and the second direction y may have angles other than 90 °.

Each conductive element 110 includes a first portion 110a disposed on a first aisle R and a second portion 110b disposed on a second aisle C.

The plurality of conductive elements 110 of the pixel array substrate 10 include a plurality of first conductive elements 111 and a plurality of second conductive elements 112, and a plurality of first portions 111a of the plurality of first conductive elements 111 and a plurality of first portions 112a of the plurality of second conductive elements 112 are alternately arranged in the first direction x and respectively disposed on the plurality of different first walkways R.

It should be noted that the first portion 111a of the first conductive element 111 and the first portion 112a of the second conductive element 112 are disposed on the nth first channel Rn and the (n+1) th first channel rn+1, respectively, and the second portion 111b of the first conductive element 111 and the second portion 112b of the second conductive element 112 are disposed on the mth second channel Cm and the (m+p) th second channel cm+1, respectively, wherein n, m and p are positive integers.

That is, the

second portions

111b and 112b of the adjacent first conductive element 111 and second conductive element 112 are dispersed on different second walkways C, but not concentrated on the same second walkway C. Therefore, the width W of the second channel C (i.e., the lateral channel) in the second direction y can be reduced, which helps the substrate 102 provide more area to set the important pixel structures PX, and improves the design flexibility of the pixel structures PX.

For example, in the present embodiment, p may be optionally equal to 1; that is, the first portion 111a of the first conductive element 111 and the first portion 112a of the second conductive element 112 are disposed on the nth first aisle Rn and the (n+1) th first aisle rn+1, respectively, and the second portion 111b of the first conductive element 111 and the second portion 112b of the second conductive element 112 are disposed on the (m) th second aisle Cm and the (m+1) th second aisle cm+1, respectively. However, the present invention is not limited thereto, and in other embodiments, p may be other positive integers other than 1.

In the present embodiment, each conductive element 110 may further optionally include a third portion 110c disposed on another first aisle R, wherein the first portion 110a of each conductive element 110 has a data input terminal in electrically connected to a driving circuit (e.g., without limitation, a driving chip; not shown), the second portion 110b of each conductive element 110 is electrically connected to the first portion 110a of each conductive element 110, and the third portion 110c of each conductive element 110 is electrically connected to the second portion 110b of each conductive element 110 and at least one pixel row PXR.

In the present embodiment, the third portion 111c of the first conductive element 111 and the third portion 112c of the second conductive element 112 can be disposed on the n-j first walkways Rn-2 and the n-k first walkways Rn-1, j and k are positive integers, and j > k, respectively. For example, in this embodiment, j may be optionally equal to 2, and k may be optionally equal to 1; that is, the third portion 111c of the first conductive element 111 and the third portion 112c of the second conductive element 112 are disposed on the n-2 th first walkway Rn-2 and the n-1 st first walkway Rn-1, respectively. However, the present invention is not limited thereto, and in other embodiments, j and k may be other positive integers other than 2 and 1, as long as j > k.

Fig. 4 is a schematic layout (layout) of the intersection r1 of the first portion 111a of the first conductive element 111 and the second portion 112b of the second conductive element 112 according to an embodiment of the invention. Fig. 4 corresponds to the interlace r1 of fig. 1.

Referring to fig. 1 and 4, in the present embodiment, the first portion 111a of the first conductive element 111 and the first portion 112a of the second conductive element 112 are respectively disposed on the adjacent first walkways Rn, rn+1, and the first portion 111a of the first conductive element 111 spans the second portion 112b of the second conductive element 112.

Specifically, in the present embodiment, the first portion 111a of the first conductive element 111 includes a first sub-portion 111a-1 and a plurality of second sub-portions 111a-2 connected to two ends of the first sub-portion 111a-1, wherein the first sub-portion 111a-1 of the first portion 111a of the first conductive element 111 spans a portion of the second portion 112b of the second conductive element 112, and the first sub-portion 111a-1 of the first portion 111a of the first conductive element 111 and a portion of the second portion 112b of the second conductive element 112 belong to different two conductive layers.

For example, in the present embodiment, an insulating layer (not shown) may be sandwiched between the first metal layer and the second metal layer, the first sub-portion 111a-1 of the first portion 111a of the first conductive element 111 may belong to the first metal layer, and the second sub-portion 111a-2 of the first portion 111a of the first conductive element 111 and a portion of the second portion 112b of the second conductive element 112 may belong to the second metal layer, but the invention is not limited thereto.

Referring to fig. 1, it is noted that, in the present embodiment, the first portion 111a of the first conductive element 111 spans the second portion 112b of the second conductive element 112; that is, in the top view of the pixel array substrate 10, a portion of the second portion 112b of the second conductive element 112 is disposed between the adjacent first portion 111a of the first conductive element 111 and the first portion 112a of the second conductive element 112. Therefore, the area between the pixel structures PX can be more effectively utilized, the overall arrangement range of the conductive elements 110 is reduced, and more area is provided to arrange the pixel structures PX, so as to improve the design flexibility of the pixel structures PX.

Fig. 5 is a schematic diagram of a layout (layout) of a crossing r2 of the third portion 112c of the second conductive element 112 and the second portion 111b of the first conductive element 111 according to an embodiment of the invention. Fig. 5 corresponds to the interlace r2 of fig. 1.

Referring to fig. 1 and 5, in the present embodiment, the first portion 111a of the first conductive element 111 and the first portion 112a of the second conductive element 112 are respectively disposed on the adjacent first walkways Rn, rn+1, and the third portion 112c of the second conductive element 112 spans the second portion 111b of the first conductive element 111.

Specifically, in the present embodiment, the third portion 112c of the second conductive element 112 includes a first sub-portion 112c-1 and a plurality of second sub-portions 112c-2 respectively connected to two ends of the first sub-portion 112c-1, wherein the second portion 111b of the first conductive element 111 spans the first sub-portion 112c-1 of the third portion 112c of the second conductive element 112, and a portion of the second portion 111b of the first conductive element 111 and the first sub-portion 112c-1 of the third portion 112c of the second conductive element 112 belong to different two conductive layers.

For example, in the present embodiment, an insulating layer (not shown) may be sandwiched between the first metal layer and the second metal layer, the first sub-portion 112c-1 of the third portion 112c of the second conductive element 112 may belong to the first metal layer, and the second sub-portion 112c-2 of the third portion 112c of the second conductive element 112 and a portion of the second portion 111b of the first conductive element 111 may belong to the second metal layer, but the invention is not limited thereto.

Referring to fig. 1, it is noted that, in the present embodiment, the third portion 112c of the second conductive element 112 spans the second portion 111b of the first conductive element 111; that is, in the top view of the pixel array substrate 10, a portion of the second portion 111b of the first conductive element 111 is disposed between the first portion 111a of the adjacent first conductive element 111 and the third portion 112c of the second conductive element 112. Therefore, the area between the pixel structures PX can be more effectively utilized, the overall arrangement range of the conductive elements 110 is reduced, and more area is provided to arrange the pixel structures PX, so as to improve the design flexibility of the pixel structures PX.

It should be noted that the following embodiments use the element numbers and part of the content of the foregoing embodiments, where the same numbers are used to denote the same or similar elements, and descriptions of the same technical content are omitted. Reference is made to the foregoing embodiments for an explanation of omitted parts, which will not be repeated.

The pixel array substrate 10A of fig. 6 is similar to the pixel array substrate 10 of fig. 1 described above, and the difference between them is that: the arrangement of the plurality of pixel structures PX of the pixel array substrate 10A of fig. 6 is slightly different from the arrangement of the plurality of pixel structures PX of the pixel array substrate 10 of fig. 1.

Referring to fig. 1, in the embodiment of fig. 1, each pixel structure PX may be separated from other pixel structures PX; that is, each first lane R of the pixel array substrate 10 may be an area between two adjacent pixel rows PXR, and each second lane C of the pixel array substrate 10 may be an area between two adjacent pixel columns (not shown).

Referring to fig. 6, in the embodiment of fig. 6, a plurality of pixel structures PX may be aggregated into a plurality of pixel groups GPX, each pixel group GPX includes a plurality of pixel structures PX arranged in a matrix of a·b, a and b are positive integers, and at least one of a and b is greater than 1; the first walkways R and the second walkways C are disposed outside the pixel groups GPX, and the first walkways R and the second walkways C are gaps between the pixel groups GPX. For example, in the present embodiment, a=b=2, i.e. each pixel group GPX may include a plurality of pixel structures PX arranged in a matrix of 2×2. However, the present invention is not limited thereto, and in other embodiments, a and b may be other positive integers other than 2, as long as at least one of a and b is greater than 1.

The pixel array substrate 10A of fig. 6 has similar technical effects and advantages as those of the pixel array substrate 10 of fig. 1, and will not be repeated here.

The pixel array substrate 10B of fig. 7 is similar to the pixel array substrate 10 of fig. 1 described above, and the difference between them is that: the plurality of conductive elements 110 of the pixel array substrate 10B of fig. 7 further includes a plurality of third conductive elements 113.

Referring to fig. 7, the pixel array substrate 10B includes a substrate 102, a plurality of pixel structures PX and a plurality of conductive elements 110. The plurality of pixel structures PX are arranged on the substrate 102 to define a plurality of first streets R and a plurality of second streets C between the plurality of pixel structures PX, wherein the plurality of first streets R are arranged in sequence in a first direction x, the plurality of second streets C are arranged in sequence in a second direction y, and the first direction x is staggered with the second direction y. The plurality of pixel structures PX are arranged in a plurality of pixel rows PXR. The plurality of pixel structures PX of each pixel row PXR are arranged in the second direction y. Each conductive element 110 is electrically connected to at least one pixel row PXR. Each conductive element 110 includes a first portion 110a disposed on a first aisle R and a second portion 110b disposed on a second aisle C. The plurality of conductive elements 110 include a plurality of first conductive elements 111 and a plurality of second conductive elements 112, and the plurality of first portions 111a of the plurality of first conductive elements 111 and the plurality of first portions 112a of the plurality of second conductive elements 112 are alternately arranged in the first direction x and are respectively disposed on the plurality of different first walkways R. The first portion 111a of the first conductive element 111 and the first portion 112a of the second conductive element 112 are respectively disposed on the nth first channel Rn and the (n+1) th first channel rn+1, the second portion 111b of the first conductive element 111 and the second portion 112b of the second conductive element 112 are respectively disposed on the (m) th second channel Cm and the (m+p) th second channel cm+1, and n, m and p are positive integers.

Unlike the embodiment of fig. 1, in the present embodiment, the plurality of conductive elements 110 further includes a plurality of third conductive elements 113, a plurality of first portions 111a of the plurality of first conductive elements 111, a plurality of first portions 112a of the plurality of second conductive elements 112, and a plurality of first portions 113a of the plurality of third conductive elements 113 are respectively disposed in a plurality of different first walkways R, and the first portion 112a of each second conductive element 112 is disposed between the first portion 111a of a corresponding first conductive element 111 and the first portion 113a of a corresponding third conductive element 113.

The first portion 111a of the first conductive element 111, the first portion 112a of the second conductive element 112, and the first portion 113a of the third conductive element 113 are respectively disposed on the nth first aisle Rn, the (n+1) th first aisle rn+1, and the (n+2) th first aisle rn+2. The second portion 111b of the first conductive element 111, the second portion 112b of the second conductive element 112, and the second portion 113b of the third conductive element 113 are respectively disposed in the mth second walkway Cm, the (m+p) th second walkway cm+1, and the (m+q) th second walkway cm+2, q being positive integers, and q > p.

For example, in the present embodiment, p=1, q=2; that is, the first portion 111a of the first conductive element 111, the first portion 112a of the second conductive element 112, and the first portion 113a of the third conductive element 113 are provided to the nth first lane Rn, the (n+1) th first lane rn+1, and the (n+2) th first lane rn+2, respectively, and the second portion 111b of the first conductive element 111, the second portion 112b of the second conductive element 112, and the second portion 113b of the third conductive element 113 are provided to the (m+2) th second lane Cm, the (m+1) th second lane cm+1, and the (m+2) th second lane cm+2, respectively. However, the present invention is not limited thereto, and in other embodiments, p and g may be other positive integers other than 1 and 2, so long as q > p.

The third portion 111c of the first conductive element 111, the third portion 112c of the second conductive element 112, and the third portion 113c of the third conductive element 113 are respectively disposed on the n-j first walkways Rn-2, the n-k first walkways Rn-1, and the n-l first walkways Rn, l being 0 or a positive integer, and j > k > l. For example, in the present embodiment, j may be selectively equal to 2, k may be selectively equal to 1, and l may be selectively equal to 0; that is, the third portion 111c of the first conductive element 111, the third portion 112c of the second conductive element 112, and the third portion 113c of the third conductive element 113 can be disposed on the n-2 th first aisle Rn-2, the n-1 st first aisle Rn-1, and the n-th first aisle Rn, respectively, but the invention is not limited thereto.

Fig. 8 is a schematic diagram of a layout (layout) of an intersection r3 of a first portion 112a of a second conductive element 112 and a second portion 113b of a third conductive element 113 according to an embodiment of the invention. Fig. 8 corresponds to the interlace r3 of fig. 7.

Referring to fig. 7 and 8, in the present embodiment, the first portion 112a of the second conductive element 112 and the first portion 113a of the third conductive element 113 are disposed on the adjacent first walkways rn+1, rn+2, and the first portion 112a of the second conductive element 112 spans the second portion 113b of the third conductive element 113.

Specifically, in the present embodiment, the first portion 112a of the second conductive element 112 includes a first sub-portion 112a-1 and a plurality of second sub-portions 112a-2 respectively connected to two ends of the first sub-portion 112a-1, wherein the first sub-portion 112a-1 of the first portion 112a of the second conductive element 112 spans a portion of the second portion 113b of the third conductive element 113, and a portion of the second portion 113b of the third conductive element 113 and the first sub-portion 112a-1 of the first portion 112a of the second conductive element 112 belong to different two conductive layers.

For example, in the present embodiment, an insulating layer (not shown) may be sandwiched between the first metal layer and the second metal layer, the first sub-portion 112a-1 of the first portion 112a of the second conductive element 112 may belong to the first metal layer, and the second sub-portion 112a-2 of the first portion 112a of the second conductive element 112 and a portion of the second portion 113b of the third conductive element 113 may belong to the second metal layer.

Fig. 9 is a schematic diagram of a layout (layout) of an intersection r1' of a third portion 113c of a third conductive element 113 and a second portion 112b of a second conductive element 112 according to an embodiment of the invention. Fig. 9 corresponds to the intersection r1' of fig. 7.

Referring to fig. 7 and 9, in the present embodiment, the first portion 112a of the second conductive element 112 and the first portion 113a of the third conductive element 113 are disposed on the adjacent first walkways rn+1, rn+2, and the third portion 113c of the third conductive element 113 spans the second portion 112b of the second conductive element 112.

Specifically, in the present embodiment, the third portion 113c of the third conductive element 113 includes a first sub-portion 113c-1 and a plurality of second sub-portions 113c-2 respectively connected to two ends of the first sub-portion 113c-1, wherein the first sub-portion 113c-1 of the third portion 113c of the third conductive element 113 spans the second portion 112b of the second conductive element 112, and the first sub-portion 113c-1 of the third portion 113c of the third conductive element 113 and the second portion 112b of the second conductive element 112 belong to different two conductive layers.

For example, in the present embodiment, an insulating layer (not shown) may be sandwiched between the first metal layer and the second metal layer, the first sub-portion 113c-1 of the third portion 113c of the third conductive element 113 may belong to the first metal layer, and the second sub-portion 113c-2 of the third portion 113c of the third conductive element 113 and a portion of the second portion 112b of the second conductive element 112 may belong to the second metal layer, but the invention is not limited thereto.

The pixel array substrate 10C of fig. 10 is similar to the pixel array substrate 10B of fig. 7 described above, and the difference between them is that: the arrangement of the plurality of pixel structures PX of the pixel array substrate 10C of fig. 10 is slightly different from the arrangement of the plurality of pixel structures PX of the pixel array substrate 10B of fig. 7.

Referring to fig. 7, in the embodiment of fig. 7, each pixel structure PX may be separated from other pixel structures PX; that is, each first lane R of the pixel array substrate 10B may be an area between two adjacent pixel rows PXR, and each second lane C of the pixel array substrate 10 may be an area between two adjacent pixel columns (not shown).

Referring to fig. 10, in the embodiment of fig. 10, a plurality of pixel structures PX may be aggregated into a plurality of pixel groups GPX, each pixel group GPX includes a plurality of pixel structures PX arranged in a matrix of a·b, a and b are positive integers, and at least one of a and b is greater than 1; the first walkways R and the second walkways C are disposed outside the pixel groups GPX, and the first walkways R and the second walkways C are gaps between the pixel groups GPX. For example, in the present embodiment, a=b=2, i.e. each pixel group GPX may include a plurality of pixel structures PX arranged in a matrix of 2×2. However, the present invention is not limited thereto, and in other embodiments, a and b may be other positive integers other than 2, as long as at least one of a and b is greater than 1.

Claims

1. A pixel array substrate, comprising:

a substrate;

the pixel structures are arranged on the substrate in an array manner to define a plurality of first walkways and a plurality of second walkways which are positioned between the pixel structures, wherein the first walkways are arranged in sequence in a first direction, the second walkways are arranged in sequence in a second direction, and the first direction and the second direction are staggered; and

the pixel structures are arranged in a plurality of pixel rows, the pixel structures of each pixel row are arranged in the second direction, each conductive element is electrically connected with at least one pixel row, and each conductive element comprises a first part arranged on a first pavement and a second part arranged on a second pavement;

the conductive elements comprise a plurality of first conductive elements and a plurality of second conductive elements, and a plurality of first parts of the first conductive elements and a plurality of first parts of the second conductive elements are alternately arranged in the first direction and are respectively arranged on different first walkways;

the first portion of the first conductive element and the first portion of the second conductive element are respectively disposed on the nth first channel and the (n+1) th first channel, the second portion of the first conductive element and the second portion of the second conductive element are respectively disposed on the (m) th second channel and the (m+p) th second channel, and n, m and p are positive integers.

2. The pixel array substrate of claim 1, wherein the first portion of the first conductive element spans the second portion of the second conductive element.

3. The pixel array substrate of claim 1, wherein each of said conductive elements further comprises a third portion disposed in another of said first lanes, said first portion of each of said conductive elements having a data input, said second portion of each of said conductive elements being electrically connected to said first portion of each of said conductive elements, and said third portion of each of said conductive elements being electrically connected to said second portion of each of said conductive elements and said at least one pixel column;

the third portion of the first conductive element and the third portion of the second conductive element are respectively disposed on the nth-jth first aisle and the nth-kth first aisle, j and k are positive integers, and j > k.

4. The pixel array substrate of claim 3, wherein the third portion of the second conductive element spans the second portion of the first conductive element.

5. The pixel array substrate of claim 1, wherein the plurality of conductive elements further comprises a plurality of third conductive elements, a plurality of first portions of the plurality of first conductive elements, a plurality of first portions of the plurality of second conductive elements, and a plurality of first portions of the plurality of third conductive elements are respectively disposed in different ones of the plurality of first lanes, and the first portion of each of the plurality of second conductive elements is disposed between the first portion of a corresponding one of the plurality of first conductive elements and the first portion of a corresponding one of the plurality of third conductive elements;

the first portion of the first conductive element, the first portion of the second conductive element, and the first portion of the third conductive element are respectively disposed on the nth first aisle, the (n+1) th first aisle, and the (n+2) th first aisle;

the second portion of the first conductive element, the second portion of the second conductive element, and the second portion of the third conductive element are disposed in an mth second aisle, an mth+p second aisle, and an mth+q second aisle, respectively, q being a positive integer, and q > p.

6. The pixel array substrate of claim 5, wherein the first portion of the second conductive element spans the second portion of the third conductive element.

7. The pixel array substrate of claim 5, wherein each of said conductive elements further comprises a third portion disposed in another of said first lanes, said first portion of each of said conductive elements having a data input, said second portion of each of said conductive elements being electrically connected to said first portion of each of said conductive elements, and said third portion of each of said conductive elements being electrically connected to said second portion of each of said conductive elements and said at least one pixel column;

the third portion of the first conductive element, the third portion of the second conductive element, and the third portion of the third conductive element are disposed in the nth-jth first aisle, the nth-kth first aisle, and the nth-l first aisle, respectively, j and k are positive integers, l is 0 or a positive integer, and j > k > l.

8. The pixel array substrate of claim 7, wherein the third portion of the third conductive element spans the second portion of the second conductive element.

9. The pixel array substrate of claim 1, further comprising:

the multiplexers are arranged between the pixel structures, and each multiplexer is electrically connected to a corresponding conductive element and at least one pixel column.

10. The pixel array substrate of claim 1, wherein the pixel structures comprise a plurality of pixel groups, each pixel group comprises a plurality of pixel structures arranged in a matrix of a-b, the first and second streets are disposed outside the pixel groups, the first and second streets are gaps between the pixel groups, a and b are positive integers, and at least one of a and b is greater than 1.