TWI742705B - Display apparatus - Google Patents
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- TWI742705B TWI742705B TW109118284A TW109118284A TWI742705B TW I742705 B TWI742705 B TW I742705B TW 109118284 A TW109118284 A TW 109118284A TW 109118284 A TW109118284 A TW 109118284A TW I742705 B TWI742705 B TW I742705B
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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Abstract
Description
本發明是有關於一種光電裝置,且特別是有關於一種顯示裝置。The present invention relates to an optoelectronic device, and particularly relates to a display device.
發光二極體顯示裝置包括主動元件基板及被轉置於主動元件基板上的多個發光二極體元件。繼承發光二極體的特性,發光二極體顯示裝置具有省電、高效率、高亮度及反應時間快等優點。此外,相較於有機發光二極體顯示裝置,發光二極體顯示裝置還具有色彩易調校、發光壽命長、無影像烙印等優勢。因此,發光二極體顯示裝置被視為下一世代的顯示技術。The light emitting diode display device includes an active device substrate and a plurality of light emitting diode devices transferred on the active device substrate. Inheriting the characteristics of light-emitting diodes, light-emitting diode display devices have the advantages of power saving, high efficiency, high brightness, and fast response time. In addition, compared with organic light-emitting diode display devices, light-emitting diode display devices also have advantages such as easy color adjustment, long light-emitting life, and no image burn-in. Therefore, light-emitting diode display devices are regarded as the next generation of display technology.
發光二極體顯示裝置的主動元件基板包括用以驅動發光二極體元件的多條資料線、多條掃描線及多個畫素驅動電路。資料線、掃描線及畫素驅動電路包括由多個導電層製作的多條線路,不同導電層的多條線路具有多個交叉處,導致發光二極體顯示面板的RC負載(RC loading)增加,線路斷線的機率也提升。此外,發光二極體顯示裝置所需的掃描線的數量眾多,需佔用相當的佈局面積,使得發光二極體顯示裝置的解析度不易提升。為提高發光二極體顯示裝置的解析度,可使用一解多工器與掃描線電性連接。在採用解多工器的情況下,輸入至解多工器的資料訊號需包括一重置訊號,進而使得畫素結構被畫素資料訊號寫入的時間不足,導致顯示畫面易異常。The active device substrate of the light emitting diode display device includes a plurality of data lines, a plurality of scanning lines and a plurality of pixel driving circuits for driving the light emitting diode device. The data lines, scan lines, and pixel drive circuits include multiple lines made of multiple conductive layers, and multiple lines of different conductive layers have multiple intersections, resulting in an increase in the RC loading of the light-emitting diode display panel , The probability of line disconnection is also increased. In addition, the number of scan lines required by the light-emitting diode display device is large, which requires a considerable layout area, so that the resolution of the light-emitting diode display device cannot be easily improved. In order to improve the resolution of the light emitting diode display device, a demultiplexer can be used to electrically connect the scan line. In the case of using the demultiplexer, the data signal input to the demultiplexer needs to include a reset signal, so that the time for the pixel structure to be written by the pixel data signal is insufficient, and the display screen is prone to abnormalities.
本發明提供一種顯示裝置,性能佳。The invention provides a display device with good performance.
本發明的一種顯示裝置,包括基板、多個導電結構、多個畫素結構、多條資料線以及多條掃描線。基板具有第一表面、第二表面和多個貫孔,其中第一表面相對於第二表面,且多個貫孔貫穿第一表面和第二表面。多個導電結構分別設置於多個貫孔中。多個畫素結構設置於基板的第一表面上,且沿第一方向排成一畫素列,其中每一畫素結構包括電晶體和電性連接至電晶體的發光元件。多條資料線設置於基板的第一表面上,在第一方向上排列,且電性連接至畫素列之多個畫素結構的多個電晶體。多條掃描線電性連接至畫素列之多個畫素結構的多個電晶體,其中畫素列的多個畫素結構包括第一畫素結構及第二畫素結構,多條掃描線包括第一掃描線及第二掃描線,第一掃描線及第二掃描線設置於基板的第二表面上且在第二方向上排列,第一掃描線及第二掃描線分別透過多個導電結構電性連接至第一畫素結構的電晶體及第二畫素結構的電晶體,且第一方向與第二方向交錯。A display device of the present invention includes a substrate, multiple conductive structures, multiple pixel structures, multiple data lines, and multiple scan lines. The substrate has a first surface, a second surface and a plurality of through holes, wherein the first surface is opposite to the second surface, and the plurality of through holes penetrate the first surface and the second surface. The plurality of conductive structures are respectively arranged in the plurality of through holes. A plurality of pixel structures are arranged on the first surface of the substrate and arranged in a pixel row along the first direction. Each pixel structure includes a transistor and a light-emitting element electrically connected to the transistor. A plurality of data lines are arranged on the first surface of the substrate, are arranged in a first direction, and are electrically connected to a plurality of transistors of a plurality of pixel structures in a pixel row. A plurality of scan lines are electrically connected to a plurality of transistors of a plurality of pixel structures of the pixel row, wherein the plurality of pixel structures of the pixel row include a first pixel structure and a second pixel structure, and a plurality of scan lines It includes a first scan line and a second scan line. The first scan line and the second scan line are arranged on the second surface of the substrate and are arranged in the second direction. The first scan line and the second scan line respectively pass through a plurality of conductive lines. The structure is electrically connected to the transistor of the first pixel structure and the transistor of the second pixel structure, and the first direction and the second direction are staggered.
在本發明的一實施例中,上述的每一畫素結構更包括電容,設置於基板的第一表面上,電性連接至畫素結構的電晶體,且具有第一電極、第二電極和位於第一電極與第二電極之間的絕緣層,其中畫素結構之電容的第一電極重疊於掃描線。In an embodiment of the present invention, each of the above-mentioned pixel structures further includes a capacitor, which is disposed on the first surface of the substrate, is electrically connected to the transistor of the pixel structure, and has a first electrode, a second electrode, and a transistor. An insulating layer located between the first electrode and the second electrode, wherein the first electrode of the capacitor of the pixel structure overlaps the scan line.
在本發明的一實施例中,上述的每一畫素結構更包括電容,設置於基板的第一表面上,電性連接至畫素結構的電晶體,且具有第一電極、第二電極和位於第一電極與第二電極之間的絕緣層,其中畫素結構之電容的第一電極於基板上的垂直投影環繞一貫孔。In an embodiment of the present invention, each of the above-mentioned pixel structures further includes a capacitor, which is disposed on the first surface of the substrate, is electrically connected to the transistor of the pixel structure, and has a first electrode, a second electrode, and a transistor. The insulating layer located between the first electrode and the second electrode, wherein the vertical projection of the first electrode of the pixel structure capacitor on the substrate surrounds a through hole.
在本發明的一實施例中,上述的每一畫素結構更包括電容,設置於基板的第一表面上,電性連接至畫素結構的電晶體,且具有第一電極、第二電極和位於第一電極與第二電極之間的絕緣層,其中畫素結構之電容的第一電極於基板上的垂直投影具有一缺口,而一貫孔位於缺口中。In an embodiment of the present invention, each of the above-mentioned pixel structures further includes a capacitor, which is disposed on the first surface of the substrate, is electrically connected to the transistor of the pixel structure, and has a first electrode, a second electrode, and a transistor. In the insulating layer located between the first electrode and the second electrode, the vertical projection of the first electrode of the pixel structure capacitor on the substrate has a gap, and a through hole is located in the gap.
在本發明的一實施例中,上述的第一掃描線的厚度大於資料線的厚度。In an embodiment of the present invention, the thickness of the aforementioned first scan line is greater than the thickness of the data line.
在本發明的一實施例中,上述的畫素列的多個畫素結構更包括第三畫素結構,多條掃描線更包括第三掃描線,第三掃描線設置於基板的第一表面上且電性連接至第三畫素結構的電晶體,而第一掃描線的線寬大於第三掃描線的線寬。In an embodiment of the present invention, the multiple pixel structures of the aforementioned pixel column further include a third pixel structure, the multiple scan lines further include a third scan line, and the third scan line is disposed on the first surface of the substrate And electrically connected to the transistor of the third pixel structure, and the line width of the first scan line is larger than the line width of the third scan line.
在本發明的一實施例中,上述的畫素列的多個畫素結構更包括第三畫素結構,多條掃描線更包括第三掃描線,第三掃描線設置於基板的第一表面上且電性連接至第三畫素結構的電晶體,第三畫素結構的發光元件發出紅光,且第一畫素結構的發光元件及第二畫素結構的發光元件發出藍光及綠光。In an embodiment of the present invention, the multiple pixel structures of the aforementioned pixel column further include a third pixel structure, the multiple scan lines further include a third scan line, and the third scan line is disposed on the first surface of the substrate And electrically connected to the transistor of the third pixel structure, the light emitting element of the third pixel structure emits red light, and the light emitting element of the first pixel structure and the light emitting element of the second pixel structure emit blue and green light .
在本發明的一實施例中,上述的每一畫素結構更包括電容,設置於基板的第一表面上,電性連接至畫素結構的電晶體,且具有第一電極、第二電極和位於第一電極與第二電極之間的絕緣層。畫素列的多個畫素結構更包括第三畫素結構,多條掃描線更包括第三掃描線,第三掃描線設置於基板的第一表面上且電性連接至第三畫素結構的電晶體,而第三畫素結構的電容大於第一畫素結構的電容。In an embodiment of the present invention, each of the above-mentioned pixel structures further includes a capacitor, which is disposed on the first surface of the substrate, is electrically connected to the transistor of the pixel structure, and has a first electrode, a second electrode, and a transistor. An insulating layer located between the first electrode and the second electrode. The plurality of pixel structures of the pixel column further include a third pixel structure, and the plurality of scan lines further include a third scan line. The third scan line is disposed on the first surface of the substrate and is electrically connected to the third pixel structure The capacitance of the third pixel structure is greater than that of the first pixel structure.
在本發明的一實施例中,上述的每一畫素結構更包括電容,設置於基板的第一表面上,電性連接至畫素結構的電晶體,且具有第一電極、第二電極和位於第一電極與第二電極之間的絕緣層。畫素列的多個畫素結構更包括第三畫素結構,多條掃描線更包括第三掃描線,第三掃描線設置於基板的第一表面上且電性連接至第三畫素結構的電晶體,而第三畫素結構之電容的第一電極的面積大於第一畫素結構之電容的第一電極的面積。In an embodiment of the present invention, each of the above-mentioned pixel structures further includes a capacitor, which is disposed on the first surface of the substrate, is electrically connected to the transistor of the pixel structure, and has a first electrode, a second electrode, and a transistor. An insulating layer located between the first electrode and the second electrode. The plurality of pixel structures in the pixel column further includes a third pixel structure, and the plurality of scan lines further include a third scan line. The third scan line is disposed on the first surface of the substrate and is electrically connected to the third pixel structure The area of the first electrode of the capacitor of the third pixel structure is larger than the area of the first electrode of the capacitor of the first pixel structure.
在本發明的一實施例中,上述的第三畫素結構的發光元件發出紅光,且第一畫素結構的發光元件及第二畫素結構的發光元發出藍光及綠光。In an embodiment of the present invention, the light-emitting element of the third pixel structure described above emits red light, and the light-emitting element of the first pixel structure and the light-emitting element of the second pixel structure emit blue and green light.
現將詳細地參考本發明的示範性實施例,示範性實施例的實例說明於附圖中。只要有可能,相同元件符號在圖式和描述中用來表示相同或相似部分。Reference will now be made in detail to the exemplary embodiments of the present invention, and examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and descriptions to indicate the same or similar parts.
應當理解,當諸如層、膜、區域或基板的元件被稱為在另一元件“上”或“連接到”另一元件時,其可以直接在另一元件上或與另一元件連接,或者中間元件可以也存在。相反,當元件被稱為“直接在另一元件上”或“直接連接到”另一元件時,不存在中間元件。如本文所使用的,“連接”可以指物理及/或電性連接。再者,“電性連接”或“耦合”可以是二元件間存在其它元件。It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connected" can refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that there are other elements between two elements.
本文使用的“約”、“近似”、或“實質上”包括所述值和在本領域普通技術人員確定的特定值的可接受的偏差範圍內的平均值,考慮到所討論的測量和與測量相關的誤差的特定數量(即,測量系統的限制)。例如,“約”可以表示在所述值的一個或多個標準偏差內,或±30%、±20%、±10%、±5%內。再者,本文使用的“約”、“近似”或“實質上”可依光學性質、蝕刻性質或其它性質,來選擇較可接受的偏差範圍或標準偏差,而可不用一個標準偏差適用全部性質。As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within the acceptable deviation range of the specific value determined by a person of ordinary skill in the art, taking into account the measurement in question and the The specific amount of measurement-related error (ie, the limitation of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "about", "approximately" or "substantially" as used herein can be based on optical properties, etching properties or other properties to select a more acceptable range of deviation or standard deviation, and not one standard deviation can be applied to all properties .
除非另有定義,本文使用的所有術語(包括技術和科學術語)具有與本發明所屬領域的普通技術人員通常理解的相同的含義。將進一步理解的是,諸如在通常使用的字典中定義的那些術語應當被解釋為具有與它們在相關技術和本發明的上下文中的含義一致的含義,並且將不被解釋為理想化的或過度正式的意義,除非本文中明確地這樣定義。Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of related technologies and the present invention, and will not be interpreted as idealized or excessive The formal meaning, unless explicitly defined as such in this article.
圖1為本發明一實施例之顯示裝置10的立體示意圖。FIG. 1 is a three-dimensional schematic diagram of a
圖2為本發明一實施例之顯示裝置10的剖面示意圖。2 is a schematic cross-sectional view of a
圖3為本發明一實施例之畫素結構SPX的等效電路示意圖。FIG. 3 is a schematic diagram of an equivalent circuit of a pixel structure SPX according to an embodiment of the present invention.
圖4為本發明一實施例之顯示裝置10之佈局(layout)的透視示意圖。FIG. 4 is a perspective schematic diagram of the layout of the
圖3省略圖4的電容C。Fig. 3 omits the capacitor C of Fig. 4.
圖5為根據圖4的剖線A-A’所繪之本發明一實施例之顯示裝置10的剖面示意圖。FIG. 5 is a schematic cross-sectional view of the
圖6為根據圖4的剖線B-B’所繪之本發明一實施例之顯示裝置10的剖面示意圖。6 is a schematic cross-sectional view of the
請參照圖1,顯示裝置10包括基板110,具有相對的第一表面110a及第二表面110b。第一表面110a也可稱為基板110的正面。第二表面110b也可稱為基板110的背面。舉例而言,在本實施例中,基板110的材質可以是玻璃、石英、有機聚合物、不透光/反射材料(例如:晶圓、陶瓷、或其它可適用的材料)、或是其它可適用的材料。1, the
請參照圖1、圖2及圖4,多個畫素結構SPX設置於基板110的第一表面110a上,且沿第一方向x排成一畫素列R。Referring to FIGS. 1, 2 and 4, a plurality of pixel structures SPX are disposed on the
請參照圖3及圖4,每一畫素結構SPX包括一發光元件LED和用以驅動發光元件LED的畫素驅動電路DVC。畫素驅動電路DVC包括電晶體T1,電性連接至發光元件LED。舉例而言,在本實施例中,發光元件LED可以是被轉置於基板110之第一表面110a上的微型發光二極體元件(μLED)。然而,本發明不限於此,在其它實施例中,發光元件LED也可以是有機發光二極體或其它種類的發光元件。3 and 4, each pixel structure SPX includes a light-emitting element LED and a pixel driving circuit DVC for driving the light-emitting element LED. The pixel driving circuit DVC includes a transistor T1, which is electrically connected to the light-emitting element LED. For example, in this embodiment, the light emitting element LED may be a micro light emitting diode element (μLED) that is transferred to the
在本實施例中,畫素驅動電路DVC除了包括電晶體T1還可包括電晶體T2及電容C1,其中電晶體T1的第一端T1a電性連接至對應的一資料線DL,電晶體T1的控制端T1c電性連接至對應的一掃描線SL,電晶體T1的第二端T1b電性連接至電晶體T2的控制端T2c,電容C1電性連接於電晶體T1的第二端T1b及電晶體T2的第一端T2a,電晶體T2的第一端T2a電性連接至具有一電源電位VDD的電源線(未繪示),電晶體T2的第二端T2b電性連接至發光元件LED的第一電極(未繪示),發光元件LED的第二電極(未繪示)電性連接至具有參考電位VSS的共通線(未繪示)。In this embodiment, in addition to the transistor T1, the pixel driving circuit DVC may also include a transistor T2 and a capacitor C1. The first terminal T1a of the transistor T1 is electrically connected to a corresponding data line DL. The control terminal T1c is electrically connected to a corresponding scan line SL, the second terminal T1b of the transistor T1 is electrically connected to the control terminal T2c of the transistor T2, and the capacitor C1 is electrically connected to the second terminal T1b of the transistor T1 and The first end T2a of the transistor T2, the first end T2a of the transistor T2 is electrically connected to a power line (not shown) having a power supply potential VDD, and the second end T2b of the transistor T2 is electrically connected to the light emitting element LED The first electrode (not shown) and the second electrode (not shown) of the light-emitting element LED are electrically connected to a common line (not shown) with a reference potential VSS.
簡言之,在本實施例中,畫素驅動電路DVC可包括二個電晶體及一個電容(2T1C)。然而,本發明不限於此,畫素驅動電路DVC還可以包括其它電晶體及/或其它電容,而形成其它架構,例如但不限於:三個電晶體及一個電容(3T1C)、三個電晶體及二個電容(3T2C)、四個電晶體及一個電容(4T1C)、四個電晶體及二個電容(4T2C)、五個電晶體及一個電容(5T1C)、五個電晶體及二個電容(5T2C)、六個電晶體及二個電容(6T2C)、七個電晶體及一個電容(7T1C)等架構。In short, in this embodiment, the pixel driving circuit DVC may include two transistors and one capacitor (2T1C). However, the present invention is not limited to this. The pixel driving circuit DVC may also include other transistors and/or other capacitors to form other structures, such as but not limited to: three transistors and one capacitor (3T1C), three transistors And two capacitors (3T2C), four transistors and one capacitor (4T1C), four transistors and two capacitors (4T2C), five transistors and one capacitor (5T1C), five transistors and two capacitors (5T2C), six transistors and two capacitors (6T2C), seven transistors and one capacitor (7T1C) and other structures.
請參照圖3及圖4,顯示裝置10還包括多條資料線DL,設置於基板110的第一表面110a上,在第一方向x上排列,且電性連接至畫素列R之多個畫素結構SPX的多個電晶體T1。3 and 4, the
舉例而言,在本實施例中,畫素列R的多個畫素結構SPX包括在第一方向x上依序排列的第一畫素結構SPX1、第二畫素結構SPX2及第三畫素結構SPX3,且第一畫素結構SPX1的電晶體T1、第二畫素結構SPX2的電晶體T1及第三畫素結構SPX3的電晶體T1可分別電性連接至多條資料線DL,但本發明不以此為限。For example, in this embodiment, the plurality of pixel structures SPX of the pixel row R includes a first pixel structure SPX1, a second pixel structure SPX2, and a third pixel structure sequentially arranged in the first direction x Structure SPX3, and the transistor T1 of the first pixel structure SPX1, the transistor T1 of the second pixel structure SPX2, and the transistor T1 of the third pixel structure SPX3 can be electrically connected to a plurality of data lines DL, but the present invention Not limited to this.
請參照圖3及圖4,顯示裝置10還包括多條掃描線SL,電性連接至畫素列R之多個畫素結構SPX的多個電晶體T1。請參照圖1、圖2及圖4,基板110具有貫穿第一表面110a和第二表面110b的多個貫孔112。顯示裝置10還包括多個導電結構112s,分別設置於多個貫孔112中。畫素列R的多個畫素結構SPX包括第一畫素結構SPX1及第二畫素結構SPX2。多條掃描線SL包括第一掃描線SL1及第二掃描線SL2。第一掃描線SL1及第二掃描線SL2設置於基板110的第二表面110b上,且在第二方向y上排列,其中第一方向x與第二方向y交錯。位於第二表面110b上的第一掃描線SL1及第二掃描線SL2是分別透過位於多個貫孔112中的多個導電結構112s分別電性連接至位於第一表面110a上之第一畫素結構SPX1的電晶體T1及第二畫素結構SPX2的電晶體T1。Referring to FIGS. 3 and 4, the
請參照圖4,畫素列R的多個畫素結構SPX還包括第三畫素結構SPX3。在本實施例中,第一畫素結構SPX1的發光元件LED、第二畫素結構SPX2的發光元件LED及第三畫素結構SPX3的發光元件LED可分別用以發出不同的第一色光、第二色光及第三色光,而第一畫素結構SPX1、第二畫素結構SPX2及第三畫素結構SPX3可組成一畫素單元PX。在本實施例中,第一色光、第二色光及第三色光例如是藍光、綠光及紅光,但本發明不以此為限。多條掃描線SL還包括電性連接至第三畫素結構SPX3的第三掃描線SL3。在本實施例中,第三掃描線SL3也可設置於基板110的第二表面110b上,且透過位於貫孔112中的導電結構112s電性連接至位於第一表面110a上之第三畫素結構SPX3的電晶體T1。Referring to FIG. 4, the multiple pixel structures SPX of the pixel column R further include a third pixel structure SPX3. In this embodiment, the light-emitting element LED of the first pixel structure SPX1, the light-emitting element LED of the second pixel structure SPX2, and the light-emitting element LED of the third pixel structure SPX3 can be used to emit different first color lights, respectively. The second color light and the third color light, and the first pixel structure SPX1, the second pixel structure SPX2, and the third pixel structure SPX3 can form a pixel unit PX. In this embodiment, the first color light, the second color light, and the third color light are, for example, blue light, green light, and red light, but the invention is not limited thereto. The plurality of scan lines SL further includes a third scan line SL3 electrically connected to the third pixel structure SPX3. In this embodiment, the third scan line SL3 can also be disposed on the
簡言之,在本實施例中,所有的掃描線SL可選擇性地皆設置於基板110的第二表面110b上。然而,本發明不限於此,在其它實施例中,也可以是,部分的掃描線SL設置於基板110的第一表面110a上,而另一部分的掃描線SL設置於基板110的第二表面110b上,將於後續段落配合其它圖式舉例說明之。In short, in this embodiment, all the scan lines SL can be selectively disposed on the
請參照圖1、圖2及圖4,在本實施例中,顯示裝置10還可包括電性連接至多條掃描線SL的閘極驅動電路GOA。在本實施例中,閘極驅動電路GOA的至少部分構件可與畫素結構SPX的電晶體T1一起製作。也就是說,在本實施例中,閘極驅動電路GOA可以是整合型閘極驅動電路(Gate Driver on Array),且與畫素結構SPX的電晶體T1皆設置於基板110的第一表面110a上。請參照圖1及圖2,基板110還具有貫孔114,顯示裝置10還可包括設置於貫孔114中的導電結構114s,位於基板110之第一表面110a上的閘極驅動電路GOA可透過位於貫孔114中的導電結構114s電性連接至位於基板110之第二表面110b上的掃描線SL。Referring to FIGS. 1, 2 and 4, in this embodiment, the
請參照圖4及圖5,在本實施例中,設置於基板110之第二表面110b上的第一掃描線SL1、第二掃描線SL2及第三掃描線SL3和設置於基板110之貫孔112、114中的導電結構112s、114s可使用電鍍方法形成,而設置於基板110之第一表面110a上的畫素結構SPX及資料線DL可使用微影技術形成。因此,在本實施例中,第一掃描線SL1的線寬W11、第二掃描線SL2的線寬W12及第三掃描線SL3的線寬W13會遠大於資料線DL的線寬W2;第一掃描線SL1的厚度T11、第二掃描線SL2的厚度T12及第三掃描線SL3的厚度T13會遠大於資料線DL的厚度T2。4 and 5, in this embodiment, the first scan line SL1, the second scan line SL2, and the third scan line SL3 provided on the
在本實施例中,基於導電性的考量,掃描線SL、資料線DL及導電結構112s、114s一般是使用金屬材料,例如:銅、鈦、鋁、鉬、銀等。但本發明不限於此,根據其他實施例,掃描線SL、資料線DL及導電結構112s、114s也可以使用其他導電材料。In this embodiment, based on the consideration of conductivity, the scan line SL, the data line DL, and the
請參照圖4,在本實施例中,每一畫素結構SPX更包括電容C。畫素結構SPX的電容C電性連接至畫素結構SPX的電晶體T1。在圖4中,是以電容C電性連接至電晶體T1的第一端T1a為示例。然而,本發明不以此為限,在其它實施例中,電容C也可以其它方式與電晶體T1電性連接。Please refer to FIG. 4, in this embodiment, each pixel structure SPX further includes a capacitor C. The capacitor C of the pixel structure SPX is electrically connected to the transistor T1 of the pixel structure SPX. In FIG. 4, the capacitor C is electrically connected to the first terminal T1a of the transistor T1 as an example. However, the present invention is not limited to this. In other embodiments, the capacitor C can also be electrically connected to the transistor T1 in other ways.
請參照圖4及圖6,電容C設置於基板110的第一表面110a上,且具有第一電極121、第二電極122和位於第一電極121與第二電極122之間的絕緣層123。在本實施例中,電晶體T1具有一半導體圖案T1d,電容C的其中一電極(例如:第二電極122)可與半導體圖案T1d於同一道製程中製作,而電容C的其中一電極(例如:第二電極122)的材質與半導體圖案T1d的材質可相同,但本發明不以此為限。4 and 6, the capacitor C is disposed on the
請參照圖4,值得注意的是,在本實施例中,每一畫素結構SPX之電容C的第一電極121重疊於一掃描線SL。4, it is worth noting that in this embodiment, the
舉例而言,在本實施例中,畫素列R的第一畫素結構SPX1、第二畫素結構SPX2及第三畫素結構SPX3沿第一方向x依序排列於基板110的第一表面110a上,第一畫素結構SPX1的電晶體T1、第二畫素結構SPX2的電晶體T1及第三畫素結構SPX3的電晶體T1分別電性連接至設置於第二表面110b上的第一掃描線SL1、第二掃描線SL2及第三掃描線SL3,第二掃描線SL2、第一掃描線SL1及第三掃描線SL3沿第二方向y依序排列,其中第一畫素結構SPX1之電容C的第一電極121可重疊於第一掃描線SL1的一彎曲部SL1a,第二畫素結構SPX2之電容C的第一電極121可重疊於第二掃描線SL2的一分支部SL2a,且第三畫素結構SPX3之電容C的第一電極121可重疊於第一掃描線SL1的另一彎曲部SL1b。For example, in this embodiment, the first pixel structure SPX1, the second pixel structure SPX2, and the third pixel structure SPX3 of the pixel row R are sequentially arranged on the first surface of the
在本實施例中,每一畫素結構SPX之電容C的第一電極121於基板110上的垂直投影環繞一貫孔112。藉此,畫素結構SPX能更有效率地利用第一表面110a的佈局面積,進而提升顯示裝置10的解析度。在本實施例中,電容C之第一電極121於基板110上的垂直投影可部分地環繞一貫孔112;也就是說,電容C的第一電極121於基板110上的垂直投影可具有開放式的缺口121a,而貫孔112位於缺口121a中。然而,本發明不以此為限,在其它實施例中,電容C之第一電極121於基板110上的垂直投影也可完全地環繞一貫孔112;也就是說,電容C的第一電極121於基板110上的垂直投影也可具有封閉式的一鏤空處,而貫孔112可位於所述鏤空處內。In this embodiment, the vertical projection of the
在此必須說明的是,下述實施例沿用前述實施例的元件標號與部分內容,其中採用相同的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,下述實施例不再重述。It must be noted here that the following embodiments use the element numbers and part of the content of the foregoing embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.
圖7為本發明一實施例之顯示裝置10A之佈局(layout)的透視示意圖。圖7的顯示裝置10A與圖4的顯示裝置10類似,兩者的差異在於:圖7之第三掃描線SL3與圖4之第三掃描線SL3不同;圖7之第三畫素結構SPX3的電容C與圖4之第三畫素結構SPX3的電容C不同。FIG. 7 is a perspective schematic diagram of the layout of the
請參照圖7,在本實施例中,部分的掃描線SL設置於基板110的第一表面110a上,而另一部分的掃描線SL設置於基板110的第二表面110b上。Referring to FIG. 7, in this embodiment, part of the scan line SL is disposed on the
舉例而言,在本實施例中,一畫素列R的多個畫素結構SPX包括在第一方向x上依序排列的第一畫素結構SPX1、第二畫素結構SPX2及第三畫素結構SPX3,第一畫素結構SPX1的電晶體T1及第二畫素結構SPX2的電晶體T1及第三畫素結構SPX3的電晶體T1分別電性連接至第一掃描線SL1、第二掃描線SL2及第三掃描線SL3。與圖4之實施例不同的是,在本實施例中,第一掃描線SL1及第二掃描線SL2設置於基板110的第二表面110b上(可參考圖2),但第三掃描線SL3是設置於基板110的第一表面110a上。For example, in this embodiment, a plurality of pixel structures SPX of a pixel row R includes a first pixel structure SPX1, a second pixel structure SPX2, and a third pixel structure sequentially arranged in the first direction x. The pixel structure SPX3, the transistor T1 of the first pixel structure SPX1, the transistor T1 of the second pixel structure SPX2, and the transistor T1 of the third pixel structure SPX3 are electrically connected to the first scan line SL1 and the second scan respectively Line SL2 and the third scan line SL3. The difference from the embodiment in FIG. 4 is that in this embodiment, the first scan line SL1 and the second scan line SL2 are disposed on the
類似地,在本實施例中,設置於基板110之第二表面110b上的構件(例如:第一掃描線SL1及第二掃描線SL2)是使用電鍍方法形成,而設置於基板110之第一表面110a上的構件(例如:第三掃描線SL3)是利用微影技術形成。因此,第一掃描線SL1的線寬W11及第二掃描線SL2的線寬W12會遠大於第三掃描線SL3的線寬W13。在本實施例中,與線寬W13較小之第三掃描線SL3電性連接之第三畫素結構SPX3的發光元件LED(可參考圖3)發出紅光,而與線寬W11、W12較大之第一掃描線SL1及第二掃描線SL2電性連接之第一畫素結構SPX1的發光元件LED及第二畫素結構SPX2的發光元件LED發出藍光及綠光。Similarly, in this embodiment, the components (for example, the first scan line SL1 and the second scan line SL2) disposed on the
此外,在本實施例中,用以發出紅光之第三畫素結構SPX3的電容C大於用以發出藍光及綠光之第一畫素結構SPX1的電容C及第二畫素結構SPX2的電容C。In addition, in this embodiment, the capacitance C of the third pixel structure SPX3 for emitting red light is greater than the capacitance C of the first pixel structure SPX1 and the second pixel structure SPX2 for emitting blue and green light. C.
舉例而言,在本實施例中,為使第三畫素結構SPX3的電容C大於第一畫素結構SPX1的電容C及第二畫素結構SPX2的電容C,可令第三畫素結構SPX3之電容C的第一電極121的面積大於第一畫素結構SPX1之電容C的第一電極121的面積及第二畫素結構SPX2之電容C的第一電極121的面積,及/或第三畫素結構SPX3之電容C的第二電極122的面積大於第一畫素結構SPX1之電容C的第二電極122的面積及第二畫素結構SPX2之電容C的第二電極122的面積。然而,本發明不限於此,在其它實施例中,也可使用其它方式,使第三畫素結構SPX3的電容C大於第一畫素結構SPX1的電容C及第二畫素結構SPX2的電容C。For example, in this embodiment, in order to make the capacitance C of the third pixel structure SPX3 larger than the capacitance C of the first pixel structure SPX1 and the capacitance C of the second pixel structure SPX2, the third pixel structure SPX3 can be made The area of the
用以發出不同色光之第一畫素結構SPX1的發光元件LED、第二畫素結構SPX2的發光元件LED及第三畫素結構SPX3的發光元件LED的發光效率不同,所需的驅動電流也不同,利用大小不儘相同之電容C來搭配第一畫素結構SPX1的發光元件LED、第二畫素結構SPX2的發光元件LED及第三畫素結構SPX3的發光元件LED,可使顯示裝置10A具有良好的電性及光學表現。The light-emitting element LED of the first pixel structure SPX1, the light-emitting element LED of the second pixel structure SPX2, and the light-emitting element LED of the third pixel structure SPX3 that emit different colors of light have different luminous efficiency and different driving currents. , Using capacitors C of different sizes to match the light-emitting element LED of the first pixel structure SPX1, the light-emitting element LED of the second pixel structure SPX2, and the light-emitting element LED of the third pixel structure SPX3, the
圖8為本發明一實施例之顯示裝置10B之佈局(layout)的透視示意圖。圖8的顯示裝置10B與圖4的顯示裝置10類似,兩者的差異在於:圖8之資料線DL與畫素結構SPX的電性連接方式與圖4之資料線DL與畫素結構SPX的電性連接方式不同。FIG. 8 is a perspective schematic diagram of the layout of the
請參照圖8,具體而言,在本實施例中,相鄰兩畫素結構SPX可與同一條資料線DL電性連接。藉此,能減少資料線DL的數量,節省設置資料線DL所需的佈局面積,而更進一步地提升顯示裝置10B的解析度。此外,還能減少資料驅動晶片與多條資料線DL電性連接的接腳數目,降低顯示裝置10B所需之資料驅動晶片的購入成本。Please refer to FIG. 8. Specifically, in this embodiment, two adjacent pixel structures SPX can be electrically connected to the same data line DL. Thereby, the number of data lines DL can be reduced, the layout area required for setting the data lines DL can be saved, and the resolution of the
綜上所述,在本發明一實施例中,至少部分的掃描線設置於基板的第二表面,且設置於基板之第二表面的掃描線可利用位於基板之貫孔中的導電結構電性連接至設置於基板之第一表面上的畫素結構。至少部分的掃描線可無需佔用基板之第一表面的佈局面積,而第一表面可有更大的佈局面積供畫素驅動電路的電容設置。藉此,設置於基板之第一表面上的畫素驅動電路的電容能設計得較大,而使顯示裝置整體的驅動電路更為穩定。To sum up, in an embodiment of the present invention, at least part of the scan lines are provided on the second surface of the substrate, and the scan lines provided on the second surface of the substrate can be electrically conductive structures located in the through holes of the substrate. Connected to the pixel structure arranged on the first surface of the substrate. At least part of the scan lines may not need to occupy the layout area of the first surface of the substrate, and the first surface may have a larger layout area for the capacitance setting of the pixel driving circuit. In this way, the capacitance of the pixel driving circuit provided on the first surface of the substrate can be designed to be larger, so that the overall driving circuit of the display device is more stable.
此外,由於至少部分的掃描線設置於基板的第二表面,因此,至少部分的掃描線和與其交叉之多條資料線之間的距離大,至少部分的掃描線和與其交叉之多條資料線之間的雜散電容小,而有助降低顯示裝置的RC負載(RC loading),穩定顯示裝置整體的驅動電路。In addition, since at least part of the scan lines are disposed on the second surface of the substrate, the distance between at least part of the scan lines and the data lines crossing it is large, and the distance between at least part of the scan lines and the data lines crossing it is large. The stray capacitance between them is small, which helps to reduce the RC load of the display device (RC loading) and stabilize the overall driving circuit of the display device.
更重要的是,在本發明一實施例中,由於至少部分的掃描線是設置於面積充分之基板的第二表面,因此,同一畫素列之畫素單元的第一畫素結構、第二畫素結構及第三畫素結構可分別與第一掃描線、第二掃描線及第三掃描線電性連接。藉此,利用解多工器驅動顯示裝置時,輸入至解多工器的資料訊號不需包括一重置訊號。藉此,能增加每一畫素結構被畫素資料訊號寫入的時間,進而提升顯示裝置的電性及其光學表現。More importantly, in an embodiment of the present invention, since at least part of the scan lines are provided on the second surface of the substrate with sufficient area, the first pixel structure and the second pixel structure of the pixel unit in the same pixel column The pixel structure and the third pixel structure can be electrically connected to the first scan line, the second scan line, and the third scan line, respectively. Therefore, when the display device is driven by the demultiplexer, the data signal input to the demultiplexer does not need to include a reset signal. Thereby, the time for each pixel structure to be written by the pixel data signal can be increased, thereby improving the electrical properties and optical performance of the display device.
10、10A、10B:顯示裝置
110:基板
110a:第一表面
110b:第二表面
112、114:貫孔
112s、114s:導電結構
121:第一電極
121a:缺口
122:第二電極
123:絕緣層
A-A’、B-B’:剖線
C:電容
DVC:畫素驅動電路
DL:資料線
GOA:閘極驅動電路
LED:發光元件
PX:畫素單元
R:畫素列
SPX:畫素結構
SPX1:第一畫素結構
SPX2:第二畫素結構
SPX3:第三畫素結構
SL:掃描線
SL1:第一掃描線
SL1a、SL1b:彎曲部
SL2:第二掃描線
SL2a:分支部
SL3:第三掃描線
T1、T2、T3、T4、T6:電晶體
T1a、T2a:第一端
T1b、T2b:第二端
T1c、T2c:控制端
T1d:半導體圖案
T11、T12、T13、T2:厚度
VDD:電源電位
VSS:參考電位
W11、W12、W13、W2:線寬
x:第一方向
y:第二方向10, 10A, 10B: display device
110:
圖1為本發明一實施例之顯示裝置10的立體示意圖。
圖2為本發明一實施例之顯示裝置10的剖面示意圖。
圖3為本發明一實施例之畫素結構SPX的等效電路示意圖。
圖4為本發明一實施例之顯示裝置10之佈局(layout)的透視示意圖。
圖5為根據圖4的剖線A-A’所繪之本發明一實施例之顯示裝置10的剖面示意圖。
圖6為根據圖4的剖線B-B’所繪之本發明一實施例之顯示裝置10的剖面示意圖。
圖7為本發明一實施例之顯示裝置10A之佈局(layout)的透視示意圖。
圖8為本發明一實施例之顯示裝置10B之佈局(layout)的透視示意圖。FIG. 1 is a three-dimensional schematic diagram of a
10:顯示裝置10: Display device
110:基板110: substrate
110a:第一表面110a: first surface
112:貫孔112: Through hole
121:第一電極121: first electrode
121a:缺口121a: gap
122:第二電極122: second electrode
A-A’、B-B’:剖線A-A’, B-B’: cut line
C:電容C: Capacitance
DL:資料線DL: Data line
PX:畫素單元PX: pixel unit
R:畫素列R: pixel column
SPX:畫素結構SPX: Pixel structure
SPX1:第一畫素結構SPX1: The first pixel structure
SPX2:第二畫素結構SPX2: second pixel structure
SPX3:第三畫素結構SPX3: third pixel structure
SL:掃描線SL: scan line
SL1:第一掃描線SL1: the first scan line
SL1a、SL1b:彎曲部SL1a, SL1b: curved part
SL2:第二掃描線SL2: second scan line
SL2a:分支部SL2a: Branch
SL3:第三掃描線SL3: Third scan line
T1:電晶體T1: Transistor
T1a:第一端T1a: first end
T1b:第二端T1b: second end
T1c:控制端T1c: Control terminal
T1d:半導體圖案T1d: semiconductor pattern
W11、W12、W13、W2:線寬W11, W12, W13, W2: line width
x:第一方向x: first direction
y:第二方向y: second direction
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TW202127420A (en) | 2021-07-16 |
TW202127654A (en) | 2021-07-16 |
TW202127655A (en) | 2021-07-16 |
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TWI730855B (en) | 2021-06-11 |
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TWI729856B (en) | 2021-06-01 |
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TWI745025B (en) | 2021-11-01 |
TWI732551B (en) | 2021-07-01 |
TWI722908B (en) | 2021-03-21 |
TWI747433B (en) | 2021-11-21 |
TW202127114A (en) | 2021-07-16 |
TWI735241B (en) | 2021-08-01 |
TW202127119A (en) | 2021-07-16 |
TW202127403A (en) | 2021-07-16 |
TW202127699A (en) | 2021-07-16 |
TWI734558B (en) | 2021-07-21 |
TW202127412A (en) | 2021-07-16 |
TWI742744B (en) | 2021-10-11 |
TWI728822B (en) | 2021-05-21 |
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