CN114361187A - Display substrate and display device - Google Patents

Abstract

The disclosure provides a display substrate and a display device, and belongs to the technical field of display. The display substrate comprises a plurality of test circuit groups, each test circuit group comprises a plurality of test circuits, each test circuit is respectively coupled with a data signal line and a data line lead, the data line lead is coupled with a data line, and the data line is coupled with a pixel. Each test circuit can transmit a data signal supplied from the data signal line to the data line through the data line lead to light the pixel. Because the resistance value of the conductive film layer coupled with the data line lead in each test circuit is inversely related to the length of the data line lead, the effective compensation of the resistance values of the data line leads with different lengths can be realized, and the resistance values on the data line leads are close to each other. Furthermore, the uniformity of the data signals transmitted to the data lines is better, and the uniformity of the light emitting brightness of the pixels is better. Therefore, the lighting test can be ensured to have better precision.

Description

Display substrate and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display substrate and a display device.

Background

An organic light-emitting diode (OLED) display substrate is widely used in various display devices due to its advantages of low power consumption, fast response speed, wide viewing angle, and the like.

At present, in order to ensure that the factory yield of the OLED display substrate is good, before the OLED display substrate is shipped, a lighting test is performed on a plurality of pixels in the OLED display substrate to verify whether the plurality of pixels can normally emit light. In this regard, a panel test (CT) circuit is generally disposed in the OLED display substrate, and the CT circuit is coupled to a plurality of data lines through a plurality of data line leads, and the plurality of data lines are coupled to a plurality of pixels. The CT circuit is used for transmitting data signals to a plurality of data lines through a plurality of data line lead wires, and the plurality of data lines are used for further transmitting the received data signals to a plurality of pixels so as to light the plurality of pixels.

However, due to the arrangement, the lengths of the data line leads are different, i.e., the resistance values of the data line leads are different. Therefore, the uniformity of the data signals transmitted to each data line is poor, and the uniformity of the luminance of the plurality of pixels is poor, which affects the testing accuracy of the lighting test.

Disclosure of Invention

The embodiment of the disclosure provides a display substrate and a display device, which can solve the problem that the test precision of a lighting test is influenced due to the difference of resistance values on leads of various data lines in the related art.

The technical scheme is as follows:

in one aspect, a display substrate is provided, the display substrate including:

a substrate having a display area and a non-display area at least partially surrounding the display area;

a plurality of pixels located in the display area;

a plurality of data lines located in the display region and coupled to the plurality of pixels, and configured to provide data signals to the plurality of pixels;

a plurality of data line leads located in the non-display region and coupled to the plurality of data lines;

at least one switch control line, a plurality of data signal lines, and a plurality of test circuit groups located in the non-display area, each of the test circuit groups including a plurality of test circuits, each of the test circuits having a plurality of conductive film layers and being coupled to one of the switch control lines, one of the data signal lines, and one of the data line leads through the plurality of conductive film layers, and being configured to transmit a data signal from the data signal line to the data line via the data line lead in response to a switch control signal provided by the switch control line;

wherein, in the multi-layer conductive film layer included in each test circuit, the resistance value of the target conductive film layer coupled with the data line lead is inversely related to the length of the data line lead.

Optionally, the length of the orthographic projection of the target conductive film layer on the substrate is inversely related to the length of the data line lead.

Optionally, the width of the orthographic projection of the target conductive film layer on the substrate is positively correlated with the length of the data line lead.

Optionally, the maximum width of the orthographic projection of the target conductive film layer on the substrate is positively correlated with the length of the data line lead.

Optionally, the multilayer conductive film layer includes: the active layer, the first gate metal layer and the first source drain metal layer are positioned on one side of the substrate;

the active layer is coupled with the first source drain metal layer, the first source drain metal layer is also coupled with the data signal line and the data line lead respectively, and the first gate metal layer is coupled with the switch control line;

the target conductive film layer includes: the active layer is coupled with the data line lead through the first source drain metal layer.

Optionally, the display substrate further includes: a second gate metal layer and a second source drain metal layer;

the switch control line and the first source-drain metal layer are located on the same layer, the data signal line and the first source-drain metal layer and the second source-drain metal layer are located on the same layer, and the data line lead and the first gate metal layer or the second gate metal layer are located on the same layer.

Optionally, each of the pixels includes a plurality of sub-pixels of different colors, and each of the sub-pixels is coupled to one of the data lines; the number of the test circuits included in each test circuit group, the number of the switch control lines and the number of the data signal lines included in the display substrate are the same as the number of the sub-pixels included in each pixel;

each test circuit group comprises a plurality of test circuits, wherein each test circuit is coupled with different switch control lines and is coupled with different data signal lines;

and in each test circuit group, the test circuits coupled with the data lines corresponding to the sub-pixels with the same color share the same data signal line and the same switch control line.

Optionally, each of the pixels includes: red, green and blue sub-pixels;

in each test circuit group, the test circuit coupled with the data line corresponding to the red sub-pixel and the test circuit coupled with the data line corresponding to the blue sub-pixel share the same data line lead.

Optionally, each of the test circuits includes: a switching transistor;

the gate of the switching transistor is coupled to the switching control line, the first pole of the switching transistor is coupled to the data signal line, and the second pole of the switching transistor is coupled to the data line lead.

In another aspect, there is provided a display device including: a power supply assembly, and a display substrate as described in the above aspect;

the power supply assembly is coupled with the display substrate and used for supplying power to the display substrate.

To sum up, the beneficial effects brought by the technical scheme provided by the embodiment of the present disclosure at least include:

a display substrate and a display device are provided. The display substrate comprises a plurality of test circuit groups, each test circuit group comprises a plurality of test circuits, each test circuit is respectively coupled with a data signal line and a data line lead, the data line lead is coupled with a data line, and the data line is coupled with a pixel. Each test circuit can transmit a data signal supplied from the data signal line to the data line through the data line lead to light the pixel. Because the resistance value of the conductive film layer coupled with the data signal line in each test circuit is inversely related to the length of the data line lead, the effective compensation of the resistance values of the data line leads with different lengths can be realized, and the resistance values on the data line leads are close to each other. Furthermore, the uniformity of the data signals transmitted to the data lines is better, and the uniformity of the light emitting brightness of the pixels is better. Therefore, the lighting test can be ensured to have better precision.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a display substrate according to an embodiment of the disclosure;

FIG. 2 is a schematic diagram of a resistance distribution of leads of various data lines provided by an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of another display substrate provided in the embodiments of the present disclosure;

fig. 4 is a schematic structural diagram of another display substrate provided in the embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of another display substrate provided in an embodiment of the disclosure;

fig. 6 is a schematic structural diagram of another display substrate provided in an embodiment of the disclosure;

fig. 7 is a structural layout of a test circuit in a display substrate according to an embodiment of the present disclosure;

FIG. 8 is a structural layout of a test circuit in another display substrate provided by the embodiments of the present disclosure;

FIG. 9 is a structural layout of a test circuit in a display substrate according to an embodiment of the disclosure;

fig. 10 is a structural layout of a test circuit in a display substrate according to another embodiment of the disclosure;

FIG. 11 is a schematic diagram of a display substrate including a test circuit structure layout provided by an embodiment of the present disclosure;

fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

The terminology used in the description of the embodiments of the present disclosure is for the purpose of describing the embodiments of the present disclosure only and is not intended to be limiting of the present disclosure. Unless otherwise defined, technical or scientific terms used in the embodiments of the present disclosure should have the ordinary meaning as understood by those having ordinary skill in the art to which the present disclosure belongs. For example, the use of "first," "second," or "third," and similar language in the embodiments of this disclosure is not intended to imply any order, quantity, or importance, but rather the intention is to distinguish one element from another. Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprise" or "comprises", and the like, means that the element or item listed before "comprises" or "comprising" covers the element or item listed after "comprising" or "comprises" and its equivalents, and does not exclude other elements or items. "upper", "lower", "left", or "right", etc. are used merely to indicate relative positional relationships, which may also change accordingly when the absolute position of the object being described changes. "connect" or "couple" refers to an electrical connection. "and/or" means that three relationships may exist, e.g., A and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

Display devices employing OLED display substrates have become the mainstream trend at present, and the manufacturing of the display devices generally includes a substrate (panel, PNL) section and a module section which are sequentially performed. Wherein, the manufacture of the display substrate is mainly carried out in the PNL section; the module section mainly encapsulates a driving circuit and a display substrate, and the driving circuit is a circuit for driving the display substrate to display.

In addition, in order to verify the production of the PNL segment, a defective display substrate manufactured in the PNL segment is intercepted in advance to save the module material of the subsequent module segment, and to clarify the material relationship between the PNL segment and the module segment, a CT circuit is usually used in the PNL segment to perform a lighting test on pixels in the display substrate. And, in order to improve the utilization rate of the display substrate, the CT circuit is usually disposed at a Fanout (Fanout) position. That is, with reference to FIG. 1, the CT circuit is generally located at a lower intermediate position of the display substrate. The CT circuit is coupled to the data lines of the display substrate coupled to the pixels through a plurality of data line leads to illuminate the pixels. For example, a plurality of pixels in the display substrate are usually arranged in an array, a plurality of rows of pixels are correspondingly coupled to a plurality of data lines, and a plurality of data line leads are correspondingly coupled to the plurality of data lines one by one. In the lighting test, the data signals transmitted to the data line leads by the CT circuit are identical, and theoretically, the light emission luminance of each pixel should be identical.

However, due to the arrangement, the lengths of the leads of the data lines are different. Referring to fig. 1, when the CT circuit is located right under the display substrate at the middle position, the length of each data line lead is gradually shortened along the direction of the left and right sides of the display substrate near the middle position of the display substrate. Calculation formula of resistance value R of combined resistance: "R ═ ρ L/S; where ρ represents resistivity, determined by the properties of the structure (e.g., data line lead) itself that constitutes the resistance; l represents the length of the structure constituting the resistor; s represents the cross-sectional area of the resistance, "and the length of the data line lead is positively correlated with the magnitude of the resistance R. That is, the longer the length of the data line lead, the greater the resistance value thereon; conversely, the shorter the length of the data line lead, the smaller the resistance value thereon. Fig. 2 shows a resistance distribution on each data line lead to which each data line is coupled, from the left side to the right side of the display substrate. The abscissa indicates the position of the data line lead, and the ordinate indicates the magnitude of the resistance value R, which may be in ohms (Ω). As can be seen from fig. 2, the shortest data line at the middle of the display substrate has the smallest resistance value corresponding to the coupled data line lead, and the longest data lines at the two sides of the display substrate have the largest resistance value corresponding to the coupled data line lead. The different resistance values on the leads of the data lines lead to different loads (loading) on the leads of the data lines, which in turn causes poor uniformity of data signals transmitted to the data lines, different luminance of the pixels in each row, and non-uniform display luminance of the display substrate, resulting in the vertical defect (block mura) shown in fig. 1.

The embodiment of the disclosure provides a display substrate, when the lighting test is performed on the display substrate, the display substrate does not generate block mura shown in fig. 1 due to resistance value difference, and the lighting test precision is high.

Fig. 3 is a schematic structural diagram of a display substrate according to an embodiment of the disclosure. As shown in fig. 3, the display substrate includes: a substrate 01 having a display region a1 and a non-display region B1 at least partially surrounding the display region a 1. For example, fig. 3 shows the non-display region B1 located on the lower side of the display region a1, adjacent to the display region a1, i.e., partially surrounding the display region a 1. Of course, the non-display region B1 is not limited to being located at the lower side of the display region a1, and the non-display region B1 may be located at the upper side of the display region a 1.

With continued reference to fig. 3, the display substrate further comprises: a plurality of pixels 02 located in the display area a1, and a plurality of data lines D0. And a plurality of data line leads D1, at least one switch control line SW1, a plurality of data signal lines D2, and a plurality of test circuit groups 03 located in the non-display area B1.

The data lines D0 are coupled to the pixels 02 and are used for providing data signals to the pixels 02. The data line leads D1 are coupled to the data lines D0. For example, referring to fig. 3, a plurality of pixels 02 may be arranged in an array, pixels 02 located in the same column may be coupled to the same data line D0, and each data line lead D1 may be coupled to one data line D0. It should be noted that each pixel 02 may include a plurality of sub-pixels of different colors, each sub-pixel may be coupled to one data line D0, and the data lines D0 to which different sub-pixels are coupled are different. That is, each pixel 02 is coupled to a plurality of data lines D0.

Each test circuit group 03 includes a plurality of test circuits 031. Each test circuit 031 has a plurality of conductive film layers (not shown), and is coupled to one switch control line SW1, one data signal line D2, and one data line lead D1 through the plurality of conductive film layers. Each test circuit 031 is for transmitting a data signal supplied from the data signal line D2 to the data line D0 via the data line lead D1 in response to a switch control signal supplied from the switch control line SW 1. That is, the data signals supplied from the plurality of data lines D0 to the plurality of pixels 02 may be from the data signal line D2. The plurality of pixels 02 can emit light by being driven by the data signal, and thus, a lighting test of the plurality of pixels 02 is realized. The plurality of test circuit groups 03 herein correspond to the CT circuits described in the above embodiments.

Among the multiple conductive layers included in each test circuit 031, the resistance R of the target conductive layer coupled to the data line lead D1 is inversely related to the length of the data line lead D1. That is, the longer the length of the data line lead D1, the smaller the resistance value R of the target conductive film layer; conversely, the shorter the length of the data line lead D1, the greater the resistance value R of the target conductive film layer. Thus, for the data line lead D1 with a longer length and a larger resistance value R, the resistance value R of the data line lead D1 can be compensated by reducing the resistance value of the target conductive film layer in the test circuit 031 coupled thereto; for the data line lead D1 with a shorter length and a smaller resistance value R, the resistance value R of the data line lead D1 can be compensated by increasing the resistance value of the target conductive film layer in the test circuit 031 coupled thereto. Finally, the loading uniformity on the data line leads D1 with different lengths is better, so that the data signals transmitted to the data lines D0 by the test circuits 031 are more consistent, and the uniformity of the light emitting brightness of each pixel 02 is better. Furthermore, the test accuracy of the lighting test can be improved, and the test precision is better.

In summary, the embodiments of the present disclosure provide a display substrate. The display substrate comprises a plurality of test circuit groups, each test circuit group comprises a plurality of test circuits, each test circuit is respectively coupled with a data signal line and a data line lead, the data line lead is coupled with a data line, and the data line is coupled with a pixel. Each test circuit can transmit a data signal supplied from the data signal line to the data line through the data line lead to light the pixel. Because the resistance value of the conductive film layer coupled with the data signal line in each test circuit is inversely related to the length of the data line lead, the effective compensation of the resistance values of the data line leads with different lengths can be realized, and the resistance values on the data line leads are close to each other. Furthermore, the uniformity of the data signals transmitted to the data lines is better, and the uniformity of the light emitting brightness of the pixels is better. Therefore, the lighting test can be ensured to have better precision.

In combination with the above resistance value formula, in the embodiment of the disclosure, the resistance value of the target conductive film layer can be flexibly set by adjusting the length or the width of the orthographic projection of the target conductive film layer on the substrate 01.

As an alternative implementation, the length of the positive projection of the target conductive film layer of each test circuit 031 on the substrate 01 may be set to be inversely related to the length of the data line lead D1. That is, the longer the length of the data line lead D1, the shorter the length of the orthographic projection of the set target conductive film layer on the substrate 01; conversely, the shorter the length of the data line lead D1, the longer the length of the orthographic projection of the target conductive film layer set on the substrate 01.

Alternatively, as another alternative implementation, the width of the orthographic projection of the target conductive film layer of each test circuit 031 on the substrate 01 may be set to be positively correlated with the length of the data line lead D1. That is, the longer the length of the data line lead D1 is, the wider the width of the orthographic projection of the set target conductive film layer on the substrate 01 is; conversely, the shorter the length of the data line lead D1, the narrower the width of the orthographic projection of the target conductive film layer on the substrate 01 is set.

Of course, in some other embodiments, the length and the width of the orthographic projection of the target conductive film layer on the substrate 01 can be adjusted at the same time, so as to realize reliable compensation of the resistance value on the data line lead D1.

Alternatively, in the embodiment of the present disclosure, it may be that the maximum width of the orthographic projection of the target conductive film layer on the substrate 01 is set to be positively correlated with the length of the data line lead D1. For example, the width of the orthographic projection of the segments of the target conductive film layer on the substrate 01 is not uniform, wherein the width of the widest part is positively correlated with the length of the data line lead D1. Of course, in some other embodiments, the average width of the orthographic projection of the target conductive film layer on the substrate 01 may be positively correlated with the length of the data line lead D1. Alternatively, the widths of the orthographic projections of the segments of the target conductive film layer on the substrate 01 are consistent.

Alternatively, in the embodiment of the present disclosure, as described in the above embodiment, each pixel 02 may include a plurality of sub-pixels of different colors. On this basis, each sub-pixel may be coupled to a corresponding data line D0. The plurality of sub-pixels in the display substrate may be arranged in an array, and the sub-pixels in the same column may share the same data line D0. I.e., to the same data line D0.

The number of test circuits 031 included in each test circuit group 03, and the number of switch control lines SW1 and the number of data signal lines D2 included in the display substrate may be the same as the number of sub-pixels included in each pixel 02. Also, each of the test circuits 031 included in each of the test circuit groups 03 is coupled to a different switch control line SW1 and to a different data signal line D2. And, in each test circuit group 03, the test circuits 031 coupled to the data lines D0 corresponding to the sub-pixels of the same color share the same data signal line D2 (i.e., coupled to the same data signal line D2), and share the same switch control line SW1 (i.e., coupled to the same switch control line SW 1).

For example, referring to fig. 4, each pixel 02 shown includes: a Red (Red, R) sub-pixel R1, a Blue (Blue, B) sub-pixel B1, and a Green (G) sub-pixel G1. The red sub-pixel R1 in the same column is coupled to the same data line D0, the green sub-pixel G1 in the same column is coupled to the same data line D0, and the blue sub-pixel B1 in the same column is coupled to the same data line D0. Accordingly, each test circuit group 03 includes three test circuits 031 including a first test circuit 031-1, a second test circuit 031-2, and a third test circuit 031-3. The display substrate includes three switch control lines SW1-R1, SW1-G1 and SW1-B1, and three data signal lines D2-R1, D2-G1 and D2-B1. That is, the CT circuit according to the embodiment of the present disclosure is a CT circuit having a 3D3S (i.e., including 3 data signal lines and 3 switch control lines) configuration. Of course, in some embodiments, the CT circuit may have other configurations, such as 3D1S (i.e., including 3 data signal lines and 1 switch control line).

The first test circuit 031-1 may be coupled to switch control lines SW1-R1, data signal lines D2-R1, and a data line lead D1, respectively, and the data line lead D1 may be coupled to a data line D0 coupled to the red sub-pixel R1. The first test circuit 031-1 may be configured to transmit the data signals provided from the data signal lines D2-R1 to the data line D0 coupled to the red subpixel R1 via the data line lead D1 in response to the switch control signals provided from the switch control lines SW1-R1 to light the red subpixel R1. Also, the first test circuits 031-1 in different test circuit groups 03 are coupled to the switch control lines SW1-R1 and the data signal lines D2-R1.

The second test circuit 031-2 may be coupled to switch control lines SW1-B1, data signal lines D2-B1, and a data line lead D1, respectively, and the data line lead D1 may be coupled to a data line D0 to which the blue subpixel B1 is coupled. The second test circuit 031-2 may be configured to transmit the data signals provided from the data signal lines D2-B1 to the data line D0 coupled to the blue subpixel B1 via the data line lead D1 in response to the switch control signal provided from the switch control line SW1-B1 to light the blue subpixel B1. Also, the second test circuits 031-2 in different test circuit groups 03 are coupled to the switch control lines SW1-B1 and the data signal lines D2-B1.

The third test circuit 031-3 may be coupled to switch control lines SW1-G1, data signal lines D2-G1, and a data line lead D1, respectively, and the data line lead D1 may be coupled to a data line D0 to which the green sub-pixel G1 is coupled. The third test circuit 031-3 may be configured to transmit the data signals provided from the data signal lines D2-G1 to the data line D0 coupled to the green subpixel G1 via the data line lead D1 in response to the switch control signals provided from the switch control lines SW1-G1 to light the green subpixel G1. Also, the third test circuits 031-3 in different test circuit groups 03 are coupled to the switch control lines SW1-G1 and the data signal lines D2-G1.

Alternatively, referring to fig. 4, the sub-pixels of different colors are coupled to different data lines D0, and different test circuits 031 are coupled to different data lines D0 through different data line leads D1. Alternatively, referring to fig. 5, in each test circuit group 03, the test circuit 031 coupled to the data line D0 corresponding to the red sub-pixel R1 and the test circuit 031 coupled to the data line D0 corresponding to the blue sub-pixel B1 may share the same data line lead D1. I.e., the first test circuit 031-1 and the third test circuit 031-3 are coupled to the same data line lead D1. On this basis, as shown in fig. 5, the red sub-pixel R1 and the blue sub-pixel B1 may be coupled to the same data line D0 and to the same data line lead D1 through the same data line D0. Of course, in some embodiments, the red sub-pixel R1 and the blue sub-pixel B1 may be coupled to different data lines D0, and then the different data lines D0 are coupled to the same data line lead D1.

It is tested that the data signal required for driving the red sub-pixel R1 to emit light is closer to the data signal required for driving the blue sub-pixel B1 to emit light. Thus, by providing a data line lead D1 coupled to the data line D0 corresponding to the red sub-pixel R1 and the data line D0 corresponding to the blue sub-pixel B1, or further providing the red sub-pixel R1 and the blue sub-pixel B1 coupled to the same data line D0, the wiring can be simplified effectively, and the cost can be saved.

Taking the structure shown in fig. 5 as an example, fig. 6 shows a schematic structure diagram of another display substrate. As can be seen with reference to fig. 6, each of the test circuits 031 (i.e., the first test circuit 031-1, the second test circuit 031-2, and the third test circuit 031-3) may include: the transistor T1 is switched.

Wherein a gate of the switching transistor T1 may be coupled to the switching control line SW1, a first pole of the switching transistor T1 may be coupled to the data signal line D2, and a second pole of the switching transistor T1 may be coupled to the data line lead D1.

For example, the first test circuit 031-1 may include a switching transistor T1 having a gate coupled to a switching control line SW1-R1, a first pole coupled to a data signal line D2-R1, and a second pole coupled to a data line lead D1. The second test circuit 031-2 includes a switching transistor T1 whose gate may be coupled to a switch control line SW1-B1, whose first pole may be coupled to a data signal line D2-B1, and whose second pole may be coupled to a data line lead D1. The third test circuit 031-2 includes a switching transistor T1 whose gate may be coupled to a switch control line SW1-G1, whose first pole may be coupled to a data signal line D2-G1, and whose second pole may be coupled to a data line lead D1.

Also, the second pole of the switching transistor T1 included in the second test circuit 031-2 and the second pole of the switching transistor T1 included in the third test circuit 031-2 shown in fig. 6 are coupled to the same data line lead D1. In addition, as can also be seen with reference to fig. 6, each pixel 02 in the display substrate may include one red sub-pixel R1, one blue sub-pixel B1, and two green sub-pixels G1. The two green sub-pixels G1 are symmetrically disposed and coupled to the same data line lead D1. The red sub-pixel R1 and the blue sub-pixel B1 may each be polygonal in shape, and the size of the red sub-pixel R1 is smaller than the size of the blue sub-pixel B1. The green sub-pixel G1 may be shaped in a semicircle. Of course, in some embodiments, the sub-pixels may have other shapes, and the size of the red sub-pixel R1 may be larger than that of the blue sub-pixel B1.

For example, taking the case that the length of the orthographic projection of the target conductive film layer of each test circuit 031 on the substrate 01 is inversely related to the length of the data line lead D1, fig. 7 shows the structural layout of a first test circuit 031-1 and a second test circuit 031-2. FIG. 8 shows a layout of a third test circuit 031-3. And, taking as an example that the maximum width of the orthographic projection of the target conductive film layer of each test circuit 031 on the substrate 01 is positively correlated with the length of the data line lead D1, fig. 9 shows the structural layout of a first test circuit 031-1 and a second test circuit 031-2.

As can be seen with reference to fig. 7 to 9, each test circuit 031 has a plurality of conductive film layers that may include: an active layer (poly) P1, a first GATE metal layer GATE1, and a first source & drain (SD) metal layer SD1 on one side of the substrate 01. The active layer P1 may be coupled to the first source-drain metal layer SD1, the first source-drain metal layer SD1 may be coupled to the data signal line D2 and the data line lead D1, respectively, and the first GATE metal layer GATE1 may be coupled to the switch control line SW 1. On this basis, the target conductive film layer described in the above embodiment may include: and an active layer P1 coupled to the data line wiring D1 through the first source drain metal layer SD 1. That is, the resistance value of the data line wire D1 may be compensated by adjusting the length and/or width of the active layer P1.

For example, referring to fig. 7 and 8, and the corresponding partial enlarged views, it can be seen that the longer the data line wire D1, the shorter the length L0 of the active layer P1. As can be seen with reference to fig. 9 and its partial enlarged view, the longer the data line wire D1, the wider the width D0 of the active layer P1.

It should be noted that, when the width d0 is adjusted, the target conductive film layer may further include: and a first source-drain metal layer SD1 coupled to the data signal line D2. That is, the width of the first source-drain metal layer SD1 may be adjusted at the same time. Of course, in some embodiments, when the length L0 is adjusted, the length of the first source-drain metal layer SD1 may also be adjusted at the same time.

Alternatively, as can be seen with reference to fig. 7 to 9, the display substrate may further include: a second GATE metal layer GATE2 and a second source drain metal layer SD 2.

The switch control line SW1 may be located on the same layer as the first source-drain metal layer SD1, and the data signal line D2 may be located on the same layer as the first source-drain metal layer SD1 and the second source-drain metal layer SD2, that is, the data signal line D2 may include two source-drain metal layers, i.e., the source-drain metal layer SD1 and the source-drain metal layer SD 2. In this manner, stability of the data signal supplied from the data signal line D2 can be ensured. The data line wire D1 may be located at the same layer as the first GATE metal layer GATE1 or the second GATE metal layer GATE 2. For example, one data line wire D1 may be located at the same level as the first GATE metal layer GATE1 and the other data line wire D1 may be located at the same level as the second GATE metal layer GATE2 in every adjacent two data line wires D1.

Wherein, being located on the same layer may mean: and forming a film layer for forming a specific pattern by using the same film forming process, and patterning the film layer by using the same mask plate through a one-time composition process to form a layer structure. Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and/or portions located at the "same layer" are made of the same material and are formed through the same patterning process. Thus, manufacturing processes and manufacturing costs can be saved, and manufacturing efficiency can be accelerated.

Alternatively, with reference to fig. 7 to 9, the active layer P1, the first GATE metal layer GATE1, the second GATE metal layer GATE2, the first source drain metal layer SD1, and the second source drain metal layer SD2 may be sequentially stacked in a direction away from the substrate 01. There may be one or more insulating layers between each adjacent two layers. The first source-drain metal layer SD1 and the active layer P1 may be coupled by a via through an insulating layer therebetween, and the first source-drain metal layer SD1 and the first GATE metal layer GATE1 may be coupled by a via through an insulating layer therebetween.

Fig. 7 and 9 are schematic illustrations, and do not indicate a specific stacking positional relationship. The active layer P1, the first GATE metal layer GATE1, the second GATE metal layer GATE2, the first source-drain metal layer SD1, and the second source-drain metal layer SD2 are not limited to the stacked arrangement described in the embodiments of the present disclosure.

Alternatively, referring to fig. 3, in the embodiment of the present disclosure, the display region a1 and the non-display region B1 may be arranged along the first direction X1, the switch control line SW1 and the data signal line D2 in the display substrate may both extend along the second direction X2, the data line D0 may extend along the first direction X1, and the first direction X1 intersects the second direction X2. As shown in fig. 3, the first direction X1 and the second direction X2 are perpendicular to each other.

As can be seen from fig. 7 to 10, in each test circuit group 03 according to the embodiment of the disclosure, the first test circuit 031-1, the second test circuit 031-2, and the third test circuit 031-3 may be sequentially arranged along the first direction X1. And every two adjacent third test circuits 031-3 are taken as a group, the two third test circuits 031-3 may be arranged in a staggered manner along the first direction X1. And, the first test circuit 031-1 and the second test circuit 031-2 may share the active layer P1 and be coupled to the same data line lead D1.

Taking the structure shown in fig. 7 as an example, fig. 11 shows a schematic structural diagram of another display substrate. As can be further seen with reference to fig. 11, each test circuit set 03 may be located at Fanout and coupled to a data line D0 to which pixel 02 is coupled by a data line lead D1. And, the data line lead D1 becomes shorter and shorter in a direction closer to the center of the display substrate. Accordingly, as described in the above embodiments, referring to fig. 11, the active layer P1 included in the test circuit 031 may be longer and longer.

In summary, the embodiments of the present disclosure provide a display substrate. The display substrate comprises a plurality of test circuit groups, each test circuit group comprises a plurality of test circuits, each test circuit is respectively coupled with a data signal line and a data line lead, the data line lead is coupled with a data line, and the data line is coupled with a pixel. Each test circuit can transmit a data signal supplied from the data signal line to the data line through the data line lead to light the pixel. Because the resistance value of the conductive film layer coupled with the data signal line in each test circuit is inversely related to the length of the data line lead, the effective compensation of the resistance values of the data line leads with different lengths can be realized, and the resistance values on the data line leads are close to each other. Furthermore, the uniformity of the data signals transmitted to the data lines is better, and the uniformity of the light emitting brightness of the pixels is better. Therefore, the lighting test can be ensured to have better precision.

Fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. As shown in fig. 12, the display device includes: a power supply assembly J1, and a display substrate 00 as shown in the above figures.

The power supply assembly J1 is coupled to the display substrate 00 and is used for supplying power to the display substrate 00.

Optionally, the display device may be: an OLED display device, an active-matrix organic light-emitting diode (AMOLED) display device, a Liquid Crystal Display (LCD) device, a mobile phone, a tablet computer, a television, a display and any other product or component with a display function.

The above description is intended to be exemplary only and is not intended to limit the present disclosure, which is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

Claims (10)

1. A display substrate, comprising:

a substrate having a display area and a non-display area at least partially surrounding the display area;

a plurality of pixels located in the display area;

a plurality of data lines located in the display region and coupled to the plurality of pixels, and configured to provide data signals to the plurality of pixels;

a plurality of data line leads located in the non-display region and coupled to the plurality of data lines;

at least one switch control line, a plurality of data signal lines, and a plurality of test circuit groups located in the non-display area, each of the test circuit groups including a plurality of test circuits, each of the test circuits having a plurality of conductive film layers and being coupled to one of the switch control lines, one of the data signal lines, and one of the data line leads through the plurality of conductive film layers, and being configured to transmit a data signal from the data signal line to the data line via the data line lead in response to a switch control signal provided by the switch control line;

wherein, in the multi-layer conductive film layer included in each test circuit, the resistance value of the target conductive film layer coupled with the data line lead is inversely related to the length of the data line lead.

2. The display substrate of claim 1, wherein a length of a forward projection of the target conductive film layer on the substrate is inversely related to a length of the data line lead.

3. The display substrate of claim 1, wherein a width of an orthographic projection of the target conductive film layer on the substrate is positively correlated with a length of the data line lead.

4. The display substrate of claim 3, wherein a maximum width of an orthographic projection of the target conductive film layer on the substrate is positively correlated with a length of the data line lead.

5. The display substrate of any one of claims 1 to 4, wherein the multi-layer conductive film layer comprises: the active layer, the first gate metal layer and the first source drain metal layer are positioned on one side of the substrate;

the active layer is coupled with the first source drain metal layer, the first source drain metal layer is also coupled with the data signal line and the data line lead respectively, and the first gate metal layer is coupled with the switch control line;

the target conductive film layer includes: the active layer is coupled with the data line lead through the first source drain metal layer.

6. The display substrate of claim 5, further comprising: a second gate metal layer and a second source drain metal layer;

the switch control line and the first source-drain metal layer are located on the same layer, the data signal line and the first source-drain metal layer and the second source-drain metal layer are located on the same layer, and the data line lead and the first gate metal layer or the second gate metal layer are located on the same layer.

7. The display substrate according to any one of claims 1 to 4, wherein each of the pixels comprises a plurality of sub-pixels of different colors, and each of the sub-pixels is coupled to one of the data lines; the number of the test circuits included in each test circuit group, the number of the switch control lines and the number of the data signal lines included in the display substrate are the same as the number of the sub-pixels included in each pixel;

each test circuit group comprises a plurality of test circuits, wherein each test circuit is coupled with different switch control lines and is coupled with different data signal lines;

and in each test circuit group, the test circuits coupled with the data lines corresponding to the sub-pixels with the same color share the same data signal line and the same switch control line.

8. The display substrate of claim 7, wherein each of the pixels comprises: red, green and blue sub-pixels;

in each test circuit group, the test circuit coupled with the data line corresponding to the red sub-pixel and the test circuit coupled with the data line corresponding to the blue sub-pixel share the same data line lead.

9. The display substrate according to any one of claims 1 to 4, wherein each of the test circuits comprises: a switching transistor;

the gate of the switching transistor is coupled to the switching control line, the first pole of the switching transistor is coupled to the data signal line, and the second pole of the switching transistor is coupled to the data line lead.

10. A display device, characterized in that the display device comprises: a power supply assembly, and a display substrate according to any one of claims 1 to 9;

the power supply assembly is coupled with the display substrate and used for supplying power to the display substrate.

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