CN219679162U

CN219679162U - Display substrate and display device

Info

Publication number: CN219679162U
Application number: CN202320770476.8U
Authority: CN
Inventors: 徐鹏; 王威; 张毅
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2023-04-10
Filing date: 2023-04-10
Publication date: 2023-09-12
Anticipated expiration: 2033-04-10

Abstract

The utility model relates to the technical field of display, and provides a display substrate and a display device aiming at the frame wiring corrosion condition of the display substrate, wherein the display substrate comprises: the circuit comprises a substrate, a first voltage contact pad and a second voltage contact pad which are positioned in a first signal access area, a third voltage contact pad and a fourth voltage contact pad which are positioned in a second signal access area, at least one first connecting wire and at least one second connecting wire which are positioned in a connecting wiring area. The second signal access area is positioned at one side of the first signal access area far away from the display area, and the connecting wiring area is positioned between the first signal access area and the second signal access area. At least one first connection line is electrically connected to the first voltage contact pad and the third voltage contact pad; at least one second connection line is electrically connected to the second voltage contact pad and the fourth voltage contact pad. The shortest distance between the first connecting line and the adjacent second connecting line is more than 60 micrometers, so that the frame wiring corrosion condition of the display substrate in the reliability test is improved.

Description

Display substrate and display device

Technical Field

The present utility model relates to the field of display technologies, and in particular, to a display substrate and a display device.

Background

The organic light emitting diode (OLED, organic Light Emitting Diode) is an active light emitting display device, and has advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, high response speed, and the like. With the development of display technology, a display device using an OLED as a light emitting device and a thin film transistor (TFT, thin Film Transistor) for signal control has become a mainstream product in the display field.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

Aiming at the situation of frame wiring corrosion of a display substrate in reliability test, the embodiment of the utility model provides the display substrate and the display device.

In one aspect, the present embodiment provides a display substrate, including: the device comprises a substrate, at least one first voltage contact pad and at least one second voltage contact pad, at least one third voltage contact pad and at least one fourth voltage contact pad, at least one first connection line and at least one second connection line. The substrate comprises a display area, a first signal access area, a second signal access area and a connection wiring area, wherein the first signal access area, the second signal access area and the connection wiring area are positioned on one side of the display area, the first signal access area is far away from the display area, and the connection wiring area is positioned between the first signal access area and the second signal access area. At least one first voltage contact pad and at least one second voltage contact pad are located at the first signal access region. At least one third voltage contact pad and at least one fourth voltage contact pad are located in the second signal access region. At least one first connecting line and at least one second connecting line are positioned in the connecting wiring area. The at least one first connecting line is electrically connected with the at least one first voltage contact pad and the at least one third voltage contact pad; the at least one second connection line is electrically connected to the at least one second voltage contact pad and the at least one fourth voltage contact pad. The shortest distance between the first connection line and the adjacent second connection line is greater than 60 micrometers.

In some exemplary embodiments, the shortest distance between the first connection line and the adjacent second connection line is greater than or equal to 90 microns and less than or equal to 120 microns.

In some exemplary embodiments, the voltage signal transmitted by the first connection line is greater than the voltage signal transmitted by the second connection line.

In some exemplary embodiments, the display substrate further includes: at least one second inactive contact pad located at the second signal access region, the at least one second inactive contact pad located between the at least one third voltage contact pad and the at least one fourth voltage contact pad.

In some exemplary embodiments, the display substrate further includes: the at least one first ineffective connecting wire is electrically connected with the at least one second ineffective contact pad, and the at least one first ineffective connecting wire is located between the at least one first connecting wire and the at least one second connecting wire.

In some exemplary embodiments, a second inactive contact pad is disposed between the at least one third voltage contact pad and the at least one fourth voltage contact pad, the second inactive contact pad being electrically connected to two of the first inactive connection lines, the two first inactive connection lines being located between the first connection lines and the second connection lines.

In some exemplary embodiments, the display substrate further includes: at least one first non-effective contact pad located at the first signal access region, the at least one first non-effective contact pad being located between the at least one first voltage contact pad and at least one second voltage contact pad.

In some exemplary embodiments, the display substrate further includes: at least one second inactive connection line electrically connected to the at least one first inactive contact pad and the at least one second inactive contact pad.

In some exemplary embodiments, the minimum line width of the first connection line is greater than the width of the connected first voltage contact pad, and the minimum line width of the second connection line is greater than the width of the connected second voltage contact pad.

In some exemplary embodiments, the at least one first connection line and the at least one second connection line are located in different film layers.

In some exemplary embodiments, the display area includes: a plurality of sub-pixels, at least one of the plurality of sub-pixels including a pixel circuit and a light emitting element, the pixel circuit including at least one thin film transistor; the pixel circuit is electrically connected with the light emitting element through a first switching electrode. The at least one first connecting wire and the source electrode and the drain electrode of the thin film transistor are of the same-layer structure, and the at least one second connecting wire and the first switching electrode are of the same-layer structure; or the at least one first connecting line and the first switching electrode are in the same layer structure, and the at least one second connecting line and the source electrode and the drain electrode of the thin film transistor are in the same layer structure.

In some exemplary embodiments, the at least one first connection line and the at least one second connection line are double-layer wirings.

In some exemplary embodiments, the display area includes: a plurality of sub-pixels, at least one of the plurality of sub-pixels including a pixel circuit and a light emitting element, the pixel circuit including at least one thin film transistor; the at least one first connecting line and the at least one second connecting line are of the same layer structure with the source electrode and the drain electrode of the thin film transistor. The display substrate further includes: the first inorganic insulating layer is positioned in the connection wiring area, and the orthographic projection of the first inorganic insulating layer on the substrate covers the orthographic projection of the at least one first connection line and the at least one second connection line on the substrate.

In some exemplary embodiments, the display area includes: and a plurality of sub-pixels, at least one of the plurality of sub-pixels including a pixel circuit and a light emitting element, the pixel circuit being electrically connected to the light emitting element through a first transfer electrode. The display substrate further includes: a second flat layer on one side of the first transfer electrode away from the substrate, the second flat layer having at least a first region and a second region in a first frame region on one side of the display region, the thickness of the first region of the second flat layer being greater than the thickness of the second region of the second flat layer; the boundary position of the first area and the second area of the second flat layer is not overlapped with the orthographic projection of the at least one first connecting line and the at least one second connecting line on the substrate.

In some exemplary embodiments, the display substrate further includes: the integrated circuit is arranged in the first signal access area, the integrated circuit is electrically connected with the at least one first voltage contact pad and the at least one second voltage contact pad through the anisotropic conductive adhesive film, and the boundary of the anisotropic conductive adhesive film is positioned in the connection wiring area and is not overlapped with the boundary position of the first area and the second area of the second flat layer.

In another aspect, the present embodiment provides a display device including the display panel described above.

According to the display substrate provided by the embodiment, the shortest distance between the first connecting line and the adjacent second connecting line is larger than or equal to 60 micrometers, so that the situation that electrochemical corrosion occurs in the lower frame area can be improved.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate and do not limit the utility model. The shape and size of one or more of the components in the drawings do not reflect true proportions and are intended to be illustrative of the utility model.

FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the utility model;

FIG. 2 is a schematic partial cross-sectional view of a display area according to at least one embodiment of the utility model;

FIG. 3 is a schematic plan view of a portion of a first frame region according to at least one embodiment of the present utility model;

FIG. 4 is a schematic plan view of a portion of the region S1 in FIG. 3;

FIG. 5A is a schematic view of a partial cross section along the direction P-P' in FIG. 4;

FIG. 5B is a schematic partial cross-sectional view taken along the direction Q-Q' in FIG. 4;

FIG. 6 is another schematic diagram of a first connecting line and a second connecting line according to at least one embodiment of the present utility model;

FIG. 7 is another partial plan view of the region S1 of FIG. 3;

FIG. 8 is another partial plan view of the region S1 of FIG. 3;

FIG. 9 is another partial plan view of the region S1 of FIG. 3;

FIG. 10 is another partial plan view of the region S1 of FIG. 3;

FIG. 11 is an enlarged partial schematic view of the region S2 in FIG. 10;

FIG. 12 is another partial plan view of the region S1 of FIG. 3;

FIG. 13 is another partial plan view of the region S1 of FIG. 3;

FIG. 14 is another partial plan view of the region S1 of FIG. 3;

FIG. 15 is a schematic view in partial cross-section along the direction R-R' in FIG. 14;

FIG. 16 is another schematic partial cross-sectional view taken along the direction R-R' in FIG. 14;

FIG. 17 is another schematic partial cross-sectional view taken along the direction R-R' in FIG. 14;

FIG. 18 is another partial cross-sectional view taken along the direction R-R' in FIG. 14;

FIG. 19 is a partial plan view of the region S1 of FIG. 3;

fig. 20 is a schematic diagram of a display device according to at least one embodiment of the utility model.

Detailed Description

Embodiments of the present utility model will be described in detail below with reference to the accompanying drawings. Embodiments may be implemented in a number of different forms. One of ordinary skill in the art can readily recognize the fact that the manner and content of the utility model can be varied in a wide variety of forms without departing from the spirit and scope of the utility model. Therefore, the present utility model should not be construed as being limited to the following embodiments. Embodiments of the utility model and features of the embodiments may be combined with one another arbitrarily without conflict.

In the drawings, the size of one or more constituent elements, thicknesses of layers or regions may be exaggerated for clarity. Accordingly, one aspect of the utility model is not necessarily limited to this dimension, and the shape and size of one or more of the components in the drawings do not reflect true proportions. Further, the drawings schematically show ideal examples, and one embodiment of the present utility model is not limited to the shapes, numerical values, and the like shown in the drawings.

The ordinal numbers of "first", "second", "third", etc. in the present specification are provided to avoid mixing of constituent elements, and are not intended to be limited in number. The term "plurality" in the present utility model means two or more.

In the present specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, which indicate an azimuth or a positional relationship, are used to describe the positional relationship of the constituent elements with reference to the drawings, only for convenience of description of the present specification and simplification of the description, and do not indicate or imply that the apparatus or elements referred to must have a specific azimuth, be constructed and operated in a specific azimuth, and thus should not be construed as limiting the present utility model. The positional relationship of the constituent elements is appropriately changed according to the direction in which the respective constituent elements are described. Therefore, the present utility model is not limited to the words described in the specification, and may be appropriately replaced according to circumstances.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly, unless explicitly stated or limited otherwise. For example, it may be a fixed connection, a removable connection, or an integral connection; may be a mechanical connection, or a connection; may be directly connected, or indirectly connected through intermediate members, or may be in communication with the interior of two elements. The meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to circumstances.

In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and a current can flow through the drain electrode, the channel region, and the source electrode. In this specification, a channel region refers to a region through which current mainly flows.

In this specification, the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using a transistor having opposite polarity, or in the case of a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged with each other.

In this specification, "connected" includes a case where constituent elements are connected together by an element having some electric action. The "element having a certain electric action" is not particularly limited as long as it can transmit an electric signal between the connected constituent elements. Examples of the "element having some electric action" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present specification, "parallel" means a state in which two straight lines form an angle of-10 ° or more and 10 ° or less, and therefore, a state in which the angle is-5 ° or more and 5 ° or less is also included. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and thus includes a state in which the angle is 85 ° or more and 95 ° or less.

The terms "about" and "approximately" in the present utility model refer to a situation in which the limits are not strictly defined, and the process and measurement errors are allowed.

In the utility model, adjacent A and B means that A and B are close to each other, and no other wiring or pins exist between A and B.

In the actual use process of the electronic product by a user, different temperature and humidity conditions are faced. In different countries and regions, the electronic products may be damaged due to the influence of climate, use environment and the like, thereby affecting the normal use of the electronic products. Reliability testing is a common method for evaluating the tolerance of electronic products under extremely severe conditions. The current reliability test not only needs to meet the requirement of conventional use, but also provides a test requirement from continuous input to Failure (TTF) along with the expansion of the application range of electronic products.

The inventor finds that in product development, a great deal of corrosion can occur in the lower frame area of some display products in a reliability test, so that abnormal display functions of the display products are caused, for example, a screen pattern, a screen flashing, a single or multiple poor wires and the like are included. The corrosion position of the lower frame area of the display product is concentrated in a wiring area between an integrated circuit (IC, integrated Circuit) setting area and a binding pin area, and particularly the wiring position for transmitting high-voltage signals and low-voltage signals in the wiring area. The inventor finds through analysis that in the wiring area between the integrated circuit setting area and the binding pin area, the distance between the wirings for transmitting the high-voltage signal and the low-voltage signal is relatively close, so that electrochemical corrosion is easy to occur in the reliability process, the area is limited by the wiring space, the linewidths of the wirings for transmitting the high-voltage signal and the low-voltage signal are relatively small, and the wirings are more easy to heat and expand during transmitting the high-voltage signal and the low-voltage signal, so that corrosion is caused.

The embodiment provides a display substrate and a display device, which can improve the frame wiring corrosion condition of the display substrate in the reliability test.

The present embodiment provides a display substrate, including: the device comprises a substrate, at least one first voltage contact pad and at least one second voltage contact pad, at least one third voltage contact pad and at least one fourth voltage contact pad, at least one first connection line and at least one second connection line. The substrate comprises a display area, a first signal access area, a second signal access area and a connecting wiring area, wherein the first signal access area and the second signal access area are positioned on one side of the display area, the first signal access area is far away from the display area, and the connecting wiring area is positioned between the first signal access area and the second signal access area. At least one first voltage contact pad and at least one second voltage contact pad are located in the first signal access region. At least one third voltage contact pad and at least one fourth voltage contact pad are located in the second signal access region. The at least one first connecting wire and the at least one second connecting wire are positioned in the connecting wiring area. The at least one first connecting line is electrically connected with the at least one first voltage contact pad and the at least one third voltage contact pad; the at least one second connection line is electrically connected to the at least one second voltage contact pad and the at least one fourth voltage contact pad. The shortest distance between a first connection line and an adjacent second connection line is greater than 60 micrometers.

In some exemplary embodiments, the shortest distance between a first connection line and an adjacent second connection line may be greater than or equal to 90 microns and less than or equal to 120 microns. For example, the shortest distance between a first connection line and an adjacent second connection line may be greater than or equal to 100 microns and less than or equal to 110 microns.

The display substrate of the present example is illustrated below by some examples.

Fig. 1 is a schematic view of a display substrate according to at least one embodiment of the utility model. In some examples, as shown in fig. 1, the display substrate may include a display area AA and a peripheral area BB located at the periphery of the display area AA. The peripheral region BB may include: a first frame area B1 located at one side of the display area AA, and a second frame area B2 located at the other side of the display area AA. The first and second frame regions B1 and B2 may communicate with each other. For example, the first frame region B1 may be a lower frame region of the display substrate, and the second frame region B2 may include an upper frame region, a left frame region, and a right frame region of the display substrate.

In some examples, as shown in fig. 1, the display area AA may be rectangular, such as rounded rectangle. However, the present embodiment is not limited thereto. For example, the display area may be circular or elliptical or other shapes.

In some examples, as shown in fig. 1, the display area AA may include at least a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL. The orthographic projections of the plurality of gate lines GL and the plurality of data lines DL on the substrate may cross to form a plurality of sub-pixel regions, and one sub-pixel PX may be disposed in one sub-pixel region. The plurality of data lines DL may be electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL may be configured to supply data signals to the plurality of sub-pixels PX. The plurality of gate lines GL may be electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL may be configured to supply gate control signals to the plurality of sub-pixels PX. In some examples, the gate control signal may include a scan signal, or may include a scan signal and a light emission control signal, or may include a scan signal, a reset control signal, and a light emission control signal.

In some examples, as shown in fig. 1, the first direction X may be an extending direction (e.g., a row direction) of the gate lines GL in the display area AA, and the second direction Y may be an extending direction (e.g., a column direction) of the data lines DL in the display area AA. The first direction X and the second direction Y may intersect each other, for example, the first direction X and the second direction Y may be perpendicular to each other.

In some examples, one pixel unit of the display area AA may include three sub-pixels, which are red, green, and blue sub-pixels, respectively. However, the present embodiment is not limited thereto. In some examples, one pixel unit may include four sub-pixels, which are red, green, blue, and white sub-pixels, respectively.

In some examples, the shape of the subpixels may be rectangular, diamond-shaped, pentagonal, or hexagonal. When a pixel unit comprises three sub-pixels, the three sub-pixels can be arranged in a horizontal parallel, vertical parallel or delta mode; when a pixel unit includes four sub-pixels, the four sub-pixels may be arranged in a horizontal parallel, vertical parallel or square manner. However, the present embodiment is not limited thereto.

In some examples, one subpixel may include: a pixel circuit and a light emitting element connected to the pixel circuit. The pixel circuit may include a plurality of transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Wherein, T in the circuit structure refers to a thin film transistor, C refers to a capacitor, the number in front of T represents the number of the thin film transistors in the circuit, and the number in front of C represents the number of the capacitors in the circuit. In some examples, the plurality of transistors in the pixel circuit may be P-type transistors or may be N-type transistors. The same type of transistor is adopted in the pixel circuit, so that the process flow can be simplified, the process difficulty of the display substrate is reduced, and the yield of products is improved. In other examples, the plurality of transistors in the pixel circuit may include a P-type transistor and an N-type transistor.

In some examples, the plurality of transistors in the pixel circuit may employ low temperature polysilicon thin film transistors, or may employ oxide thin film transistors, or may employ low temperature polysilicon thin film transistors and oxide thin film transistors. The active layer of the low temperature polysilicon thin film transistor adopts low temperature polysilicon (LTPS, low Temperature Poly-Silicon), and the active layer of the Oxide thin film transistor adopts Oxide semiconductor (Oxide). The low-temperature polycrystalline silicon thin film transistor has the advantages of high mobility, quick charge and the like, the Oxide thin film transistor has the advantages of low leakage current and the like, and the low-temperature polycrystalline silicon thin film transistor and the Oxide thin film transistor are integrated on one display substrate, namely, an LTPS+oxide (LTPO) display substrate, so that the advantages of the low-temperature polycrystalline silicon thin film transistor and the Oxide thin film transistor can be utilized, low-frequency driving can be realized, power consumption can be reduced, and display quality can be improved.

In some examples, the light emitting element may be any of a light emitting diode (LED, light Emitting Diode), an organic light emitting diode (OLED, organic Light Emitting Diode), a quantum dot light emitting diode (QLED, quantum Dot Light Emitting Diodes), a micro LED (including: mini-LED or micro-LED), or the like. For example, the light emitting element may be an OLED, and the light emitting element may emit red light, green light, blue light, white light, or the like under the driving of its corresponding pixel circuit. The color of the light emitted by the light emitting element can be determined according to the need. In some examples, the light emitting element may include: an anode, a cathode, and an organic light emitting layer between the anode and the cathode. The anode of the light emitting element may be electrically connected to a corresponding pixel circuit. However, the present embodiment is not limited thereto.

Fig. 2 is a schematic partial cross-sectional view of a display area according to at least one embodiment of the utility model. Fig. 2 illustrates a structure of one sub-pixel of a display area of a display substrate. In this example, taking the same type of a plurality of transistors in a pixel circuit as an example, the plurality of transistors in the pixel circuit may each employ a low-temperature polysilicon thin film transistor or each employ an oxide thin film transistor, for example. In other examples, the plurality of transistors in the pixel circuit may employ low temperature polysilicon thin film transistors and oxide thin film transistors.

In some examples, as shown in fig. 2, in a direction perpendicular to the display substrate, the display substrate may include: a substrate 10, and a circuit structure layer 20, a light emitting structure layer 30, and a package structure layer 40 sequentially provided on the substrate 10. The circuit structure layer 20 may include at least: a pixel circuit of a plurality of sub-pixels, the pixel circuit of each sub-pixel may include a plurality of transistors and at least one capacitor; the light emitting structure layer 30 may include at least: a plurality of sub-pixels. In some possible implementations, the display substrate may include other film layers, such as spacer pillars, touch structure layers, color filter layers, and the like, which are not limited herein.

In some examples, the substrate 10 may be a rigid base, such as a glass base. However, the present embodiment is not limited thereto. In other examples, the substrate may be a flexible base, for example, made of an insulating material such as a resin. In addition, the substrate may have a single-layer structure or a multi-layer structure. When the substrate is a multilayer structure, inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride may be interposed between the layers in a single layer or in multiple layers.

In some examples, one thin film transistor 21 and one capacitor 22 included in each sub-pixel are illustrated in fig. 2 as an example. In some examples, the circuit structure layer 20 of the display region may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source drain metal layer, and a second source drain metal layer disposed on the substrate 10. A first gate insulating layer 101 may be disposed between the semiconductor layer and the first gate metal layer, a second gate insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer, an interlayer insulating layer 103 may be disposed between the second gate metal layer and the first source drain metal layer, a passivation layer 104 and a first planarization layer 105 may be disposed between the first source drain metal layer and the second source drain metal layer, and a second planarization layer 106 may be disposed on a side of the second source drain metal layer away from the substrate 10. However, the present embodiment is not limited thereto. In other examples, the passivation layer may be omitted between the first source drain metal layer and the second source drain metal layer.

In some examples, as shown in fig. 2, the semiconductor layer of the display region may include at least: an active layer 210 of the thin film transistor 21. The active layer 210 of the thin film transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least: a gate 213 of the thin film transistor 21, and a first plate 221 of the capacitor 22. The orthographic projection of the gate 213 of the thin film transistor 21 on the substrate 10 may cover the orthographic projection of the channel region 2100 of the active layer 210 on the substrate 10. The second gate metal layer may include at least: a second plate 222 of the capacitor 22. The second plate 222 and the first plate 221 of the capacitor 22 may at least partially overlap in the orthographic projection of the substrate 10, e.g., the two may coincide. The first source drain metal layer may include at least: a source 211 and a drain 212 of the thin film transistor 21. The interlayer insulating layer 103 may be provided with a plurality of vias (e.g., including a first pixel via and a second pixel via) in the display region, and the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 in the first pixel via may be removed to expose at least a portion of the surface of the first region 2101 of the active layer 210; the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 in the second pixel via hole may be removed to expose at least a portion of the surface of the second region 2102 of the active layer 210. The source electrode 211 of the thin film transistor 21 may be electrically connected to the first region 2101 of the active layer 210 through a first pixel via, and the drain electrode 212 may be electrically connected to the second region 2102 of the active layer 210 through a second pixel via. The second source drain metal layer may include at least: a first switching electrode 231. The first switching electrode 231 may be electrically connected to the drain electrode 212 of the thin film transistor 21 of the pixel circuit through a third pixel via hole formed in the passivation layer 104 and the first planarization layer 105. The first switching electrode 231 may be electrically connected to the first electrode 301 (e.g., anode) of the light emitting element through a fourth pixel via formed in the second planarization layer 106. The present example may realize an electrical connection between the pixel circuit and the light emitting element through the first switching electrode 231.

In some examples, as shown in fig. 2, the light emitting structure layer 30 may include: a pixel defining layer 304 and a plurality of light emitting elements. For example, each light emitting element may include: a first electrode 301, an organic light emitting layer 302, and a second electrode 303 are stacked. The first electrode 301 of the light emitting device may be an anode, and the first electrode 301 may be disposed on the second flat layer 106 and electrically connected to the first switching electrode 231 through a fourth pixel via hole formed in the second flat layer 106. The pixel defining layer 304 is disposed on the first electrode 301 and the second flat layer 106, and the pixel defining layer 304 may be provided with a plurality of pixel openings, and one pixel opening may expose at least a portion of a surface of a corresponding one of the first electrodes 301. At least a portion of the organic light emitting layer 302 may be disposed within one pixel opening and connected to the corresponding first electrode 301. The second electrode 303 may be disposed on the organic light emitting layer 302 and connected to the organic light emitting layer 302. The organic light emitting layer 302 may emit light of a corresponding color under the driving of the first electrode 301 and the second electrode 303. The side of the pixel defining layer 304 remote from the substrate 10 may also be provided with a spacer layer, which may include a Plurality of Spacers (PS).

In some examples, the organic light Emitting Layer 302 of the light Emitting element may include an Emitting Layer (EML, emission Layer), and one or more film layers including a Hole injection Layer (HIL, hole Injection Layer), a Hole transport Layer (HTL, hole Transport Layer), a Hole blocking Layer (HBL, hole Block Layer), an electron blocking Layer (EBL, electron Block Layer), an electron injection Layer (EIL, electron Injection Layer), and an electron transport Layer (ETL, electron Transport Layer). The first electrode 301 and the second electrode 303 can emit light according to a desired gray scale by using the light emission characteristics of the organic material.

In some examples, the light emitting layers of the different color light emitting elements may be different. For example, the red light emitting element includes a red light emitting layer, the green light emitting element includes a green light emitting layer, and the blue light emitting element includes a blue light emitting layer. In order to reduce the process difficulty and improve the yield, a common layer may be used for the hole injection layer and the hole transport layer on one side of the light emitting layer, and a common layer may be used for the electron injection layer and the electron transport layer on the other side of the light emitting layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer may be fabricated by one process (one evaporation process or one inkjet printing process), and isolation may be achieved by a surface level difference of the formed film layer or by surface treatment or the like. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the organic light emitting layer may be formed by evaporation using a Fine Metal Mask (FMM) or an Open Mask (Open Mask), or by an inkjet process.

In some examples, as shown in fig. 2, the encapsulation structure layer 40 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of an inorganic material, the second encapsulation layer 402 may be made of an organic material, and the second encapsulation layer 402 may be disposed between the first encapsulation layer 401 and the third encapsulation layer 403, so as to ensure that external moisture cannot enter the light emitting element. However, the present embodiment is not limited thereto. For example, the encapsulation structure layer may adopt an inorganic/organic/inorganic five-layer stacked structure.

In some examples, as shown in fig. 1, the first frame region B1 may include: the fanout wiring region B10, the first signal access region B11, the connection wiring region B13, and the second signal access region B12 are sequentially disposed in a direction away from the display region AA (e.g., a direction opposite to the second direction Y). The first signal access region B11 may be provided with a plurality of first contact pads, which may be configured to be in bonding connection with an integrated circuit (IC, integrated Circuit), which may be configured to generate driving signals required for driving the sub-pixels. For example, the driving signal may include a data signal driving the sub-pixel. The first signal access area B11 may also be referred to as an integrated circuit arrangement area. The second signal access region B12 may be provided with a plurality of second contact pads, which may be configured to be bonded to a circuit board, such as a flexible circuit board (FPC, flexible Printed Circuit). The connection routing region B13 may be provided with a plurality of connection wirings, and the plurality of connection wirings may be configured to connect the first contact pad in the first signal access region B11 and the second contact pad in the second signal access region B12. The second signal access zone B12 may also be referred to as a bonding pin setup zone.

In some examples, the peripheral region of the display substrate may be provided with a timing controller, a gate driving circuit (including, for example, a scan driving circuit and a light emission driving circuit), and a data driver. Wherein the scan driving circuit may be configured to supply a scan signal to the sub-pixels along the scan lines, and the light emission driving circuit may be configured to supply a light emission control signal to the sub-pixels along the light emission control lines. The data driver may be configured to supply the data signals to the subpixels along the data lines. The timing controller may be configured to control the scan driving circuit, the light emitting driving circuit, and the data driver. For example, the scan driving circuit may be disposed at a left frame region of the display substrate, and the light emitting driving circuit may be disposed at a right frame region of the display substrate; alternatively, the left and right frame regions of the display substrate may be provided with a scan driving circuit and a light emission driving circuit. In some examples, the scan driving circuit and the light emission driving circuit may be formed together with the sub-pixels in a process of forming the sub-pixels.

In some examples, the data driver may be disposed on a separate chip or printed circuit board to connect to the sub-pixels through the first contact pads of the first signal access region on the display substrate. For example, the data driver may form a first signal access region provided at the display substrate to be connected to the first contact pad using a chip on glass, a chip on plastic, a chip on film, or the like. The timing controller may be provided separately from the data driver or may be provided integrally with the data driver. However, the present embodiment is not limited thereto.

Fig. 3 is a schematic partial plan view of a first frame region according to at least one embodiment of the utility model. In some examples, as shown in fig. 1 and 3, a first circuit region B14 may be further disposed between the fanout wiring region B10 and the first signal access region B11, and a plurality of test circuits may be disposed within the first circuit region B14, and the test circuits may be configured to supply test data signals to the plurality of data lines DL of the display area AA during a test phase. The first circuit region B14 may also be provided with a plurality of electrostatic discharge circuits to provide a discharge path of static electricity.

In some examples, as shown in fig. 1 and 3, the fanout routing area B10 may communicate with the display area AA. The fan-out wiring region B10 may be provided with a plurality of lead-out wirings, and may include, for example, a plurality of data lead-out wires 511, a plurality of driving lead-out wires 512, a first power lead-out wire 513, and second power lead-out wires 514a and 514B. The plurality of data outgoing lines 511 may be disposed in the fan-out routing area in a fan-out routing manner and electrically connected to the plurality of data lines DL of the display area AA, for example, the plurality of data outgoing lines 511 and the plurality of data lines DL may be electrically connected in a one-to-one correspondence. The plurality of data lead lines 511 may extend to the first circuit region B14, for example, electrically connected to a test circuit in the first circuit region B14, and may also extend to the first signal access region B11, and electrically connected to corresponding first contact pads in the first signal access region B11. The plurality of driving lead wires 512 may extend from the left frame area and the right frame area into the fan-out routing area B10, and extend into the first signal access area B11, and electrically connect with corresponding first contact pads in the first signal access area B11.

In some examples, as shown in fig. 1 and 3, the first power supply lead 513 and the second power supply lead 514a and 514b may be located at a side of the plurality of data lead 511 and the plurality of driving lead 512 away from the substrate. The first power outlet 513 may be electrically connected to a high potential power line (e.g., VDD power line) of the display region AA and extend to be electrically connected to at least one second contact pad 62 of the second signal access region B12. The second power supply lead-out lines 514a and 514B may be electrically connected to low potential power supply lines (e.g., VSS power supply lines) in the left and right frame regions and extend to be electrically connected to at least one second contact pad 62 of the second signal access region B12. The second power outlet 514a and 514b may be located at opposite sides of the first power outlet 513 in the first direction X.

In some examples, as shown in fig. 3, the plurality of first contact pads within the first signal access area B11 may include at least: a first set of first contact pads 61a and a second set of first contact pads 61b. The first group of first contact pads 61a may be configured to receive and transmit external control signals to the integrated circuit, and the second group of first contact pads 61b may be configured to receive and transmit signals generated by the integrated circuit, for example, data signals to data lines of a display area through the plurality of data outlets 511 and driving control signals to the gate driving circuit through the plurality of driving outlets 512. The first group of first contact pads 61a in the first signal access region B11 may be electrically connected with the plurality of second contact pads 62 in the second signal access region B12 through the plurality of connection wirings 63.

Fig. 4 is a schematic plan view of a portion of the region S1 in fig. 3. Fig. 5A is a schematic partial cross-sectional view along the direction P-P' in fig. 4. Fig. 5B is a schematic partial cross-sectional view along the direction Q-Q' in fig. 4. The cross-sectional structure of a first contact pad is illustrated in fig. 5A, and the cross-sectional structure of a second contact pad is illustrated in fig. 5B.

In some examples, as shown in fig. 5A, one first contact pad may include: the three contact pad metal layers stacked in this order include, for example, a first contact pad metal layer 711, a second contact pad metal layer 712, and a third contact pad metal layer 713. The first contact pad metal layer 711 may have the same layer structure as the first gate metal layer of the display region, the second contact pad metal layer 712 may have the same layer structure as the first source drain metal layer of the display region, and the third contact pad metal layer 713 may have the same layer structure as the second source drain metal layer of the display region. The connection trace connected to the first contact pad may have the same layer structure as the second contact pad metal layer 712 or the third contact pad metal layer 713, and may have an integral structure. However, the present embodiment is not limited thereto. In other examples, the first contact pad metal layer 711 may have the same layer structure as the first gate metal layer of the display region.

In some examples, as shown in fig. 5B, one second contact pad may include: the two contact pad metal layers stacked in sequence include, for example, a fourth contact pad metal layer 721 and a fifth contact pad metal layer 722. The fourth contact pad metal layer 721 may have the same layer structure as the first source/drain metal layer of the display region, and the fifth contact pad metal layer 722 may have the same layer structure as the second source/drain metal layer of the display region. The connection trace connected to the second contact pad may have the same layer structure as the fourth contact pad metal layer 721 or the fifth contact pad metal layer 722, and may have an integral structure.

In some examples, as shown in fig. 3 and 4, the first set of first contact pads 61a of the first signal access region B11 may include: at least one first voltage contact pad 611 and at least one second voltage contact pad 612, e.g., two first voltage contact pads 611 and two second voltage contact pads 612. Wherein, two first voltage contact pads 611 are adjacent in the first direction X, and two second voltage contact pads 612 are adjacent in the first direction X. The two first voltage contact pads 611 and the two second voltage contact pads 612 are adjacent in the first direction X. The two first voltage contact pads 611 may be located at a side of the two second voltage contact pads 612 remote from the edge of the first signal access area B11 in the first direction X.

In some examples, as shown in fig. 4, the plurality of second contact pads of the second signal access area B12 may include: at least one third voltage contact pad 621 and at least one fourth voltage contact pad 622, e.g. two third voltage contact pads 621 and two fourth voltage contact pads 622. Wherein, two third voltage contact pads 621 are adjacent in the first direction X, and two fourth voltage contact pads 622 are adjacent in the first direction X. The two third voltage contact pads 621 and the two fourth voltage contact pads 622 may be adjacent in the first direction X. The two third voltage contact pads 621 may be located at a side of the two fourth voltage contact pads 622 away from the edge of the second signal access area B12 in the first direction X.

In some examples, as shown in fig. 4, the plurality of connection wirings connecting the routing region B13 may include: at least one first connection line 631 and at least one second connection line 632, for example two first connection lines 631 and two second connection lines 632. Both ends of a first connection line 631 may be electrically connected to a first voltage contact pad 611 and a third voltage contact pad 621, respectively, and both ends of a second connection line 632 may be electrically connected to a second voltage contact pad 612 and a fourth voltage contact pad 622, respectively. The two first connection lines 631 and the two second connection lines 632 may be adjacent in the first direction X, and the two first connection lines 631 and the two second connection lines 632 may be adjacent in the first direction X.

In some examples, the voltage signal transmitted by the first connection line 631 may be greater than the voltage signal transmitted by the second connection line 632. The first voltage contact pad 611, the third voltage contact pad 621, and the first connection line 631 may be configured to transmit a high voltage signal, for example, a VGH signal, and the second voltage contact pad 612, the fourth voltage contact pad 622, and the second connection line 632 may be configured to transmit a low voltage signal, for example, a VGL signal. For example, the voltage of the VGH signal may be about 7V and the voltage of the VGL signal may be about-7V. The present embodiment is not limited thereto.

In some examples, as shown in fig. 4, the first connection line 631 and the second connection line 632 may employ irregular wiring. For example, the first connection line 631 may include: the first line segment 6311, the second line segment 6312, and the third line segment 6313 are sequentially connected. One end of the first wire segment 6311 is electrically connected to a third voltage contact pad 621, the other end is electrically connected to one end of the second wire segment 6312, the other end of the second wire segment 6312 is electrically connected to one end of the third wire segment 6313, and the other end of the third wire segment 6313 is electrically connected to a first voltage contact pad 611. For example, the first connection line 631 may be integrally formed with the fourth contact pad metal layer of the connected third voltage contact pad 621 and the second contact pad metal layer of the connected first voltage contact pad 611; alternatively, the first connection line 631 may be integrally formed with the fifth contact pad metal layer of the connected third voltage contact pad 621 and the third contact pad metal layer of the connected first voltage contact pad 611.

In some examples, as shown in fig. 4, the first, second and third line segments 6311, 6312, 6313 of the first connection line 631 may be straight line segments, and the extending directions of the first, second and third line segments 6311, 6312, 6313 may be different. In some examples, the clockwise angle between the first and second line segments 6311, 6312 may be greater than the clockwise angle between the third and second line segments 6313, 6312. For example, the clockwise angle between the third and second line segments 6313, 6312 may be less than or equal to 90 degrees and the clockwise angle between the first and second line segments 6311, 6312 may be greater than 90 degrees.

In some examples, as shown in fig. 4, the second connection line 632 may include: the fourth line segment 6321, the fifth line segment 6322, and the sixth line segment 6323 are connected in this order. One end of the fourth wire segment 6321 is electrically connected to one fourth voltage contact pad 621, the other end is electrically connected to one end of the fifth wire segment 6322, the other end of the fifth wire segment 6322 is electrically connected to one end of the sixth wire segment 6323, and the other end of the sixth wire segment 6323 is electrically connected to one second voltage contact pad 612. For example, the second connection line 632 and the fourth contact pad metal layer of the connected fourth voltage contact pad 622 and the second contact pad metal layer of the connected second voltage contact pad 612 may be of a unitary structure; alternatively, the second connection line 632 and the fifth contact pad metal layer of the connected fourth voltage contact pad 622 and the third contact pad metal layer of the connected second voltage contact pad 612 may be in a unitary structure.

In some examples, as shown in fig. 4, the fourth, fifth, and sixth line segments 6321, 6322, 6323 of the second connection line 632 may be straight line segments, and the extending directions of the fourth, fifth, and sixth line segments 6321, 6322, 6323 may be different. In some examples, the clockwise angle between the fourth line segment 6321 and the fifth line segment 6322 may be greater than the clockwise angle between the sixth line segment 6323 and the fifth line segment 6322. For example, the clockwise angle between the fourth line segment 6321 and the fifth line segment 6322 may be greater than 90 degrees, and the clockwise angle between the sixth line segment 6323 and the fifth line segment 6322 may be less than or equal to 90 degrees.

In some examples, the clockwise angle between the fourth line segment 6321 and the fifth line segment 6322 may be greater than the clockwise angle between the first line segment 6311 and the second line segment 6312, and the clockwise angle between the sixth line segment 6323 and the fifth line segment 6322 may be less than the clockwise angle between the third line segment 6313 and the second line segment 6312.

In some examples, the length of the first wire segment 6311 of the first connection wire 631 may be greater than the lengths of the second wire segment 6312 and the third wire segment 6313, and the length of the third wire segment 6313 may be greater than the length of the second wire segment 6312. The fourth line segment 6321 of the second connection line 632 may have a length greater than that of the fifth line segment 6322 and the sixth line segment 6323, for example, the fifth line segment 6322 may have a length greater than or equal to that of the sixth line segment 6323. The shortest distance between the first wire segment 6311 of the first connection wire 631 and the fourth wire segment 6321 between the adjacent second connection wire 632 may be greater than the shortest distance between the second wire segment 6312 and the adjacent fifth wire segment 6322 and greater than the shortest distance between the third wire segment 6313 and the sixth wire segment 6323. In some examples, the shortest distance between the first connection line 631 and the adjacent second connection line 632 may be greater than or equal to 60 micrometers, for example, may be greater than or equal to 65 micrometers. For example, the shortest distance between the first wire segment 6311 of the first connection wire 631 and the fourth wire segment 6321 of the adjacent second connection wire 632 may be greater than or equal to 90 micrometers and less than or equal to 120 micrometers, such as may be greater than or equal to 100 micrometers and less than or equal to 110 micrometers.

By providing the first connection line 631 and the second connection line 632 in an irregular wiring manner, the distance between the first connection line 631 and the adjacent second connection line 632 can be increased in this example, so as to reduce the risk of electrochemical corrosion occurring between the first connection line and the adjacent second connection line in the reliability test.

Fig. 6 is another schematic diagram of a first connecting line and a second connecting line according to at least one embodiment of the present utility model. In some examples, as shown in fig. 6, the second line segment 6312 and the third line segment 6313 of the first connection line 631 may be substantially perpendicular to each other. The clockwise angle a1 between the first and second line segments 6311 and 6312 of the first connection line 631 may be greater than the clockwise angle a2 between the third and second line segments 6313 and 6312. For example, a2 may be about 90 degrees and a1 may be greater than 90 degrees. The clockwise angle a3 between the fourth and fifth line segments 6321 and 6322 of the second connection line 632 may be greater than the clockwise angle a1 between the first and second line segments 6311 and 6312 of the first connection line 631. The clockwise angle a4 between the sixth line segment 6323 and the fifth line segment 6322 of the second connection line 632 may be greater than the clockwise angle a2 between the third line segment 6313 and the second line segment 6312 of the first connection line 631. For example, the clockwise angle a3 between the fourth line segment 6321 and the fifth line segment 6322 of the second connection line 632 may be substantially the same as the clockwise angle a4 between the sixth line segment 6323 and the fifth line segment 6322.

By adjusting the angles of a1, a2, a3, and a4, the irregular wiring pattern of the first connection line and the second connection line can be adjusted, thereby increasing the distance between the first connection line 631 and the adjacent second connection line 632 to reduce the risk of electrochemical corrosion occurring between the first connection line and the adjacent second connection line in the reliability test.

Fig. 7 is another partial plan view of the region S1 in fig. 3. In some examples, as shown in fig. 7, the plurality of second contact pads of the second signal access area B12 may include: two third voltage contact pads 621, two fourth voltage contact pads 622, and one second inactive contact pad 623 located between the two third voltage contact pads 621 and the two fourth voltage contact pads 622. Two third voltage contact pads 621, a second inactive contact pad 623, and two fourth voltage contact pads 622 may be arranged along one side of the first direction X. The film structure of the second ineffective contact pad 623 may be identical to the film structures of the third voltage contact pad and the fourth voltage contact pad, so that the description thereof is omitted.

In some examples, the width of the second inactive contact pad 623 (i.e., the length in the first direction X) may be 60 micrometers to 70 micrometers, such as may be about 65 micrometers.

In this example, by adding a second inactive contact pad between the third voltage contact pad and the fourth voltage contact pad, the distance between the first connection line 631 and the adjacent second connection line 632 is facilitated to be increased to reduce the risk of electrochemical corrosion occurring between the first connection line and the adjacent second connection line in the reliability test. The description of the rest of the structure of this example can refer to the description of the foregoing embodiment, so that the description is omitted here.

Fig. 8 is another partial plan view of the region S1 in fig. 3. In some examples, as shown in fig. 8, the plurality of second contact pads of the second signal access area B12 may include: two third voltage contact pads 621, two fourth voltage contact pads 622, and one second inactive contact pad 623 located between the two third voltage contact pads 621 and the two fourth voltage contact pads 622. The plurality of connection traces of the connection trace region B13 may include: two first connection lines 631, two second connection lines 632, and one first inactive connection line 633. The first inactive connection line 633 may be located between the two first connection lines 631 and the two second connection lines 632. The first inactive connection line 633 may be electrically connected to the first inactive contact pad 623 of the second signal access area B12. For example, the first inactive connection line 633 and one of the contact pad metal layers of the first inactive contact pad 623 may be in a unitary structure.

In some examples, as shown in fig. 8, the first inactive connection line 633 may extend in one direction. The first inactive connection line 633 may be located between a first line segment of the first connection line 631 and a fourth line segment of the adjacent second connection line 632. The extending directions of the first line segments of the first inactive connection line 633 and the first connection line 631 may be substantially the same, or the extending directions of the fourth line segments of the first inactive connection line 633 and the second connection line 632 may be substantially the same.

This example can increase the shielding effect of transmission signal between first connecting wire and the second connecting wire through setting up first invalid connecting wire between first connecting wire and adjacent second connecting wire, is favorable to reducing the risk of taking place electrochemical corrosion between first connecting wire and the adjacent second connecting wire in the reliability test. The description of the rest of the structure of this example can refer to the description of the foregoing embodiment, so that the description is omitted here.

Fig. 9 is another partial plan view of the region S1 in fig. 3. In some examples, as shown in fig. 9, the plurality of second contact pads of the second signal access area B12 may include: two third voltage contact pads 621, two fourth voltage contact pads 622, and one second inactive contact pad 623 located between the two third voltage contact pads 621 and the two fourth voltage contact pads 622. The plurality of connection traces of the connection trace region B13 may include: two first connection lines 631, two second connection lines 632, and two first inactive connection lines 633a and 633b. The two first inactive connection lines 633a and 633b are adjacent to each other and are located between the two first connection lines 631 and the two second connection lines 632. The first inactive connection line 633a may be adjacent to the first connection line 631, and the first inactive connection line 633b may be adjacent to the second connection line 632. The two first inactive connection lines 633a and 633B may be electrically connected to the same second inactive contact pad 623 of the second signal access area B12. For example, the two first inactive connection lines 633a and 633b may be integrally formed with one of the contact pad metal layers of one of the second inactive contact pads 623. However, the present embodiment is not limited thereto. In other examples, the second signal access region may include: two or more second inactive contact pads located between the third voltage contact pad and the fourth voltage contact pad, and each of the second inactive contact pads may be electrically connected with at least one of the first inactive connection lines.

In some examples, as shown in fig. 9, the extending directions of the first inactive connection lines 633a and 633b may be the same, and may each extend in one direction. The first inactive connection lines 633a and 633b may be located between a first line segment of the first connection line 631 and a fourth line segment of the adjacent second connection line 632. The extending directions of the first line segments of the first connection lines 631 and the first inactive connection lines 633a and 633b may be substantially the same, or the extending directions of the fourth line segments of the second connection lines 632 and the first inactive connection lines 633a and 633b may be substantially the same.

This example is through setting up two first invalid connecting lines between first connecting line and adjacent second connecting line, can increase the shielding effect of transmission signal between first connecting line and the second connecting line, is favorable to reducing the risk of taking place electrochemical corrosion between first connecting line and the adjacent second connecting line in the reliability test. The description of the rest of the structure of this example can refer to the description of the foregoing embodiment, so that the description is omitted here.

Fig. 10 is another partial plan view of the region S1 in fig. 3. Fig. 11 is a partially enlarged schematic view of the region S2 in fig. 10. In some examples, as shown in fig. 10 and 11, the first signal access area B11 may include at least: two first voltage contact pads 611 and two second voltage contact pads 612. The two first voltage contact pads 611 and the two second voltage contact pads 612 may be adjacent in the first direction X. The second signal access area B12 may include at least: two third voltage contact pads 621 and two fourth voltage contact pads 622. The two third voltage contact pads 621 and the two fourth voltage contact pads 622 may be adjacent in the first direction X. The connection routing area B13 may include at least: two first connection lines 631 and two second connection lines 632. The two first connection lines 631 and the two second connection lines 632 may each be a straight line segment extending in one direction. The first connection line 631 may be electrically connected to the first voltage contact pad 611 at a first end and to the third voltage contact pad 621 at a second end; the second connection line 632 may have a first end electrically connected to the second voltage contact pad 612 and a second end electrically connected to the fourth voltage contact pad 622.

In some examples, as shown in fig. 11, the line width of the first end of the first connection line 631 may be greater than the width of the first voltage contact pad 611, and the line width of the first end of the second connection line 632 may be greater than the width of the second voltage contact pad 612. For example, the line width of the first end of the first connection line 631 may be greater than or equal to 4 micrometers, and the line width of the first end of the second connection line 632 may be greater than or equal to 4 micrometers. The line widths of the different positions of the first connection line 631 may be substantially the same, or the line width of the first connection line 631 may be gradually increased from the first end, and the line width of the first end of the first connection line 631 may be smaller than that of the second end. The line widths of the different positions of the second connection line 632 may be substantially the same, or the line width of the second connection line 632 may be gradually increased from the first end, and the line width of the first end of the second connection line 632 may be smaller than that of the second end. In some examples, the line width of the first connection line 631 and the line width of the second connection line 632 may be substantially the same. However, the present embodiment is not limited thereto.

The present example can reduce the impedance of the first and second connection lines by increasing the line widths of the first and second connection lines, thereby reducing the risk of electrochemical corrosion occurring between the first and second connection lines adjacent to each other in the reliability test. The description of the rest of the structure of this example can refer to the description of the foregoing embodiment, so that the description is omitted here.

Fig. 12 is another partial plan view of the area S1 in fig. 3. In some examples, as shown in fig. 12, the first signal access zone B11 may include: two first voltage contact pads 611, two second voltage contact pads 612, and one first inactive contact pad 613 between the two first voltage contact pads 611 and the two second voltage contact pads 612. The first inactive contact pad 613 may be adjacent to the first voltage contact pad 611 and the second voltage contact pad 613. For example, the width of the first non-active contact pad may be about 65 microns. The second signal access area B12 may include: two third voltage contact pads 621, two fourth voltage contact pads 622, and one second inactive contact pad 623 located between the two third voltage contact pads 621 and the two fourth voltage contact pads 622. The connection routing area B13 may include at least: two first connection lines 631 and two second connection lines 632. The first connecting line 631 and the second connecting line 632 may have a substantially linear shape, for example.

The present example may help to increase the distance between the first connection line and the second connection line by providing at least one first non-effective contact pad between the first voltage contact pad and the second voltage contact pad within the first signal access region B11, which may help to reduce the rate of electrochemical corrosion occurring between the first connection line and the adjacent second connection line during the reliability test. The rest of the structure of this example can be referred to the description of the foregoing embodiments, and thus will not be repeated here.

Fig. 13 is another partial plan view of the region S1 in fig. 3. In some examples, as shown in fig. 13, the first signal access zone B11 may include: two first voltage contact pads 611, two second voltage contact pads 612, and one first inactive contact pad 613 between the two first voltage contact pads 611 and the two second voltage contact pads 612. The second inactive contact pad 613 may be adjacent to the first voltage contact pad 611 and the second voltage contact pad 612. The second signal access area B12 may include: two third voltage contact pads 621, two fourth voltage contact pads 622, and one second inactive contact pad 623 located between the two third voltage contact pads 621 and the two fourth voltage contact pads 622. The connection routing area B13 may include: two first connection lines 631, two second connection lines 632, and one second inactive connection line 634. The second inactive connection line 634 has a first end electrically connected to the first inactive contact pad 613 and a second end electrically connected to the second inactive contact pad 623. The second inactive connection line 634 may be located between the first connection line 631 and the second connection line 632. The second inactive connection line 634 may be integral with one of the contact pad metal layers of the first inactive contact pad 612, or may be integral with one of the contact pad metal layers of the second inactive contact pad 623. For example, the shapes of the first connection line 631, the second connection line 632, and the second ineffective connection line 634 may be substantially linear shapes.

The present example may facilitate reducing the rate at which electrochemical corrosion occurs between a first connection line and an adjacent second connection line during reliability testing by providing a second inactive connection line between the first connection line and the second connection line. The rest of the structure of this example can be referred to the description of the foregoing embodiments, and thus will not be repeated here.

Fig. 14 is another partial plan view of the region S1 in fig. 3. In some examples, as shown in fig. 14, the plurality of first contact pads of the first signal access area B11 may include: two first voltage contact pads 611 and two second voltage contact pads 612. The two first voltage contact pads 611 and the two second voltage contact pads 612 are adjacent in the first direction X. The plurality of second contact pads of the second signal access region B12 may include: two third voltage contact pads 621, two fourth voltage contact pads 622, and one second inactive contact pad 623. The second inactive contact pad 623 may be located between the two third voltage contact pads 621 and the two fourth voltage contact pads 622. The plurality of connection traces of the connection trace region B13 may include: two first connecting lines 631 and two second connecting lines 632. The first connection line 631 may connect the first voltage contact pad 611 and the third voltage contact pad 621, and the second connection line 632 may connect the second voltage contact pad 612 and the fourth voltage contact pad 622. For example, the first connection line 631 and the second connection line 632 may have a substantially linear shape. Alternatively, the first connection line 631 and the second connection line 632 may be substantially in the shape of a broken line.

Fig. 15 is a schematic partial cross-sectional view taken along the direction R-R' in fig. 14. In some examples, as shown in fig. 15, the first connection line 631 may include: the first and second sub-wirings 6311 and 6312 are stacked. The second sub-trace 6312 may be electrically connected to the first sub-trace 6311 through a groove or a via formed in the first planarization layer 105 and the passivation layer 104. The second connection line 632 may include: the third and fourth sub-wirings 6321 and 6322 are stacked. The fourth sub-trace 6322 may be electrically connected to the third sub-trace 6321 through a groove or a via formed in the first planarization layer 105 and the passivation layer 104. The first and third sub-wires 6311 and 6321 may be of a same layer structure, and the second and fourth sub-wires 6312 and 6322 may be of a same layer structure. For example, the first and third sub-wires 6311 and 6321 may be located at the first source-drain metal layer, and the second and fourth sub-wires 6312 and 6322 may be located at the second source-drain metal layer.

The first connecting wire and the second connecting wire of this example can adopt double-deck wiring mode, can reduce the resistance that single was walked to reduce and walk the line risk of generating heat. The rest of the structure of this example can be referred to the description of the foregoing embodiments, and thus will not be repeated here.

FIG. 16 is another partial cross-sectional view taken along the direction R-R' in FIG. 14. In some examples, as shown in fig. 16, the first connection line 631 and the second connection line 632 may be single-layered wirings. The first connection line 631 and the second connection line 632 may have a same layer structure, for example, may be located in the first source drain metal layer. The connection trace area may be provided with a first inorganic insulating layer 104a, and the orthographic projection of the first inorganic insulating layer 104a on the substrate 10 may cover the orthographic projections of the first connection line 631 and the second connection line 632 on the substrate. The first inorganic insulating layer 104a protects the first connection line 631 and the second connection line 632 by covering the first connection line 631 and the second connection line 632. The first inorganic insulating layer 104a and the passivation layer 104 may be in a unitary structure. The rest of the structure of this example can be referred to the description of the foregoing embodiments, and thus will not be repeated here.

FIG. 17 is another partial cross-sectional view taken along the direction R-R' in FIG. 14. In some examples, as shown in fig. 17, the first connection line 631 and the second connection line 632 may be single-layer wirings. The first connection line 631 may be located on the first source drain metal layer, and the second connection line 632 may be located on the second source drain metal layer. The connection trace region may be provided with a first inorganic insulating layer 104a, and the first inorganic insulating layer 104a may cover the first connection line 631. This example is located different retes through setting up first connecting wire and second connecting wire, can increase the distance between first connecting wire and the second connecting wire to be favorable to reducing the risk that electrochemical corrosion takes place between first connecting wire and the adjacent second connecting wire in the reliability test. The rest of the structure of this example can be referred to the description of the foregoing embodiments, and thus will not be repeated here.

FIG. 18 is another partial cross-sectional view taken along the direction R-R' in FIG. 14. In some examples, as shown in fig. 18, the first connection line 631 and the second connection line 632 may be single-layered wirings. The second connection line 632 may be located in the first source drain metal layer, and the first connection line 631 may be located in the second source drain metal layer. The connection trace region may be provided with a first inorganic insulating layer 104a, and the first inorganic insulating layer 104a may cover the second connection line 632. This example is located different retes through setting up first connecting wire and second connecting wire, can increase the distance between first connecting wire and the second connecting wire to be favorable to reducing the risk that electrochemical corrosion takes place between first connecting wire and the adjacent second connecting wire in the reliability test. The rest of the structure of this example can be referred to the description of the foregoing embodiments, and thus will not be repeated here.

Fig. 19 is a partial plan view schematically illustrating a region S1 in fig. 3. In some examples, as shown in fig. 19, the integrated circuit disposed in the first signal access area B11 may be electrically connected to the plurality of first contact pads through an anisotropic conductive film (ACF, anisotropic Conductive Film). At least part of the boundary F1 of the anisotropic conductive film may be located in the connection trace region B13. For example, the boundary F1 of the anisotropic conductive film may extend at least along the first direction X.

In some examples, the second planar layer may have a first region and a second region at the first border region. The thickness of the first region of the second planar layer may be greater than the thickness of the second region of the second planar layer. In this example, the thickness may refer to the perpendicular distance between the surface of the film layer on the side away from the substrate and the surface on the side closer to the substrate. The second planar layer may be prepared, for example, by a half-tone mask process. For example, in the process of preparing the second flat layer in the first frame region, a mask having a Halftone design may be used to prepare the second flat layer, so that the second flat layer may form a first region and a second region with different thicknesses in the first frame region, where the second region may form a non-smooth edge, thereby reducing an edge profile (profile) of the insulating layer and increasing a process boundary (margin). However, the present embodiment is not limited thereto. For example, the second planar layer may also be formed using a reticle preparation having a gray scale mask (gray tone) design.

In some examples, taking a halftone mask designed with a halftone mask as an example, the halftone mask may include a transparent region, an opaque region, and a translucent region, the transparent region may correspond to at least an open area of the display region and a recessed area of the first frame region, the translucent region may correspond to at least a second area of the second planar layer in the first frame region, and the opaque region may correspond to a remaining area of the display substrate. For example, before the light emitting structure layer is prepared, a photoresist may be coated on the first planarization layer, and after the photoresist is exposed and developed using a halftone mask, a photoresist full-reserved region, a photoresist half-reserved region, and a photoresist full-removal region may be formed. The photoresist full-reserved area corresponds to an opaque area of the half-tone mask, the photoresist half-reserved area corresponds to a semitransparent area of the half-tone mask, and the photoresist full-removed area corresponds to a transparent area of the half-tone mask. Subsequently, an etching process may be sequentially performed in the photoresist complete removal region and the photoresist half-reserved region. The thickness of the second region of the second planarization layer may be smaller than the thickness of the second planarization layer corresponding to the photoresist full reserved region (i.e., the first region). The junction position of the second flat layer in the first area and the second area of the first frame area and the orthographic projection of the first connecting line and the second connecting line of the connecting wiring area on the substrate may not overlap. The boundary position of the second flat layer at the first region and the second region of the first frame region and the boundary F1 of the anisotropic conductive film may not overlap. For example, the boundary position of the second flat layer between the second area and the first area of the first frame area may be located at one side of the boundary F1 of the anisotropic conductive film in the first direction X, and does not overlap with the boundary F1 of the anisotropic conductive film. The orthographic projection of the second flat layer on the substrate in the second area of the first frame area can cover the orthographic projection of a plurality of connecting wirings connected with the wiring area on the substrate.

According to the method, the boundary position of the first area and the second area of the second flat layer is optimized, so that the boundary position of the first area and the second area of the second flat layer is not overlapped with the boundary of the first connecting wire, the second connecting wire and the anisotropic conductive adhesive film, the first connecting wire and the second connecting wire can be prevented from being arranged at the position of the film layer section difference of the second flat layer, the film layer section difference of the connecting wiring position of the connecting wiring area can be reduced, the risk of electrochemical corrosion between the first connecting wire and the adjacent second connecting wire in the reliability test is reduced, and the influence of the film layer section difference of the second flat layer on the integrated circuit arrangement can be improved. The rest of the structure of this example can be referred to the description of the foregoing embodiments, and thus will not be repeated here.

Fig. 20 is a schematic diagram of a display device according to at least one embodiment of the utility model. As shown in fig. 20, the present embodiment provides a display device 91 including the display panel 910 of the foregoing embodiment. In some examples, display panel 910 may be an OLED display panel. The display device 91 may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame or a navigator.

The drawings in the present utility model relate only to the structure to which the present utility model relates, and other structures may be referred to as general designs. Features of embodiments of the utility model, i.e. embodiments, may be combined with each other to give new embodiments without conflict. It will be understood by those skilled in the art that various modifications and equivalent substitutions may be made to the technical solution of the present utility model without departing from the spirit and scope of the technical solution of the present utility model, and it is intended to cover the scope of the claims of the present utility model.

Claims

1. A display substrate, comprising:

the substrate comprises a display area, a first signal access area, a second signal access area and a connection wiring area, wherein the first signal access area, the second signal access area and the connection wiring area are positioned at one side of the display area, which is far away from the first signal access area, and the connection wiring area is positioned between the first signal access area and the second signal access area;

at least one first voltage contact pad and at least one second voltage contact pad located at the first signal access region;

at least one third voltage contact pad and at least one fourth voltage contact pad located at the second signal access region;

At least one first connecting line and at least one second connecting line are positioned in the connecting wiring area; the at least one first connection line is electrically connected to the at least one first voltage contact pad and the at least one third voltage contact pad; the at least one second connection line is electrically connected to the at least one second voltage contact pad and the at least one fourth voltage contact pad;

the shortest distance between the first connection line and the adjacent second connection line is greater than 60 micrometers.

2. The display substrate of claim 1, wherein a shortest distance between the first connection line and the adjacent second connection line is greater than or equal to 90 microns and less than or equal to 120 microns.

3. A display substrate according to claim 1 or 2, wherein the voltage signal transmitted by the first connection line is greater than the voltage signal transmitted by the second connection line.

4. The display substrate of claim 1, wherein the display substrate further comprises: at least one second inactive contact pad located at the second signal access region, the at least one second inactive contact pad located between the at least one third voltage contact pad and the at least one fourth voltage contact pad.

5. The display substrate of claim 4, further comprising: the at least one first ineffective connecting wire is electrically connected with the at least one second ineffective contact pad, and the at least one first ineffective connecting wire is located between the at least one first connecting wire and the at least one second connecting wire.

6. The display substrate according to claim 5, wherein a second inactive contact pad is disposed between the at least one third voltage contact pad and the at least one fourth voltage contact pad, the second inactive contact pad being electrically connected to two of the first inactive connection lines, the two first inactive connection lines being located between the first connection lines and the second connection lines.

7. The display substrate of claim 4, further comprising: at least one first non-effective contact pad located at the first signal access region, the at least one first non-effective contact pad being located between the at least one first voltage contact pad and at least one second voltage contact pad.

8. The display substrate of claim 7, wherein the display substrate further comprises: at least one second inactive connection line electrically connected to the at least one first inactive contact pad and the at least one second inactive contact pad.

9. The display substrate according to claim 1, wherein a minimum line width of the first connection line is larger than a width of the connected first voltage contact pad, and a minimum line width of the second connection line is larger than a width of the connected second voltage contact pad.

10. The display substrate of claim 1, wherein the at least one first connection line and the at least one second connection line are located in different film layers.

11. The display substrate of claim 10, wherein the display area comprises: a plurality of sub-pixels, at least one of the plurality of sub-pixels including a pixel circuit and a light emitting element, the pixel circuit including at least one thin film transistor; the pixel circuit is electrically connected with the light-emitting element through a first switching electrode;

the at least one first connecting wire and the source electrode and the drain electrode of the thin film transistor are of the same-layer structure, and the at least one second connecting wire and the first switching electrode are of the same-layer structure;

or the at least one first connecting line and the first switching electrode are in the same layer structure, and the at least one second connecting line and the source electrode and the drain electrode of the thin film transistor are in the same layer structure.

12. The display substrate according to claim 1, wherein the at least one first connection line and the at least one second connection line are double-layered wirings.

13. The display substrate of claim 1, wherein the display area comprises: a plurality of sub-pixels, at least one of the plurality of sub-pixels including a pixel circuit and a light emitting element, the pixel circuit including at least one thin film transistor; the at least one first connecting wire and the at least one second connecting wire are of the same layer structure with the source electrode and the drain electrode of the thin film transistor;

the display substrate further includes: the first inorganic insulating layer is positioned in the connection wiring area, and the orthographic projection of the first inorganic insulating layer on the substrate covers the orthographic projection of the at least one first connection line and the at least one second connection line on the substrate.

14. The display substrate of claim 1, wherein the display area comprises: a plurality of sub-pixels, at least one of the plurality of sub-pixels including a pixel circuit and a light emitting element, the pixel circuit being electrically connected to the light emitting element through a first transfer electrode;

The display substrate further includes: a second flat layer on one side of the first transfer electrode away from the substrate, the second flat layer having at least a first region and a second region in a first frame region on one side of the display region, the thickness of the first region of the second flat layer being greater than the thickness of the second region of the second flat layer; the boundary position of the first area and the second area of the second flat layer is not overlapped with the orthographic projection of the at least one first connecting line and the at least one second connecting line on the substrate.

15. The display substrate of claim 14, wherein the display substrate further comprises: the integrated circuit is arranged in the first signal access area, the integrated circuit is electrically connected with the at least one first voltage contact pad and the at least one second voltage contact pad through the anisotropic conductive adhesive film, and the boundary of the anisotropic conductive adhesive film is positioned in the connection wiring area and is not overlapped with the boundary position of the first area and the second area of the second flat layer.

16. A display device comprising the display substrate according to any one of claims 1 to 15.