KR20200030005A - Electronic device - Google Patents

Abstract

Provided is an electronic device. The electronic device comprises a first signal line and a second signal line. The first signal line is arranged in the electronic device, and the first signal line includes at least a first section. The second signal line is arranged to be adjacent to the first signal line, and the second signal line includes at least a second section. An extension direction of the first section is different from an extension direction of the second section. In a plan view of the electronic device, the second section and the first section cross each other.

Description

Electronic device {ELECTRONIC DEVICE}

Cross reference to related applications

This application claims the benefit of U.S. Provisional Application No. 62 / 728,863 filed September 9, 2018 and Chinese Patent Application No. 201910241685.1 filed March 28, 2019, the entire contents of which are incorporated herein by reference.

The present disclosure relates to signal line construction techniques, particularly signal line construction techniques of electronic devices.

With the development of technology, the application of electronic devices is becoming more and more wide. Recently, when an electronic device is applied to a splice-type electronic device, space of each electronic device on the splicing side will be limited to reduce a frame window generated by splicing of two adjacent electronic devices. Accordingly, a method of properly aligning the electronic components and signal lines (data lines and / or scan lines) of each electronic device on the splicing side will be discussed.

In view of the above-mentioned problems, the present disclosure provides a signal line configuration technology of an electronic device.

The present disclosure discloses an electronic device including a first signal line and a second signal line. The first signal line is arranged in the electronic device and includes at least a first section. The second signal line is arranged adjacent to the first signal line and includes at least a second section. The first extension direction of the first section is different from the second extension direction of the second section. On the top view of the electronic device, the second section intersects the first section.

1A is a schematic diagram of a light emitting diode electronic device.
1B is a schematic diagram of a light emitting diode backlight electronic device.
2A is a schematic diagram of an electronic device 100 according to an embodiment of the present disclosure.
2B is a schematic diagram of an electronic device 100 according to another embodiment of the present disclosure.
3 is a schematic diagram of an electronic device 200 according to the embodiment of the present disclosure.
4 is a partial cross-sectional view of an electronic device 100 according to the embodiment of the present disclosure.
5A is a schematic diagram of a data line section disposed between scan lines according to the embodiment of the present disclosure.
5B is a schematic diagram of a data line section disposed between scan lines according to the embodiment of the present disclosure.
5C is a schematic diagram of a data line section disposed between scan lines according to the above embodiment of the present disclosure.

The present disclosure may be more fully understood by reading the following detailed description with reference to the accompanying drawings.

It should be understood that the drawings are not drawn to scale in accordance with industry standard practice. In practice, the size of the device can be arbitrarily enlarged or reduced for clarity.

Hereinafter, the term “about” generally means within 20%, preferably within 10%, and more preferably within 5% of a given value or range. The amounts given here are approximate numbers, meaning that the term "about" can be implied without specific explanation.

In some embodiments of the present disclosure, relative terms such as “bottom”, “top”, “horizontal”, “vertical”, “below”, “above”, etc., should be understood as the orientation expressed in the paragraphs and related schematics. This relative term is used for convenience of explanation, and does not mean that the device described herein must be manufactured or operated in a specific orientation. Unless otherwise defined, terms such as "connection", "bond" and "interconnect" are two structures in direct contact, or two structures are not in direct contact (indirect contact) and another structure is between the two structures. It can mean what is provided. The terms "connected" and "coupled" can also include cases where both structures are movable or both structures are fixed.

In particular, the term "signal line" used in embodiments of the present disclosure may refer to different types of signal lines, such as data lines, scan lines, power supply voltage (VDD) lines, shared signal lines (Vcom), etc. It is not limited to this. Further, the data line or the scan line is an example of the "signal line" in the embodiments of the present disclosure, but the present disclosure is not limited to this.

Embodiments of the present disclosure (as illustrated in FIG. 1A) can be applied to, but not limited to, a light emitting diode (LED) electronic device, or a light emitting diode backlight electronic device (as illustrated in FIG. 1B). Does not. In other embodiments, the LED may be an organic LED, an inorganic LED or a quantum dot LED, but is not limited to this. In other embodiments, the LED size may be a mini LED (minimeter size) or a micro LED (micrometer size), but is not limited to this. In another embodiment, the electronic device may be a display device, a sensing device, a tiled display device, or a tiled sensing device, but is not limited thereto. As illustrated in FIG. 1A, the light emitting diode electronic device 1 includes a plurality of pixels, a plurality of signal lines (a plurality of scan lines S ₁ , S ₂ , ..., S _N ) and a plurality of data lines D ₁ , D ₂ , ..., D _M )), a gate driving circuit G11, a gate driving circuit G12, and a control chip 10 (IC). Each pixel of the light emitting diode electronic device 1 may include at least one light emitting diode (LED). For example, as illustrated on the right side of FIG. 1A, the pixel P1 of the light emitting diode electronic device 1 may include three subpixels P11, P12 and P13, and the subpixels P11 and P12 And P13) may be included in the LED packet LP1. The sub-pixels P11, P12, and P13 may include light emitting diodes of different colors (a combination of red, green, blue, or white) or the same color (eg, red, green, blue, or white). In other embodiments, the LED may be an ultraviolet LED. In some embodiments, when the sub-pixels P11, P12, and P13 include light-emitting diodes of the same color, the color conversion layer is arranged to form three colors of red, green, and blue in the light emitting direction of the light-emitting diodes of the same color. The color conversion layer may be a color photoresist or a quantum dot conversion layer. This is an example, and the present disclosure is not limited to this. The structure of the light emitting diode may be a vertical structure or a horizontal structure of the light emitting diode. For example, when the light emitting diode has a vertical structure, the two electrodes of the light emitting diode are disposed on opposite sides and overlap at least partially on the top view (Z direction) of the light emitting diode electronic device. In contrast, when the light emitting diode has a horizontal structure, the two electrodes of the light emitting diode are disposed on the same side and do not overlap. The pixel design and structure of the light emitting diode described above can also be applied to subsequent LED backlight electronic devices and will not be described again. As illustrated in FIG. 1B, the LED backlight electronic device 2 includes a plurality of backlight units BLU, a plurality of signal lines (a plurality of scan lines S ₁₁ , S ₁₂ , ..., S _1k ) and a plurality of Scan line (including D ₁₁ , D ₁₂ , ..., D _1L ), a gate driving circuit G21, a gate driving circuit G22, and a control chip 20. Each backlight unit of the light emitting diode backlight electronic device 2 may include at least a light emitting diode. As illustrated on the right side of FIG. 1B, the backlight unit B1 of the LED backlight electronic device 2 may include three sub-pixels b11, b12 and b13, and corresponding sub-pixels b11, b12 and b13) is included in the LED packet LP2, but is not limited to this. In another embodiment, the backlight unit B1 may include a single sub-pixel, and the color of the sub-pixel may be white or another color suitable for the LED backlight electronic device 2. Also, as illustrated in FIGS. 1A and 1B, since the density of the LEDs disposed in the LED device is relatively high, the LED device may have a higher resolution than the LED backlight device. In some embodiments, on a plan view along the Z-axis, the pixel P1 of the LED device 1 has a cross-sectional area of about 1.5 mm * 1.5 mm, and the backlight unit B1 of the LED backlight device 2 is about 5 It has a cross section of mm * 5 mm. This is an example, and the present disclosure is not limited to this. In order to simplify the description in detail, the electronic device 100 has been described using an LED backlight electronic device as an example, but is not limited thereto. The control chip, data line, or scan line disclosed in the following embodiments can also be applied to an LED device.

Specifically, “section” described in an embodiment of the present disclosure means a portion of signal lines corresponding to different extension directions. For example, as illustrated in FIG. 2A, the data line D1 may include a data line section D11 extending in the Y-direction and a data line section D12 extending in the X-direction. It is not limited to. Further, in an embodiment of the present disclosure, the length of the “section” may be adjusted according to the size of other electronic devices. In some embodiments of the present disclosure, the lengths of sections extending in the same direction may be the same. In some embodiments of the present disclosure, the lengths of sections extending in different directions may be the same or different.

2A is a schematic diagram of an electronic device 100 according to an embodiment of the present disclosure. The electronic device 100 may be an LED backlight electronic device. As illustrated in FIG. 2A, the electronic device 100 includes a substrate 110, a plurality of backlight units 120_1 to 120_9, a plurality of data lines D1 (data line section D11 and data line section D12). Included), D2 (including data line section D21 and data line section D22) and D3 (including data line section D31 and data line section D32)), multiple scan lines (S1 to S3) ), A gate driving circuit (gate on panel (GOP) or scan line driving circuit) 130 and a control chip 140. The control chip 140 may be a timing controller (Tcon) or other suitable control chip. In some embodiments, the substrate 110 may include a non-flexible substrate or a flexible substrate. For example, the non-flexible substrate can include a glass substrate, a sapphire substrate, or other suitable substrate. The flexible substrate can include a ceramic substrate, a plastic substrate, or other suitable substrate. The material of the plastic substrate is polyimide (PI), polyethylene terephthalate (PET), polycarbonate (PC), polyethersulfone (PES), polybutylene terephthalate (PBT), polyethylene naphthalate (PEN), polyarylate (PAR), other suitable materials, or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, as illustrated in FIG. 2A, each backlight unit 120_1 to 120_9 may include light emitting diodes LED_1 to LED_9. In some embodiments, the LEDs (LED_1 to LED_9) may be, for example, organic light emitting diodes or inorganic light emitting diodes, such as quantum dot line emitting diodes (Q-LEDs), micro LEDs, or mini LEDs, but the disclosure It is not limited to this. In particular, the schematic diagram illustrated in FIG. 2A is for convenience of description of embodiments of the present disclosure. Although the number of backlight units, scan lines, data lines or other lines in FIG. 2A is partially illustrated, the present disclosure is not limited to this. Other components may also be included in the electronic device 100.

As illustrated in FIG. 2A, the substrate 110 has a display area 111 and a non-display area 112, where the non-display area 112 is disposed adjacent to the circumference of the display area 111. The backlight units 120_1 to 120_9, the data lines D1 to D3, and the scan lines S1 to S3 may be disposed in the display area 111. In addition, in some embodiments, the minimum length d1 between the outer edge 112-1 of the non-display area 112 and the display area 111 corresponding to the first extension direction (eg, Y-direction) is zero. 2 is less than the minimum length d2 between the display area 111 and the other outer edge 112-2 of the non-display area 112 corresponding to the extension direction (e.g., X-direction), but this disclosure It is not limited to. In other words, in the above embodiment, the non-display area 112 has a larger space available in the boundary areas of the left and right sides (non-splicing), and two adjacent electronic devices on the upper and lower sides (splicing side). The boundary area of each non-display area 112 of 100 may be further reduced. However, in another embodiment of the present disclosure, the non-display area 112 may have a large space that can be utilized in the upper and lower boundary areas. In an embodiment of the present disclosure, the control chip 140 is disposed at a position where the boundary area of the non-display area 112 has a larger space. That is, in an embodiment of the present disclosure, regardless of whether the electronic device 100 is a horizontal electronic device or a vertical electronic device, the control chip 140 has a boundary area of the non-display area 112. ), The two electronic devices 100 adjacent to each other may have better splicing effects, because they are disposed at positions having a larger space according to the spatial configuration of the non-display area 112 of the Is not limited to this.

According to an embodiment of the present disclosure, when the non-display area 112 has a larger space in the left and right boundary areas, the control chip 140 is disposed on one of the left or right sides of the non-display area 112. . In addition, in the above embodiment, the control chip 140 may be disposed of the non-display area 112 according to a limitation between the configuration or mechanism of power distribution (eg, interference between the control chip 140 and the flexible printed circuit (FPC)). It may be disposed on the upper, middle or lower part of either the left or right side of the boundary area, but the present disclosure is not limited to this.

According to another embodiment of the present disclosure, when the non-display area 112 has a larger space in the boundary area of the upper and lower layers, the control chip 140 may have an upper side and a lower side of the non-display area 112. Is placed in one of them. In addition, in this embodiment, the control chip 140 may be disposed of the non-display area 112 according to a limitation between the configuration or mechanism of power distribution (eg, interference between the control chip 140 and the flexible printed circuit (FPC)). It may be disposed on the right, middle or left side of one of the upper side and the lower side of the boundary area, but the present disclosure is not limited to this.

According to an embodiment of the present disclosure, the control chip 140 may be mounted in a chip-on-film (COF) method or a chip-on-glass (COG) method, but the present disclosure is limited to this. no. The control chip 140 may be used to control different signals or to transfer data lines D1 to D3 and scan lines S1 to S3, respectively.

According to one embodiment of the present disclosure, data line D1 may include data line section D11 and data line section D12, and data line D2 may include data line section D21 and data line Section D22 may be included, and data line D3 may include data line section D31 and data line section D32. As illustrated in FIG. 2A, the data line section D12, the data line section D22, and the data line section D32 are each electrically connected to the control chip 140 and signal lines of the gate driving circuit 130 (GTO_S) is also electrically connected to the control chip 140. Further, the scan lines S1 to S3 are respectively electrically connected to the gate driving circuit 130.

In addition, as illustrated in FIG. 2A, when viewed in a plan view direction (Z-direction) of the electronic device 100, the data line section D11 includes a data line section D12, a data line section D22, and a data line Section D32 is intersected individually. The data line section D21 is individually intersected with the data line section D12, the data line section D22, and the data line section D32. The data line section D31 is individually intersected with the data line section D12, the data line section D22, and the data line section D32. The data line section D11 of the data line D1, the data line section D21 of the data line D2 and the data line section D31 of the data line D3 extend substantially in the Y-direction, and X- Are arranged sequentially in the direction. The data line section D11, the data line section D21, and the data line section D31 may have a wave shape, bent shape, mesh shape, or other suitable shape, but extend substantially in the Y-direction. Further, the data line section D12 of the data line D1, the data line section D22 of the data line D2 and the data line section D32 of the data line D3 extend substantially in the X-direction, They are arranged sequentially in the Y-direction. The data line section D12, the data line section D22, and the data line section D32 may have a wave shape, bent shape, mesh shape, or other suitable shape, but extend substantially in the X-direction.

The scan lines S1 to S3 extend substantially in the X-direction and are sequentially arranged in the Y-direction. The scan lines S1 to S3 may have a wave shape, a bent shape, a mesh shape, or other suitable shape, but still extend in the X-direction. The scan lines S1 to S3 intersect with the data line section D11, the data line section D21, and the data line section D31.

2B is a schematic diagram of an electronic device 100 according to another embodiment of the present disclosure. As illustrated in FIG. 2B, in another embodiment, the data lines D1 to D3 may be replaced with scan lines S1 to S3. That is, as illustrated in FIG. 2B, the scan line S1 may include scan line sections S11 and S12, and the scan line S2 may include scan line sections S21 and S22, The scan line S3 may include scan line sections S31 and S32. When viewed in the plan view direction (Z-direction) of the electronic device 100, the scan line section S11 is individually intersected with the scan line section S12, the scan line section S22 and the scan line section S32. The scan line section S21 is individually intersected with the scan line section S12, the scan line section S22 and the scan line section S32. The scan line section S31 is individually intersected with the scan line section S12, the scan line section S22 and the scan line section S32. The scan line section S11 of the scan line S1, the scan line section S21 of the scan line S2 and the scan line section S31 of the scan line S3 extend substantially in the Y-direction, X- Are arranged sequentially in the direction. The scan line section S11, the scan line section S21 and the scan line section S31 may have a wave shape, bent shape, mesh shape or other suitable shape, but still extend in the Y-direction. Further, the scan line section S12 of the scan line S1, the scan line section S22 of the scan line S2 and the scan line section S32 of the scan line S3 extend substantially in the X-direction, They are arranged sequentially in the Y-direction. The scan line section S12, the scan line section S22 and the scan line section S32 may have a wave shape, bent shape, mesh shape or other suitable shape, but still extend in the X-direction. Further, the data lines D1 to D3 extend substantially in the X-direction and are sequentially arranged in the Y-direction. The data lines D1 to D3 may have a wave shape, a bent shape, a mesh shape, or other suitable shape, but still extend in the X-direction. The data lines D1 to D3 intersect with the scan line section S11, the scan line section S21, and the scan line section S31. It should be noted that the arrangement of the gate driving circuit 130 and the control chip 140 is similar to that illustrated in FIG. 2A, so that it will not be repeated in FIG. 2B.

According to an embodiment of the present disclosure, a plurality of control chips may be disposed in the electronic device, which will be described later with reference to FIG. 3. 3 is a schematic diagram of an electronic device 200 according to an embodiment of the present disclosure. As illustrated in FIG. 3, the electronic device 200 includes a display area 211, a non-display area 212, two gate driving circuits 230-1 and 230-2, a control chip 240-1, Control chip 240-2, control chip 240-3, multiple data line sections extending in the Y-direction 250-1, 250-2, ..., 250-P, multiple data line sections (270, 280, 290) and a plurality of scan lines (260-1, 260-2, ..., 260-Q). As illustrated in FIG. 3, in the above embodiment, each data line may include two sections. The control chip 240-1 can control the plurality of data line sections 270, the control chip 240-2 can control the plurality of data line sections 280, and the control chip 240-3 ) May control a plurality of data line sections 290. In addition, in this embodiment, the control chips 240-1, 240-2, and 240-3 may also be disposed at positions having a larger space in the boundary area of the non-display area 212 of the electronic device 200. have. Although the schematic diagram illustrated in FIG. 3 is for convenience of description of embodiments of the present disclosure, it should be understood that the present disclosure is not limited to this. Further, other methods for constructing the signal line section disclosed in the embodiments of the present disclosure can also be applied to the present embodiment. In addition, FIG. 3 is mainly used to describe an embodiment having a plurality of control chips. Therefore, other components of the electronic device 200 may be referred to FIG. 2A and will not be described again in FIG. 3. Further, there may be different intervals between the data line sections 250-1, 250-2, ..., 250-P illustrated in FIG. 3, but the present disclosure is not limited to this. In other embodiments, the spacing between data line sections 250-1, 250-2, ..., 250-P may be substantially the same.

4 is a partial cross-sectional view of an electronic device 100 according to an embodiment of the present disclosure. Although the sectional view illustrated in FIG. 4 is for describing an embodiment of the present disclosure, it should be understood that the present disclosure is not limited to this. The structure of the other layers will also be included in the cross-sectional view of the electronic device 100. According to an embodiment of the present disclosure, as illustrated in FIG. 4, the first metal layer 410 is disposed in the electronic device 100. The first metal layer 410 includes data line sections (eg, data line sections D11 of the data lines D1), data line sections D21 and the data lines of the data lines D2 sequentially arranged in the Y-direction ( D3) is patterned to form the data line section D31 (eg, but not limited to, through lithography, etching, etc.), but the present disclosure is not limited to this. Then, an insulating layer is disposed on the first metal layer 410. The insulating layer 420 may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or a combination of silicon oxide (SiOx) and silicon nitride (SiNx), but the present disclosure is not limited thereto. Subsequently, a plurality of through holes H (eg, H1, H2 and H3 illustrated in FIG. 2A) are formed in the insulating layer 420 through a patterning process, and the second metal layer 430 is formed on the insulating layer 420. By the deposition, the first metal layer 410 may contact the second metal layer 430 by filling the second metal layer 430 in the through hole. The second metal layer 430 includes data line sections (eg, data line sections D12 of the data lines D1) sequentially arranged in the X-direction, data line sections D22 of the data lines D2, and data lines ( D3) is patterned to form the data line section D32 (eg, but not limited to, through lithography, etching, etc.), but the present disclosure is not limited to this. The data line section of the first metal layer 410 is electrically connected to the data line section of the second metal layer 430 through a through hole. For example, the data line section D11 of the data line D1 may be electrically connected to the data line section D12 of the data line D1 through the through hole H1, and the data of the data line D2 The line section D21 may be electrically connected to the data line section D22 of the data line D2 through the through hole H2, and the data line section D31 of the data line D3 may be through hole H3. Through it may be electrically connected to the data line section (D32) of the data line (D3). therefore. The signal of the data line section D11 may be transmitted to the data line section D12, the signal of the data line section D21 may be transmitted to the data line section D22, and the signal of the data line section D31 May be transmitted to the data line section D32. In this embodiment, the first metal layer 410 and the second metal layer 430 may include conductive materials such as metal, alloy, metal oxide, metal oxynitride, or other suitable material. Further, in some embodiments, the first metal layer 410 or the second metal layer 430 may be at least two or more conductive layers. For example, in the cross-sectional direction (Z-direction), when the first metal layer 410 or the second metal layer 430 has a three-layer structure, the material used is molybdenum / aluminum / molybdenum or titanium from bottom to top. It can be / copper / titanium. In some embodiments, the first metal layer 410 and the second metal layer 430 may be a single conductive layer.

According to an embodiment of the present disclosure, data line sections (eg, data line section D12 of data line D1) sequentially arranged in the Y-direction, data line section D22 of data line D2, and The data line section D32 of the data line D3 may be evenly arranged at intervals between scan lines. According to another embodiment of the present disclosure, data line sections sequentially arranged in the Y-direction (eg, data line section D12 of data line D1, data line section D22 of data line D2), and The data line section D32 of the data line D3 may be randomly arranged at intervals between scan lines. The following paragraphs will be explained by FIGS. 5A-5C. Although the method of configuring the data line segments illustrated in FIGS. 5A-5C is for describing some embodiments of the present disclosure, it should be understood that the present disclosure is not limited to this. In some embodiments, a method of constructing a data line section may include a control chip (to reduce border edges formed by splicing of each non-display area 112 of two adjacent electronic devices 100). 140) or other manufacturing requirements.

5A is a schematic diagram of a data line section disposed between scan lines in accordance with an embodiment of the present disclosure. As illustrated in FIG. 5A, the display area 511 of the electronic device has backlight units B ₁ to B ₄₅ , 45 scan lines scan_01 to scan_45, and 160 data line sections data_001 to data_160. That is, the scan lines scan_01 to scan_45 have 44 intervals (space separation) to form 160 data line sections (data_001 to data_160). If it is determined to set the data line sections (data_001 to data_160) in the middle and place the four data line sections at one interval as illustrated in FIG. 5A, 160 data line sections (data_001 to data_160) are four data lines The sections can be evenly arranged at intervals between scan lines scan_03 to scan_43, but the present disclosure is not limited to this. In one embodiment, setting in the middle means that the control chip 140 is disposed at a position in the Y-direction about half of the non-display area 112 of the electronic device 100.

5B is a schematic diagram of a data line section disposed between scan lines according to another embodiment of the present disclosure. As illustrated in FIG. 5B, the display area 511 of the electronic device has backlight units B ₁ to B ₄₅ , 45 scan lines scan_01 to scan_45, and 160 data line sections data_001 to data_160. That is, the scan lines scan_01 to scan_45 have 44 intervals (space separation) to form 160 data line sections (data_001 to data_160). When data line sections (data_001 to data_160) are set in the middle and it is determined to configure eight data line sections at one interval as illustrated in FIG. 5B, 160 data line sections (data_001 to data_160) are eight. Data line sections can be evenly arranged at intervals between scan lines scan_13 to scan_33, but the present disclosure is not limited to this.

5C is a schematic diagram of a data line section disposed between scan lines according to another embodiment of the present disclosure. As illustrated in FIG. 5C, the display area 511 of the electronic device has backlight units B ₁ to B ₄₅ , 45 scan lines scan_01 to scan_45, and 160 data line sections data_001 to data_160. That is, the scan lines scan_01 to scan_45 have 44 intervals (space separation) to form 160 data line sections (data_001 to data_160). When the data line sections (data_001 to data_160) are set in the middle and it is determined to configure 12 data line sections at one interval as illustrated in FIG. 5C, the data line sections (data_001 to data_002) are the scan lines (scan_15) ~ scan_16), and scan lines scan_15 to scan_16 may be configured to scan lines scan_29 to scan_30. The remaining data line sections may be evenly arranged at intervals between scan lines (scan_16 to scan_29) by 12 data line sections, but the present disclosure is not limited to this.

In the above embodiment of the present disclosure, it should be noted that the data lines are arranged at intervals of scan lines as examples, but the present disclosure is not limited to this. That is, in another embodiment of the present disclosure, each scan line may include two scan line sections, and the scan line sections may be arranged at intervals of data lines.

According to some embodiments of the present disclosure, the control chip of the electronic device may be disposed at a position where the non-display area has a larger space. Further, according to some embodiments of the present disclosure, the data line or the scan line may be composed of two sections according to configuration requirements, and the sections connecting the control chips may be arranged at intervals of the data lines or scan lines. . Accordingly, according to some embodiments of the present disclosure, the space of the boundary area of the non-display area of the electronic device can be effectively used and / or the area occupied by the trace of the signal line can also be reduced.

As used herein, "an embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure, but the feature, It does not mean that the structure or properties are present in all examples. Thus, the expressions “in one embodiment” or “in some embodiments” as used in the specification are not necessarily referring to the same embodiment of the present disclosure.

Ordinal numbers such as “first”, “second”, “third”, and the like in the specification and claims of the present disclosure are not sequential, and are only for distinguishing two different devices of the same name. In the context of the present disclosure, the term "bond" refers to any kind of direct or indirect electronic connection. Although the present disclosure is disclosed in preferred embodiments as described above, the breadth and scope of the disclosure should not be limited by any of the embodiments described above. Those skilled in the art can make small changes and modifications without departing from the spirit and scope of the present disclosure. The scope of the present disclosure should be defined in accordance with the following claims and their equivalents.

Claims (20)

As an electronic device:
A first signal line having a first section extending in a first direction; And
A second signal line adjacent to the first signal line and having a second section extending in a second direction different from the first direction
Including,
When viewed from a top view of the electronic device, the second section intersects the first section. The electronic device of claim 1, wherein the first signal line and the second signal line are data lines, or the first signal line and the second line are scan lines. According to claim 1,
Display area; And
Non-display area adjacent to the display area
Further comprising,
A first minimum length between the outer edge of the non-display area and the display area is shorter than a second minimum length between the other outer edge of the non-display area and the display area;
The electronic device of claim 1, wherein a first extending direction of the outer edge is parallel to the second direction, and a second extending direction of the other outer edge is parallel to the first direction. 4. The electronic device of claim 3, further comprising a control chip electrically connected to the second section. The electronic device of claim 4, wherein the control chip is adjacent to the other outer edge and is disposed in the non-display area. The electronic device of claim 1, wherein the first signal line further comprises a third section extending in the second direction, and the third section intersects the first section. The method of claim 6, further comprising a first metal layer, a second metal layer and an insulating layer disposed between the first metal layer and the second metal layer, the first section is included in the first metal layer, the third Electronic device, characterized in that the section is included in the second metal layer. The electronic device of claim 7, wherein the insulating layer includes a through hole, and the first section is electrically connected to the third section through the through hole. The method of claim 6,
A third signal line extending in the second direction and traversing the first section; And
A fourth signal line extending in the second direction, adjacent to the third signal line, and traversing the first section
Including,
And the second section and the third section are arranged between the third signal line and the fourth signal line. The method of claim 9,
A fifth signal line extending in the second direction, adjacent to the fourth signal line, and crossing the first section;
A plurality of first sections are disposed between the third signal line and the fourth signal line, and a plurality of second sections are disposed between the fourth signal line and the fifth signal line;
The number of the first sections of the electronic device is different from the number of the plurality of second sections. The electronic device according to claim 1, wherein the electronic device is a landscape electronic device or a portrait electronic device. The electronic device of claim 4, wherein the control chip is disposed at a position where the non-display area has a larger space. 5. The electronic device according to claim 4, wherein the control chip is a timing controller (Tcon). The electronic device of claim 4, wherein the control chip is mounted in a chip-on-film (COF) method or a chip-on-glass (COG) method. 5. The electronic device of claim 4, wherein the control chip is configured to transmit different signals to the first signal line and the second signal line. The electronic device of claim 3, wherein a plurality of backlight units, a plurality of data lines, and a plurality of scan lines are disposed in the display area. The electronic device according to claim 8, wherein the second metal layer is formed on the insulating layer, and the first metal layer contacts the second metal layer by filling the second metal layer in the through hole. The electronic device of claim 7, wherein the insulating layer is formed of silicon oxide (SiOx), silicon nitride (SiNx), or a combination of silicon oxide (SiOx) and silicon nitride (SiNx). The electronic device according to claim 7, wherein the first metal layer or the second metal layer is a single layer or a multi-layer conductive layer. The first metal layer or the second metal layer has a three-layer structure, and the three-layer structure is an alternating layer of molybdenum, aluminum, and molybdenum from the bottom of the first metal layer or the second metal layer to the top. An electronic device formed or formed of alternating layers of titanium, copper, and titanium.

Images