TWI722908B - Pixel array substrate - Google Patents

Abstract

A pixel array substrate including a substrate, a first hole, a second hole, a first conductive pattern, a second conductive pattern, at least one signal line and at least one auxiliary pattern is provided. The substrate has a first surface and a second surface opposite to each other. The first hole and the second hole respectively penetrate the first surface and the second surface. The first conductive pattern and the second conductive pattern are disposed on one side of the first surface of the substrate. The at least one signal line is disposed on one side of the second surface of the substrate. The first conductive pattern and the second conductive pattern are electrically connected to the at least one signal line via the first hole and the second hole, respectively. The at least one auxiliary pattern is overlapped with a virtual connection between the first hole and the second hole.

Description

Pixel array substrate

The present invention relates to a circuit substrate, and particularly relates to a pixel array substrate.

In recent years, light-emitting diode displays, such as organic light-emitting diode (OLED) displays or micro light-emitting diode (micro-LED) displays, have high color saturation The advantages of high-end electronic products, such as high-end electronic products, such as high-speed, fast response speed, and high contrast, have sharply increased the market stereotypes of high-end electronic products. On the other hand, because the appearance of light-emitting diode displays is lighter and thinner than traditional liquid crystal displays, and its excellent flexibility can meet diversified display applications, such as curved displays, rollable TV walls, or electronics Paper and other applications.

In order to achieve a narrow border (or no border) design and ultra-high-resolution display screen, when the pixel circuit density increases, the peripheral circuits are arranged in the pixel area, which will inevitably further cause the display area to be used for The layout space of the configuration circuit is insufficient. In order to improve the above-mentioned problems, it is one of the more common solutions to dispose the circuits of the pixel array substrate on opposite sides of the substrate and electrically connect to each other through a plurality of micro-holes in the substrate. However, the presence of these micro-holes will cause the stiffness and flexibility of the substrate to deteriorate.

The present invention provides a pixel array substrate with holes, which has better stiffness and flexibility.

The pixel array substrate of the present invention includes a substrate, a first hole, a second hole, a first conductive pattern, a second conductive pattern, at least one signal line, and at least one auxiliary pattern. The substrate has a first surface and a second surface opposite to each other. The first hole and the second hole respectively penetrate the first surface and the second surface. The first conductive pattern and the second conductive pattern are disposed on one side of the first surface of the substrate. At least one signal line is arranged on one side of the second surface of the substrate. The first conductive pattern and the second conductive pattern are electrically connected to at least one signal line through the first hole and the second hole, respectively. At least one auxiliary pattern is overlapped and arranged on the virtual line between the first hole and the second hole.

Based on the above, in the pixel array substrate of an embodiment of the present invention, the electrical connection relationship between the plurality of conductive patterns on opposite sides of the substrate and the plurality of signal lines is realized through a plurality of holes penetrating the substrate. When the pixel array substrate is flexed, the auxiliary patterns provided on the virtual lines of the holes can prevent the stress from being concentrated between the holes and causing cracks in the nearby film. In other words, the stiffness of the substrate near the edge of the hole can be increased, thereby improving the flexibility resistance of the pixel array substrate.

As used herein, "approximately", "approximately", "essentially", or "substantially" includes the stated value and the average value within the acceptable deviation range of the specific value determined by a person of ordinary skill in the art, taking into account all The measurement in question and the specific number of errors associated with the measurement (ie, the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or, for example, within ±30%, ±20%, ±15%, ±10%, ±5%. Furthermore, "about", "approximately", "essentially", or "substantially" used in this article can be based on measurement properties, cutting properties, or other properties to select a more acceptable deviation range or standard deviation. Not one standard deviation applies to all properties.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connection" can refer to physical and/or electrical connection. Furthermore, "electrical connection" can mean that there are other components between the two components.

In addition, relative terms such as "lower" or "bottom" and "upper" or "top" can be used herein to describe the relationship between one element and another element, as shown in the figure. It should be understood that relative terms are intended to include different orientations of the device in addition to the orientation shown in the figures. For example, if the device in one figure is turned over, elements described as being on the "lower" side of other elements will be oriented on the "upper" side of the other elements. Therefore, the exemplary term "lower" may include an orientation of "lower" and "upper," depending on the specific orientation of the drawing. Similarly, if the device in one figure is turned over, elements described as "below" or "below" other elements will be oriented "above" the other elements. Thus, the exemplary terms "above" or "below" can include an orientation of above and below.

Reference will now be made in detail to the exemplary embodiments of the present invention, and examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and descriptions to indicate the same or similar parts.

FIG. 1 is a schematic top view of a pixel array substrate according to a first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of the pixel array substrate of FIG. 1. In particular, for the sake of clarity, FIG. 1 omits the insulating layer 110, gate insulating layer 120, interlayer insulating layer 130, flat layer 140, active device T, connection pad BP1, connection pad BP2, and light emitting device of FIG. 2 in FIG. The drawing of the LED, and the signal line SL1 and the signal line SL2 in FIG.

1 and 2, the pixel array substrate 10 includes a substrate 100, a plurality of conductive patterns, a plurality of signal lines, and a plurality of holes. The substrate 100 has a first surface 100a and a second surface 100b opposite to each other. The conductive patterns are arranged on the side of the first surface 100 a of the substrate 100, and the signal lines are arranged on the side of the second surface 100 b of the substrate 100. More specifically, in order to increase the layout space of the pixel array substrate 10 for disposing circuits, the signal lines, peripheral traces, and pixel drive circuits are scattered on opposite sides of the substrate 100 and pass through the substrate 100. These holes are used to realize the electrical connection between these circuits.

In this embodiment, the substrate 100 may be a hard substrate, and its material includes glass or quartz, but it is not limited thereto. In other embodiments, the substrate 100 may also be a soft substrate (that is, a flexible substrate), and its material includes polyimide, polyethylene terephthalate (PET), and polyisophthalate. Polyethylene naphthalate (PEN), polyethersulfone (PES), polymethyl methacrylate (PMMA), polycarbonate (PC), or other suitable polymer polymerization Things.

Furthermore, the conductive patterns of the pixel array substrate 10 include a plurality of conductive patterns CP1 and a plurality of conductive patterns CP2, and the conductive patterns CP1 and the conductive patterns CP2 belong to different film layers. These conductive patterns CP1 (or conductive patterns CP2) are arranged in multiple columns and multiple rows in the direction X and the direction Y, respectively, and are structurally separated from each other. It is worth noting that a plurality of holes of the pixel array substrate 10 are respectively provided corresponding to these conductive patterns. For example, the hole H1 and the hole H2 of the pixel array substrate 10 respectively overlap the conductive pattern CP11 and the conductive pattern CP12 in the direction Z, and the hole H3 and the hole H4 of the pixel array substrate 10 overlap the conductive pattern respectively in the direction Z. The pattern CP21 and the conductive pattern CP22. In this embodiment, the holes of the pixel array substrate 10 can be formed by laser drilling, etching, mechanical drilling, or other precision processing methods, but Not limited to this.

In this embodiment, the multiple signal lines of the pixel array substrate 10 may include multiple signal lines SL1 and multiple signal lines SL2. These signal lines SL1 are arranged along the direction Y and extend in the direction X. These signal lines SL2 are arranged along the direction X and extend in the direction Y. More specifically, the signal lines SL1 intersect with the signal lines SL2. For example, in this embodiment, the signal line SL1 can be a scan line, and the signal line SL2 can be a power line for transmitting a voltage source (such as Vdd), but it is not limited to this. . In other embodiments, the signal line SL1 and the signal line SL2 can also be selected from data lines, sensing lines, or reset lines, respectively. In order to ensure the electrical independence of the signal line SL1 and the signal line SL2, the pixel array substrate 10 further includes an insulating layer 110 on the side of the second surface 100b of the substrate 100, and the insulating layer 110 is disposed on the signal line SL1 and the signal line Between SL2.

In this embodiment, the conductive patterns CP1 (for example, the conductive pattern CP11 and the conductive pattern CP12) are respectively arranged on the extension paths of the signal lines SL1, and the conductive patterns CP2 (for example, the conductive pattern CP21 and the conductive pattern CP22) are respectively arranged on these On the extension path of the signal line SL2. It is worth noting that the holes (for example, holes H1 and H2) overlapping the conductive pattern CP1 are also arranged on the extension path of a corresponding signal line SL1, and the holes (for example, the holes H3 and the holes H4) overlapping the conductive pattern CP2 are also arranged on the extension path of the corresponding signal line SL1. Set on the extension path of a corresponding signal line SL2. For example, the conductive pattern CP11 and the conductive pattern CP12 on the first surface 100a of the substrate 100 are electrically connected to the same signal line SL1 on the second surface 100b of the substrate 100 through the holes H1 and H2, and are located on the substrate The conductive pattern CP21 and the conductive pattern CP22 on the first surface 100a of the substrate 100 are electrically connected to the two signal lines SL2 on the second surface 100b of the substrate 100 via the hole H3 and the hole H4, respectively.

The pixel array substrate 10 further includes a plurality of pixel structures PX. For example, the multiple signal lines SL1 and the multiple signal lines SL2 can define multiple pixel regions, and the pixel structures PX are respectively disposed in the pixel regions, but it is not limited thereto. The pixel structure PX includes an active device T and a light emitting device LED that are electrically connected to each other. In this embodiment, the method of forming the active device T may include the following steps: forming a semiconductor pattern SC, a gate insulating layer 120, a gate electrode G, an interlayer insulating layer 130, and a source electrode S on the first surface 100a of the substrate 100 in sequence. And the drain D, where the semiconductor pattern SC includes a source region SR, a drain region DR, and a channel region CH. The source electrode S and the drain electrode D penetrate the interlayer insulating layer 130 and the gate insulating layer 120 to respectively electrically connect the source region SR and the drain region DR of the semiconductor pattern SC, and the other end of the source electrode S is connected to the conductive pattern CP21.

In this embodiment, the gate G of the active device T can be selectively disposed above the semiconductor pattern SC to form a top-gate TFT, but the invention is not limited to this. According to other embodiments, the gate G of the active device can also be arranged under the semiconductor pattern SC to form a bottom-gate TFT. On the other hand, the material of the semiconductor pattern SC is, for example, a polysilicon semiconductor material, that is, the active device T may be a low temperature polysilicon thin film transistor (LTPS TFT). However, the present invention is not limited to this. In other embodiments, the active device may also be an amorphous silicon thin film transistor (a-Si TFT), a micro-Si thin film transistor (micro-Si TFT), or a metal oxide. Material Transistor (Metal Oxide Transistor).

After the step of forming the active device T is completed, a flat layer 140, a connection pad BP1 and a connection pad BP2 are sequentially formed on the interlayer insulating layer 130, the source electrode S and the drain electrode D. The connection pad BP1 penetrates the flat layer 140 for electrical conductivity. Connect the drain D of the active device T. The connection pad BP1 and the connection pad BP2 are used for receiving the light-emitting element LED, and the light-emitting element LED is electrically connected to the pixel circuit layer on the substrate 100 via these connection pads. In this embodiment, the light emitting element LED may include an epitaxial structure ES, a first electrode E1 and a second electrode E2, and the first electrode E1 and the second electrode E2 are located on the same side of the epitaxial structure ES. That is to say, the light-emitting element LED of this embodiment may be a flip-chip type light-emitting diode, but the invention is not limited to this. In other embodiments, the light-emitting element may also be a lateral type light-emitting diode or a vertical type light-emitting diode.

It should be noted that the gate G, the source S, the drain D, the insulating layer 110, the gate insulating layer 120, the interlayer insulating layer 130, the planarization layer 140, and the connection pads are respectively known to those with ordinary knowledge in any technical field. Any gate, any source, any drain, any insulating layer, any gate insulating layer, any interlayer insulating layer, any flat layer, and any connecting pad for the display panel, And the gate G, the source S, the drain D, the insulating layer 110, the gate insulating layer 120, the interlayer insulating layer 130, the planarization layer 140, and the connection pads can be used by any person with ordinary knowledge in the art. It is formed by one method, so it will not be repeated here.

Furthermore, the pixel array substrate 10 further includes a plurality of auxiliary patterns, and these auxiliary patterns are respectively arranged on the virtual connections of the plurality of holes. For example, these auxiliary patterns include auxiliary pattern AP1, auxiliary pattern AP2, and auxiliary pattern AP3. The auxiliary pattern AP1 is arranged on the virtual line CL1 between the hole H1 and the hole H2. The auxiliary pattern AP2 and the auxiliary pattern AP3 are arranged on the virtual line CL2 between the hole H3 and the hole H4. Accordingly, it can be avoided that when the pixel array substrate 10 is deflected, stress is concentrated between the holes, causing cracks in the nearby film layer (for example, the conductive layer or the insulating layer), causing electrical problems. In other words, by arranging at least one auxiliary pattern on the virtual connections of the holes, the stiffness of the substrate 100 near the edges of the holes can be increased, thereby improving the flexibility resistance of the pixel array substrate 10. From another point of view, through the setting of these auxiliary patterns, the accuracy of laser drilling can also be effectively improved. That is, the yield rate of the laser drilling process can be improved.

It should be noted that the virtual connection here is defined by the connection between the geometric centers of the two holes, but it is not limited to this. In other embodiments, the virtual line can also be defined by the line at any point on the respective edges of the two holes. Since the signal line SL1 in FIG. 1 roughly overlaps the geometric centers of the holes H1 and H2, the virtual connection CL1 between the holes H1 and the hole H2 in FIG. 1 should overlap the signal line SL1. However, for the sake of clarity, the virtual connection CL1 is shown slightly deviating from the signal line SL1.

In this embodiment, the auxiliary pattern AP1, the gate G, the conductive pattern CP11, and the conductive pattern CP12 can selectively belong to the same film layer. The auxiliary pattern AP2, the auxiliary pattern AP3, the source S, the drain D, the conductive pattern CP21 and The conductive patterns CP22 can selectively belong to the same film layer, but it is not limited thereto. That is, the material of the auxiliary pattern may include metal materials, such as molybdenum, aluminum, copper, the above alloy, or a combination of the above, but it is not limited thereto. However, the present invention is not limited to this. According to other embodiments, in order to increase the ductility of the film layer between the multiple holes, the material of the auxiliary pattern may also be a polymer material with a small Young’s modulus.

In particular, these auxiliary patterns have floating potentials. That is to say, although the auxiliary patterns of this embodiment are made of conductive materials, they are not electrically connected to the driving circuit layer of the pixel array substrate 10 or any signal lines. This ensures that the pixel array substrate The electrical operation of 10 (or display) is not affected. On the other hand, in order to achieve the closest arrangement of display pixels, the extension direction of the auxiliary pattern can be selectively perpendicular to the extension direction of the virtual line between the holes. For example, in this embodiment, the extension direction of the auxiliary pattern AP1 (for example, the direction Y) can be perpendicular to the extension direction of the virtual line CL1 between the hole H1 and the hole H2, and the extension direction of the auxiliary pattern AP2 and the auxiliary pattern AP3 (for example, The direction Y) may be perpendicular to the extending direction of the virtual line CL2 between the hole H3 and the hole H4, but the present invention is not limited thereto.

Other embodiments will be listed below to describe the disclosure in detail, wherein the same components will be marked with the same symbols, and the description of the same technical content will be omitted. For the omitted parts, please refer to the foregoing embodiments, and will not be repeated hereafter.

FIG. 3 is a schematic top view of a pixel array substrate according to a second embodiment of the present invention. Please refer to FIG. 3, the difference between the pixel array substrate 11 of this embodiment and the pixel array substrate 10 of FIG. 1 is that the arrangement of auxiliary patterns is different. Specifically, the pixel array substrate 11 includes an auxiliary pattern AP11, an auxiliary pattern AP12, an auxiliary pattern AP21, and an auxiliary pattern AP22. The auxiliary pattern AP11 and the auxiliary pattern AP21 are arranged on the virtual line CL1 between the hole H1 and the hole H2, and the auxiliary pattern AP12 and the auxiliary pattern AP22 are arranged on the virtual line CL2 between the hole H3 and the hole H2.

It should be noted that by overlapping the auxiliary pattern AP21 and the auxiliary pattern AP22 on the auxiliary pattern AP11 and the auxiliary pattern AP12 respectively in the direction Z, the ductility of the film between these holes can be further increased. On the other hand, through the different extension directions of the two overlapping auxiliary patterns, the ductility of the film layer between the holes in different directions can be increased. For example, the auxiliary pattern AP11 and the auxiliary pattern AP21 arranged on the virtual line CL1 of the hole H1 and the hole H2 extend in the direction Y and the direction X, respectively, and the auxiliary pattern AP11 and the auxiliary pattern AP21 arranged on the virtual line CL2 of the hole H3 and the hole H4 The pattern AP12 and the auxiliary pattern AP22 extend in the direction X and the direction Y, respectively.

In this embodiment, the auxiliary pattern AP11, the auxiliary pattern AP12, and the conductive pattern CP1 can optionally be the same film layer, and the auxiliary pattern AP21, the auxiliary pattern AP22, and the conductive pattern CP2 can selectively be the same film layer, but not so. Is limited.

4 is a schematic top view of a pixel array substrate according to a third embodiment of the present invention. Referring to FIG. 4, the difference between the pixel array substrate 12 of this embodiment and the pixel array substrate 10 of FIG. 1 lies in the different arrangements of signal lines, conductive patterns, and auxiliary patterns. In this embodiment, in order to achieve the densest arrangement of the pixel structure, the extending direction of the plurality of signal lines SL1' is not perpendicular and not parallel to the plurality of signal lines SL2. For example, the signal lines SL1' are arranged along the direction Y'and extend in the direction X', and overlap in the direction Z with a plurality of conductive patterns CP1' and a plurality of holes (such as holes H1', holes H2') And the holes H5) are respectively arranged on the extension paths of the signal lines SL1'. On the other hand, different from the arrangement of the plurality of conductive patterns CP2 in FIG. 1, the plurality of conductive patterns CP2' of this embodiment are arranged in multiple strings in the direction Y, the direction X', and the direction Y', respectively.

Furthermore, the pixel array substrate 12 includes an auxiliary pattern AP1a, an auxiliary pattern AP1b and an auxiliary pattern AP1c on the same film layer, and an auxiliary pattern AP2' on another film layer. For example, the virtual line CL3 between the hole H1' and the hole H2' is provided with an auxiliary pattern AP1a, and the virtual line CL4 between the hole H1' and the hole H3' is provided with an auxiliary pattern AP1b and an auxiliary pattern AP2' that overlap each other. An auxiliary pattern AP1c is provided on the virtual line CL5 between the hole H1' and the hole H4'. Accordingly, when the pixel array substrate 12 is flexed, the stress concentrated between the holes can prevent the nearby film layer (such as the conductive layer or the insulating layer) from producing cracks, causing electrical problems. In other words, by arranging at least one auxiliary pattern on the virtual connections of these holes, the stiffness of the substrate 100 near the edges of the holes can be increased, thereby improving the flexibility resistance of the pixel array substrate 12.

In this embodiment, the auxiliary pattern AP1a, the auxiliary pattern AP1b, the auxiliary pattern AP1c, and the conductive pattern CP1' can optionally be the same film layer, and the auxiliary pattern AP2' and the conductive pattern CP2' can optionally be the same film layer, but Not limited to this.

FIG. 5 is a schematic top view of a pixel array substrate according to a fourth embodiment of the present invention. Referring to FIG. 5, the difference between the pixel array substrate 13 of this embodiment and the pixel array substrate 10 of FIG. 1 is that the projection contours of the auxiliary patterns on the substrate are different. In this embodiment, a plurality of auxiliary patterns of the pixel array substrate 13, such as the auxiliary pattern AP1", the auxiliary pattern AP2", the auxiliary pattern AP3" and the auxiliary pattern AP4, have a circular vertical projection outline on the substrate 100. Therefore, when the pixel array substrate 13 is flexed, it is possible to prevent stress from being concentrated on the corners of the auxiliary pattern AP1 as shown in FIG. 1 to cause damage to the auxiliary pattern AP1. From another point of view, through the auxiliary pattern having a circular outline The configuration can also increase the ductility of the film layer located between the multiple holes in all directions.

FIG. 6 is a schematic top view of a pixel array substrate according to a fifth embodiment of the present invention. Please refer to FIG. 6, the difference between the pixel array substrate 14 of this embodiment and the pixel array substrate 10 of FIG. 1 is that the projection contour of the auxiliary pattern on the substrate is different. In this embodiment, the multiple auxiliary patterns of the pixel array substrate 14, such as the auxiliary pattern AP1L, the auxiliary pattern AP1R, the auxiliary pattern AP2L, and the auxiliary pattern AP2R, have a vertical projection outline on the substrate 100 in a meniscus shape. It should be noted that the auxiliary pattern of this embodiment can be overlapped with multiple virtual lines of holes in different arrangement directions. For example, the auxiliary pattern AP1L overlaps the virtual lines of holes H1 and H2 in direction Z at the same time. CL1, the virtual line CL6 between the hole H2 and the hole H3, and the virtual line CL2 between the hole H3 and the hole H4. Accordingly, the ductility of the film layer between these holes can be increased. On the other hand, through the contour of the meniscus, it is also possible to avoid stress concentration on the corners of the auxiliary pattern AP1 as shown in FIG. 1 to cause damage to the auxiliary pattern AP1. In other words, the auxiliary pattern of this embodiment can have better bending resistance.

In this embodiment, the auxiliary pattern AP1L has a first extension AP1La and a second extension AP1Lb connected, and the extension direction of the first extension AP1La is different from the extension direction of the second extension AP1Lb. For example, when the substrate 100 is deflected along the direction X, the first extension AP1La of the auxiliary pattern AP1L provided on the virtual line CL1 between the hole H1 and the hole H2 can increase the film between the hole H1 and the hole H2 The ductility of the layer in the direction X; similarly, the second extension AP1Lb of the auxiliary pattern AP1L arranged on the virtual line CL2 between the hole H3 and the hole H4 can increase the film layer between the hole H3 and the hole H4 in the direction Extensibility on X. When the substrate 100 is deflected along the arrangement direction of the holes H2 and H3, the second extension AP1Lb provided on the virtual line CL6 between the holes H2 and the holes H3 can also increase the film layer between the holes H2 and H3. The ductility in the direction of flexure.

Similarly, the auxiliary pattern AP2L has a first extension AP2La and a second extension AP2Lb connected, and the extension direction of the first extension AP2La is different from the extension direction of the second extension AP2Lb. For example, when the substrate 100 is deflected along the direction X, the auxiliary pattern AP2L provided on the virtual line CL2 between the hole H3 and the hole H4 can increase the film layer between the hole H3 and the hole H4 in the direction X Malleability. When the substrate 100 is deflected along the arrangement direction of the holes H1 and H4, the first extension AP2La provided on the virtual line CL7 between the holes H1 and H4 can also increase the film layer between the holes H1 and H4. The ductility in the direction of flexure. When the substrate 100 is deflected along the arrangement direction of the holes H5 and H4, the second extension AP2Lb provided on the virtual line CL8 between the holes H5 and the holes H4 can also increase the film layer between the holes H5 and H4. The ductility in the direction of flexure.

Continuing the above, through the configuration of the auxiliary pattern with the meniscus profile, the film layer located between the multiple holes (such as the hole H1, the hole H2, the hole H3, the hole H4 and the hole H5) can be increased in multiple directions. Sex. In this embodiment, the opening directions of the meniscus contours of the auxiliary pattern AP1L and the auxiliary pattern AP1R arranged in the direction Y may be opposite to each other. For example, the opening direction of the auxiliary pattern AP1L is the opposite direction of the direction X, and the auxiliary pattern AP1R The direction of the opening is the direction X.

That is, the extension direction of the first extension AP1Ra of the auxiliary pattern AP1R is substantially parallel to the extension direction of the second extension AP1Lb of the auxiliary pattern AP1L, and the extension direction of the second extension AP1Rb of the auxiliary pattern AP1R is substantially parallel to the auxiliary pattern AP1R. The extension direction of the first extension AP1La of the pattern AP1L. Similarly, the extension direction of the first extension AP2Ra of the auxiliary pattern AP2R is substantially parallel to the extension direction of the second extension AP2Lb of the auxiliary pattern AP2L, and the extension direction of the second extension AP2Rb of the auxiliary pattern AP2R is substantially parallel to the auxiliary pattern. The extension direction of the first extension section AP2La of AP2L. However, the present invention is not limited to this. In other embodiments, the opening directions of all auxiliary patterns with a meniscus profile can also be set in the same direction.

FIG. 7 is a schematic top view of a pixel array substrate according to a sixth embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of the pixel array substrate of FIG. 7. Referring to FIGS. 7 and 8, the difference between the pixel array substrate 15 of this embodiment and the pixel array substrate 10 of FIG. 1 lies in the difference in the film layer and the arrangement of the auxiliary pattern. Specifically, the auxiliary pattern (for example, auxiliary pattern AP5 and auxiliary pattern AP6) of the pixel array substrate 15, the connection pad BP1 and the connection pad BP2 are the same film layer, and the auxiliary pattern AP5 overlaps the hole H1 and the hole H2 in the direction Z, And the auxiliary pattern AP6 overlaps the hole H3 and the hole H4 in the direction Z. In this embodiment, the auxiliary pattern extends in the direction X and overlaps two adjacently arranged holes, but the invention is not limited to this. In other embodiments, the auxiliary pattern may also extend in the arrangement direction of the hole H2 and the hole H4 and overlap the hole H2 and the hole H4 at the same time.

Through the overlapping relationship between the single auxiliary pattern and the multiple holes, the stiffness of the substrate 100 near the edge of the hole can be increased, thereby improving the flexibility resistance of the pixel array substrate 15.

FIG. 9 is a schematic top view of a pixel array substrate according to a seventh embodiment of the present invention. Please refer to FIG. 9, the difference between the pixel array substrate 16 of this embodiment and the pixel array substrate 10 of FIG. 1 is that the projection contour of the auxiliary pattern on the substrate is different. In this embodiment, a plurality of auxiliary patterns of the pixel array substrate 16, such as auxiliary pattern AP71, auxiliary pattern AP72, auxiliary pattern AP81, and auxiliary pattern AP82, are projected vertically on the substrate 100 to surround a plurality of holes, and these The vertical projection profile of the auxiliary pattern can be roughly divided into two categories.

For example, the vertical projection contours of the auxiliary pattern AP71 and the auxiliary pattern AP81 respectively surrounding the hole H2 and the hole H4 on the substrate 100 are continuous ring patterns, and the auxiliary pattern AP72 and the auxiliary pattern AP82 respectively surrounding the hole H6 and the hole H7 The vertical projection profile on the substrate 100 is a discontinuous ring pattern. In this embodiment, the auxiliary pattern AP72 has a first extension section AP72a and a second extension section AP72b that are structurally separated, and the recesses of the two extension sections are opposite to each other and face the surrounding hole H6. Similarly, the auxiliary pattern AP82 has a first extension AP82a and a second extension AP82b that are structurally separated, and the notches of the two extensions are opposite to each other and face the surrounding hole H7. It is worth mentioning that by surrounding the hole through the auxiliary pattern, the ductility of the film layer around the hole can be increased, thereby improving the flexibility resistance of the pixel array substrate 16.

In this embodiment, the film layer to which the auxiliary pattern AP71 and the auxiliary pattern AP72 belong is different from the film layer to which the conductive pattern CP1 or the conductive pattern CP2 belongs. On the contrary, the auxiliary pattern AP81, the auxiliary pattern AP82, and the conductive pattern CP1 can selectively belong to the same film layer, but it is not limited thereto. It should be noted that the present invention does not limit the types of outlines of the auxiliary patterns. In other embodiments, in order to further enhance the flexibility resistance of the pixel array substrate in all directions, the vertical projection outlines of all auxiliary patterns may also be used. All are continuous ring patterns.

FIG. 10 is a schematic top view of a pixel array substrate according to an eighth embodiment of the present invention. Please refer to FIG. 10, the difference between the pixel array substrate 17 of this embodiment and the pixel array substrate 10 of FIG. 1 is that the conductive patterns and the auxiliary patterns are arranged differently. In this embodiment, the conductive pattern CP1A of the pixel array substrate 17 does not overlap the conductive pattern CP2 in the direction Z, the conductive pattern CP2 is located on the virtual line CL9 between the hole H1" and the hole H2", and the auxiliary pattern AP9 is arranged on Between the conductive pattern CP1A and the conductive pattern CP2. By providing the auxiliary pattern AP9 between the signal line SL2 and the conductive pattern CP1A, the stiffness and flexibility of the substrate between the holes (especially the area between the holes and the adjacent signal lines) can be increased. In particular, the arrangement of the auxiliary pattern is not limited to the display area AA of the pixel array substrate 10, and the auxiliary pattern may also be provided in the peripheral area PA outside the display area AA.

In this embodiment, the pixel array substrate 17 may further include a plurality of peripheral wirings, such as peripheral wirings PL1 and peripheral wirings PL2, and part of the peripheral wirings passes through the holes and the signal lines on the other side of the substrate 100 ( Not shown) Electrical connection. For example, the peripheral wiring PL2 located in the peripheral area PA realizes the electrical connection relationship with the signal line on the other side of the substrate 100 through the hole H8. By providing the auxiliary pattern AP10 between the peripheral wiring PL1 and the peripheral wiring PL2, the stiffness and flexibility of the substrate between the hole H8 and the peripheral wiring PL1 can be increased.

FIG. 11 is a schematic top view of a pixel array substrate according to a ninth embodiment of the present invention. Referring to FIG. 11, the main difference between the pixel array substrate 17A of this embodiment and the pixel array substrate 10 of FIG. 1 is that the auxiliary pattern is arranged in a different manner. Specifically, the opposite sides of the conductive pattern CP2 of the pixel array substrate 17A are respectively provided with an auxiliary pattern AP91 and an auxiliary pattern AP92, and these auxiliary patterns are not provided on the virtual connections between the multiple holes (for example, the virtual connection CL1). )on. In other words, the auxiliary pattern AP91 and the auxiliary pattern AP92 are used to increase the stiffness and flexibility of the substrate around the signal trace (for example, the signal line SL2).

On the other hand, similar to the pixel array substrate 17 of FIG. 10, the auxiliary pattern of the pixel array substrate 17A can also be provided in the peripheral area PA to increase the stiffness and flexibility of the substrate between the peripheral traces. For example, the auxiliary pattern AP93 and the auxiliary pattern AP94 may also be provided on opposite sides of the peripheral wiring PL1. In this embodiment, the auxiliary pattern AP91, the auxiliary pattern AP92, the auxiliary pattern AP93, the auxiliary pattern AP94 and the conductive pattern CP1 can selectively belong to the same film layer, but it is not limited thereto.

FIG. 12 is a schematic top view of a pixel array substrate according to a tenth embodiment of the present invention. FIG. 13 is a schematic top view of the pixel array substrate of FIG. 12. In particular, for the sake of clarity, FIG. 12 omits the insulating layer 110, the gate insulating layer 120, the interlayer insulating layer 130, the flat layer 140, the active device T, the connection pad BP1, the connection pad BP2', and the light emitting device of FIG. The drawing of the element LED, and the signal line SL2 and the signal line SL3 of FIG. 12 are presented in the form of dashed lines.

12 and FIG. 13, the difference between the pixel array substrate 18 of this embodiment and the pixel array substrate 10 of FIG. 1 and FIG. 2 lies in the different arrangement of signal lines. Specifically, a part of the plurality of signal lines of the pixel array substrate 18 may be disposed on one side of the first surface 100 a of the substrate 100. For example, a plurality of signal lines SL1" used to drive the gate G of the active device T are disposed on the first surface 100a of the substrate 100, and these signal lines SL1" and the gate G of the active device T belong to the same film Floor. Therefore, the pixel array substrate 18 does not need to be provided with the conductive pattern CP1 of FIG. 1 and the holes (such as the holes H1 and the holes H2) overlapping the conductive pattern CP1.

In this embodiment, the pixel array substrate 18 may further include a plurality of signal lines SL3, which are disposed on one side of the second surface 100b of the substrate 100. The signal line SL3 and the signal line SL2 are alternately arranged in the direction X. The signal line SL3 is electrically connected to the connection pad BP2' through the hole H9. More specifically, the signal line SL3 may be a power line for transmitting a voltage source (for example, Vss). It should be noted that the signal line SL2' and the signal line SL3 do not overlap the conductive pattern (for example, the conductive pattern CP2) and the auxiliary pattern (for example, the auxiliary pattern AP2 and the auxiliary pattern AP3) in the direction Z. Accordingly, when the pixel array substrate 18 is deflected, the generated stress can be evenly dispersed on the opposite sides of the substrate 100 (that is, the two sides of the first surface 100a and the second surface 100b), which helps increase the substrate Stiffness and flexibility.

FIG. 14 is a schematic top view of a pixel array substrate according to an eleventh embodiment of the present invention. Please refer to FIG. 14, the difference between the pixel array substrate 19 of this embodiment and the pixel array substrate 17 of FIG. 10 is that the signal lines are arranged differently. In this embodiment, the signal line SL1A and the signal line SL2' of the pixel array substrate 19 do not overlap the conductive patterns (such as the conductive patterns CP1A and the conductive patterns CP2) and the auxiliary patterns (such as the auxiliary patterns AP2 and the auxiliary patterns in the direction Z). AP3 and auxiliary pattern AP9). Accordingly, when the pixel array substrate 19 is deflected, the generated stress can be evenly dispersed on the opposite sides of the substrate 100 (that is, the two sides of the first surface 100a and the second surface 100b), which helps increase the substrate’s Stiffness and flexibility.

In summary, in the pixel array substrate of an embodiment of the present invention, the electrical connection relationship between the plurality of conductive patterns on the opposite sides of the substrate and the plurality of signal lines is achieved through a plurality of holes penetrating the substrate. When the pixel array substrate is flexed, the auxiliary patterns provided on the virtual lines of the holes can prevent the stress from being concentrated between the holes and causing cracks in the nearby film. In other words, the stiffness of the substrate near the edge of the hole can be increased, thereby improving the flexibility resistance of the pixel array substrate.

10, 11, 12, 13, 14, 15, 16, 17, 17A, 18, 19: pixel array substrate 100: substrate 100a: first surface 100b: second surface 110: Insulation layer 120: gate insulation 130: Interlayer insulation 140: flat layer AA: Display area AP1, AP1", AP1a, AP1b, AP1c, AP11, AP12, AP1L, AP1R, AP2, AP2', AP2", AP21, AP22, AP2L, AP2R, AP3, AP3", AP4, AP5, AP6, AP71, AP72, AP81, AP82, AP9, AP91, AP92, AP93, AP94, AP10: auxiliary patterns AP1La, AP1Ra, AP2La, AP2Ra, AP72a, AP82a: the first extension AP1Lb, AP1Rb, AP2Lb, AP2Rb, AP72b, AP82b: second extension BP1, BP2, BP2’: connecting pad CH: Channel area CL1, CL2, CL3, CL4, CL5, CL6, CL7, CL8, CL9: virtual connection CP1, CP11, CP12, CP1A, CP2, CP21, CP22: conductive pattern D: Dip pole DR: Drain region ES: epitaxial structure E1: first electrode E2: second electrode G: Gate H1, H1’, H1”, H2, H2’, H2”, H3, H3’, H4, H4’, H5, H6, H7, H8, H9: holes LED: light-emitting element PA: Peripheral area PL1, PL2: Peripheral routing PX: Pixel structure S: source SC: Semiconductor pattern SL1, SL1’, SL1”, SL1A, SL2, SL2’, SL3: signal lines SR: Source region T: Active component X, X’, Y, Y’, Z: direction

FIG. 1 is a schematic top view of a pixel array substrate according to a first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of the pixel array substrate of FIG. 1. FIG. 3 is a schematic top view of a pixel array substrate according to a second embodiment of the present invention. 4 is a schematic top view of a pixel array substrate according to a third embodiment of the present invention. FIG. 5 is a schematic top view of a pixel array substrate according to a fourth embodiment of the present invention. FIG. 6 is a schematic top view of a pixel array substrate according to a fifth embodiment of the present invention. FIG. 7 is a schematic top view of a pixel array substrate according to a sixth embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of the pixel array substrate of FIG. 7. FIG. 9 is a schematic top view of a pixel array substrate according to a seventh embodiment of the present invention. FIG. 10 is a schematic top view of a pixel array substrate according to an eighth embodiment of the present invention. FIG. 11 is a schematic top view of a pixel array substrate according to a ninth embodiment of the present invention. FIG. 12 is a schematic top view of a pixel array substrate according to a tenth embodiment of the present invention. FIG. 13 is a schematic top view of the pixel array substrate of FIG. 12. FIG. 14 is a schematic top view of a pixel array substrate according to an eleventh embodiment of the present invention.

10: Pixel array substrate

100: substrate

AP1, AP2, AP3: auxiliary pattern

CL1, CL2: Virtual connection

CP1, CP11, CP12, CP2, CP21, CP22: conductive pattern

H1, H2, H3, H4: holes

SL1, SL2: signal line

X, Y, Z: direction

Claims (16)

A pixel array substrate includes: A substrate having a first surface and a second surface opposite to each other; A first hole and a second hole, each passing through the first surface and the second surface; A first conductive pattern and a second conductive pattern disposed on one side of the first surface of the substrate; At least one signal line is disposed on one side of the second surface of the substrate, wherein the first conductive pattern and the second conductive pattern are electrically connected to the at least one signal line through the first hole and the second hole, respectively; as well as At least one auxiliary pattern is overlapped and arranged on a virtual line between the first hole and the second hole. The pixel array substrate according to claim 1, wherein the material of the at least one auxiliary pattern includes a metal material. The pixel array substrate according to claim 2, wherein the at least one auxiliary pattern has a floating potential. The pixel array substrate according to claim 1, wherein the material of the at least one auxiliary pattern includes a polymer material. The pixel array substrate according to claim 1, wherein the at least one auxiliary pattern includes a first auxiliary pattern and a second auxiliary pattern, and at least one of the first conductive pattern and the second conductive pattern and the first An auxiliary pattern belongs to the same film layer. The pixel array substrate according to claim 5, wherein the first auxiliary pattern and the second auxiliary pattern belong to different layers. The pixel array substrate according to claim 6, wherein the first auxiliary pattern overlaps the second auxiliary pattern. The pixel array substrate according to claim 5, wherein the extension direction of the first auxiliary pattern is different from the extension direction of the second auxiliary pattern. The pixel array substrate according to claim 1, wherein the auxiliary pattern has a first extension section and a second extension section connected, and the extension direction of the first extension section is different from that of the second extension section direction. The pixel array substrate according to claim 1, wherein the outline of the vertical projection of the auxiliary pattern on the substrate is a meniscus shape. The pixel array substrate according to claim 1, wherein the outline of the vertical projection of the auxiliary pattern on the substrate is a circle. The pixel array substrate according to claim 1, wherein the auxiliary pattern overlaps the first hole and the second hole. The pixel array substrate according to claim 1, wherein the auxiliary pattern surrounds the first hole. The pixel array substrate according to claim 1, further comprising a third conductive pattern disposed between the first conductive pattern and the second conductive pattern, and the at least one auxiliary pattern is located between the first hole and the second conductive pattern. Between three conductive patterns. The pixel array substrate according to claim 1, wherein the extension direction of the auxiliary pattern is perpendicular to the arrangement direction of the first hole and the second hole. The pixel array substrate according to claim 1, wherein the auxiliary pattern does not overlap the first signal line and the second signal line.

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