TWI722908B - Pixel array substrate - Google Patents
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- TWI722908B TWI722908B TW109117483A TW109117483A TWI722908B TW I722908 B TWI722908 B TW I722908B TW 109117483 A TW109117483 A TW 109117483A TW 109117483 A TW109117483 A TW 109117483A TW I722908 B TWI722908 B TW I722908B
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Abstract
Description
本發明是有關於一種電路基板,且特別是有關於一種畫素陣列基板。The present invention relates to a circuit substrate, and particularly relates to a pixel array substrate.
近年來,由於發光二極體顯示器,例如有機發光二極體(Organic light-emitting diode,OLED)顯示器或微型發光二極體顯示器(micro light-emitting diode,micro-LED)顯示器,具有高色彩飽和度、應答速度快及高對比等優勢,於高階電子產品的市場成見度急遽增加。另一方面,由於發光二極體顯示器的外觀相較於傳統的液晶顯示器更顯輕薄,且其優異的可撓性可滿足多元化的顯示應用,例如:曲面顯示、可捲式電視牆或電子紙等應用。In recent years, light-emitting diode displays, such as organic light-emitting diode (OLED) displays or micro light-emitting diode (micro-LED) displays, have high color saturation The advantages of high-end electronic products, such as high-end electronic products, such as high-speed, fast response speed, and high contrast, have sharply increased the market stereotypes of high-end electronic products. On the other hand, because the appearance of light-emitting diode displays is lighter and thinner than traditional liquid crystal displays, and its excellent flexibility can meet diversified display applications, such as curved displays, rollable TV walls, or electronics Paper and other applications.
為了實現窄邊框(或無邊框)的外觀設計與超高解析度的顯示畫面,在畫素電路密度增加的情況下,將周邊線路配置在畫素區內,勢必會進一步造成顯示區內可用於配置電路的佈局空間不足。為了改善上述的問題,將畫素陣列基板的電路分散地設置在基板的相對兩側,並經由基板的多個微孔洞而彼此電性連接是目前較常見的解決方法之一。然而,這些微孔洞的存在會造成基板的挺性(stiffness)與可撓性(flexibility)變差。In order to achieve a narrow border (or no border) design and ultra-high-resolution display screen, when the pixel circuit density increases, the peripheral circuits are arranged in the pixel area, which will inevitably further cause the display area to be used for The layout space of the configuration circuit is insufficient. In order to improve the above-mentioned problems, it is one of the more common solutions to dispose the circuits of the pixel array substrate on opposite sides of the substrate and electrically connect to each other through a plurality of micro-holes in the substrate. However, the presence of these micro-holes will cause the stiffness and flexibility of the substrate to deteriorate.
本發明提供一種具有孔洞的畫素陣列基板,其挺性與可撓性較佳。The present invention provides a pixel array substrate with holes, which has better stiffness and flexibility.
本發明的畫素陣列基板,包括基板、第一孔洞、第二孔洞、第一導電圖案、第二導電圖案、至少一訊號線以及至少一輔助圖案。基板具有相對的第一表面與第二表面。第一孔洞與第二孔洞各自貫穿第一表面與第二表面。第一導電圖案與第二導電圖案設置於基板的第一表面的一側。至少一訊號線設置於基板的第二表面的一側。第一導電圖案與第二導電圖案分別經由第一孔洞與第二孔洞電性連接至少一訊號線。至少一輔助圖案重疊設置於第一孔洞與第二孔洞的虛擬連線。The pixel array substrate of the present invention includes a substrate, a first hole, a second hole, a first conductive pattern, a second conductive pattern, at least one signal line, and at least one auxiliary pattern. The substrate has a first surface and a second surface opposite to each other. The first hole and the second hole respectively penetrate the first surface and the second surface. The first conductive pattern and the second conductive pattern are disposed on one side of the first surface of the substrate. At least one signal line is arranged on one side of the second surface of the substrate. The first conductive pattern and the second conductive pattern are electrically connected to at least one signal line through the first hole and the second hole, respectively. At least one auxiliary pattern is overlapped and arranged on the virtual line between the first hole and the second hole.
基於上述,在本發明的一實施例的畫素陣列基板中,位於基板相對兩側的多個導電圖案與多條訊號線的電性連接關係是經由貫穿基板的多個孔洞來實現。當畫素陣列基板被撓曲時,這些孔洞的虛擬連線上所設置的輔助圖案,可避免應力集中在這些孔洞之間而使附近的膜層產生裂縫。換句話說,可增加基板在孔洞邊緣附近的區域的挺性,據以提升畫素陣列基板的耐撓曲性。Based on the above, in the pixel array substrate of an embodiment of the present invention, the electrical connection relationship between the plurality of conductive patterns on opposite sides of the substrate and the plurality of signal lines is realized through a plurality of holes penetrating the substrate. When the pixel array substrate is flexed, the auxiliary patterns provided on the virtual lines of the holes can prevent the stress from being concentrated between the holes and causing cracks in the nearby film. In other words, the stiffness of the substrate near the edge of the hole can be increased, thereby improving the flexibility resistance of the pixel array substrate.
本文使用的「約」、「近似」、「本質上」、或「實質上」包括所述值和在本領域普通技術人員確定的特定值的可接受的偏差範圍內的平均值,考慮到所討論的測量和與測量相關的誤差的特定數量(即,測量系統的限制)。例如,「約」可以表示在所述值的一個或多個標準偏差內,或例如±30%、±20%、±15%、±10%、±5%內。再者,本文使用的「約」、「近似」、「本質上」、或「實質上」可依量測性質、切割性質或其它性質,來選擇較可接受的偏差範圍或標準偏差,而可不用一個標準偏差適用全部性質。As used herein, "approximately", "approximately", "essentially", or "substantially" includes the stated value and the average value within the acceptable deviation range of the specific value determined by a person of ordinary skill in the art, taking into account all The measurement in question and the specific number of errors associated with the measurement (ie, the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or, for example, within ±30%, ±20%, ±15%, ±10%, ±5%. Furthermore, "about", "approximately", "essentially", or "substantially" used in this article can be based on measurement properties, cutting properties, or other properties to select a more acceptable deviation range or standard deviation. Not one standard deviation applies to all properties.
在附圖中,為了清楚起見,放大了層、膜、面板、區域等的厚度。應當理解,當諸如層、膜、區域或基板的元件被稱為在另一元件「上」或「連接到」另一元件時,其可以直接在另一元件上或與另一元件連接,或者中間元件可以也存在。相反,當元件被稱為「直接在另一元件上」或「直接連接到」另一元件時,不存在中間元件。如本文所使用的,「連接」可以指物理及/或電性連接。再者,「電性連接」可為二元件間存在其它元件。In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connection" can refer to physical and/or electrical connection. Furthermore, "electrical connection" can mean that there are other components between the two components.
此外,諸如「下」或「底部」和「上」或「頂部」的相對術語可在本文中用於描述一個元件與另一元件的關係,如圖所示。應當理解,相對術語旨在包括除了圖中所示的方位之外的裝置的不同方位。例如,如果一個附圖中的裝置翻轉,則被描述為在其它元件的「下」側的元件將被定向在其它元件的「上」側。因此,示例性術語「下」可以包括「下」和「上」的取向,取決於附圖的特定取向。類似地,如果一個附圖中的裝置翻轉,則被描述為在其它元件「下方」或「下方」的元件將被定向為在其它元件「上方」。因此,示例性術語「上面」或「下面」可以包括上方和下方的取向。In addition, relative terms such as "lower" or "bottom" and "upper" or "top" can be used herein to describe the relationship between one element and another element, as shown in the figure. It should be understood that relative terms are intended to include different orientations of the device in addition to the orientation shown in the figures. For example, if the device in one figure is turned over, elements described as being on the "lower" side of other elements will be oriented on the "upper" side of the other elements. Therefore, the exemplary term "lower" may include an orientation of "lower" and "upper," depending on the specific orientation of the drawing. Similarly, if the device in one figure is turned over, elements described as "below" or "below" other elements will be oriented "above" the other elements. Thus, the exemplary terms "above" or "below" can include an orientation of above and below.
現將詳細地參考本發明的示範性實施方式,示範性實施方式的實例說明於所附圖式中。只要有可能,相同元件符號在圖式和描述中用來表示相同或相似部分。Reference will now be made in detail to the exemplary embodiments of the present invention, and examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and descriptions to indicate the same or similar parts.
圖1是本發明的第一實施例的畫素陣列基板的俯視示意圖。圖2是圖1的畫素陣列基板的剖視示意圖。特別說明的是,為清楚呈現起見,圖1省略了圖2的絕緣層110、閘絕緣層120、層間絕緣層130、平坦層140、主動元件T、連接墊BP1、連接墊BP2及發光元件LED的繪示,且圖1的訊號線SL1與訊號線SL2是以虛線的方式呈現。FIG. 1 is a schematic top view of a pixel array substrate according to a first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of the pixel array substrate of FIG. 1. In particular, for the sake of clarity, FIG. 1 omits the
請參照圖1及圖2,畫素陣列基板10包括基板100、多個導電圖案、多條訊號線及多個孔洞。基板100具有相對的第一表面100a與第二表面100b。這些導電圖案設置於基板100的第一表面100a的一側,這些訊號線則是設置在基板100的第二表面100b的一側。更具體地說,為了增加畫素陣列基板10用於配置電路的可佈局空間,其訊號線、週邊走線及畫素的驅動電路是分散地設置在基板100的相對兩側,並經由基板100的這些孔洞來實現這些電路之間的電性連接關係。1 and 2, the
在本實施例中,基板100可以是硬質基板,其材質包括玻璃或石英,但不以此為限。在其他實施例中,基板100也可以是軟質基板(即可撓基板),其材質包括聚醯亞胺(polyimide)、聚乙烯對苯二甲酸酯(polyethylene terephthalate, PET)、聚間苯二甲酸乙二酯(polyethylene naphthalate, PEN)、聚醚石風(Polyethersulfone, PES)、聚甲基丙烯酸甲酯(polymethyl methacrylate, PMMA)、聚碳酸酯(Polycarbonate, PC)、或其他適合的高分子聚合物。In this embodiment, the
進一步而言,畫素陣列基板10的這些導電圖案包括多個導電圖案CP1與多個導電圖案CP2,且導電圖案CP1與導電圖案CP2屬於不同的膜層。這些導電圖案CP1(或導電圖案CP2)分別在方向X與方向Y上排成多列與多行,且結構上彼此分離。值得注意的是,畫素陣列基板10的多個孔洞分別對應這些導電圖案而設置。舉例來說,畫素陣列基板10的孔洞H1與孔洞H2在方向Z上分別重疊於導電圖案CP11與導電圖案CP12,而畫素陣列基板10的孔洞H3與孔洞H4在方向Z上分別重疊於導電圖案CP21與導電圖案CP22。在本實施例中,畫素陣列基板10的這些孔洞可藉由雷射鑽孔(laser drilling)、蝕刻(etching)、機械鑽孔(mechanical drilling)、或是其他精密的加工方式來形成,但不以此為限。Furthermore, the conductive patterns of the
在本實施例中,畫素陣列基板10的上述多條訊號線可包括多條訊號線SL1與多條訊號線SL2。這些訊號線SL1沿方向Y排列且在方向X上延伸。這些訊號線SL2沿方向X排列且在方向Y上延伸。更具體地說,這些訊號線SL1相交於這些訊號線SL2。舉例來說,在本實施例中,訊號線SL1可以是掃描線(scan line),訊號線SL2可以是用於傳輸電壓源(例如Vdd)的電源線(power line),但不以此為限。在其他實施例中,訊號線SL1、訊號線SL2也可分別選自資料線(data line)、感測線(sensing line)或重置訊號線(reset line)。為了確保訊號線SL1與訊號線SL2的電性獨立,畫素陣列基板10更包括位於基板100的第二表面100b的一側的絕緣層110,且此絕緣層110設置在訊號線SL1與訊號線SL2之間。In this embodiment, the multiple signal lines of the
在本實施例中,這些導電圖案CP1(例如導電圖案CP11與導電圖案CP12)分別設置在這些訊號線SL1的延伸路徑上,這些導電圖案CP2(例如導電圖案CP21與導電圖案CP22)分別設置在這些訊號線SL2的延伸路徑上。值得注意的是,重疊於導電圖案CP1的孔洞(例如孔洞H1與孔洞H2)也設置在對應的一條訊號線SL1的延伸路徑上,重疊於導電圖案CP2的孔洞(例如孔洞H3與孔洞H4)也設置在對應的一條訊號線SL2的延伸路徑上。舉例而言,位於基板100的第一表面100a上的導電圖案CP11與導電圖案CP12分別經由孔洞H1與孔洞H2電性連接位於基板100的第二表面100b上的同一條訊號線SL1,而位於基板100的第一表面100a上的導電圖案CP21與導電圖案CP22分別經由孔洞H3與孔洞H4電性連接位於基板100的第二表面100b上的兩條訊號線SL2。In this embodiment, the conductive patterns CP1 (for example, the conductive pattern CP11 and the conductive pattern CP12) are respectively arranged on the extension paths of the signal lines SL1, and the conductive patterns CP2 (for example, the conductive pattern CP21 and the conductive pattern CP22) are respectively arranged on these On the extension path of the signal line SL2. It is worth noting that the holes (for example, holes H1 and H2) overlapping the conductive pattern CP1 are also arranged on the extension path of a corresponding signal line SL1, and the holes (for example, the holes H3 and the holes H4) overlapping the conductive pattern CP2 are also arranged on the extension path of the corresponding signal line SL1. Set on the extension path of a corresponding signal line SL2. For example, the conductive pattern CP11 and the conductive pattern CP12 on the
畫素陣列基板10更包括多個畫素結構PX。舉例而言,多條訊號線SL1與多條訊號線SL2可定義出多個畫素區,且這些畫素結構PX分別設置於這些畫素區內,但不以此為限。畫素結構PX包括彼此電性連接的主動元件T與發光元件LED。在本實施例中,形成主動元件T的方法可包括以下步驟:於基板100的第一表面100a上依序形成半導體圖案SC、閘絕緣層120、閘極G、層間絕緣層130、源極S與汲極D,其中半導體圖案SC包括源極區SR、汲極區DR與通道區CH。源極S與汲極D貫穿層間絕緣層130與閘絕緣層120以分別電性連接半導體圖案SC的源極區SR與汲極區DR,且源極S的另一端與導電圖案CP21相連接。The
在本實施例中,主動元件T的閘極G可選擇性地配置在半導體圖案SC的上方,以形成頂部閘極型薄膜電晶體(top-gate TFT),但本發明不以此為限。根據其他的實施例,主動元件的閘極G也可配置在半導體圖案SC的下方,以形成底部閘極型薄膜電晶體(bottom-gate TFT)。另一方面,半導體圖案SC的材質例如是多晶矽半導體(polysilicon semiconductor)材料,也就是說,主動元件T可以是低溫多晶矽薄膜電晶體(LTPS TFT)。然而,本發明不限於此,在其他實施例中,主動元件也可以是非晶矽薄膜電晶體(Amorphous Silicon TFT,a-Si TFT)、微晶矽薄膜電晶體(micro-Si TFT)或金屬氧化物電晶體(Metal Oxide Transistor)。In this embodiment, the gate G of the active device T can be selectively disposed above the semiconductor pattern SC to form a top-gate TFT, but the invention is not limited to this. According to other embodiments, the gate G of the active device can also be arranged under the semiconductor pattern SC to form a bottom-gate TFT. On the other hand, the material of the semiconductor pattern SC is, for example, a polysilicon semiconductor material, that is, the active device T may be a low temperature polysilicon thin film transistor (LTPS TFT). However, the present invention is not limited to this. In other embodiments, the active device may also be an amorphous silicon thin film transistor (a-Si TFT), a micro-Si thin film transistor (micro-Si TFT), or a metal oxide. Material Transistor (Metal Oxide Transistor).
在形成主動元件T的步驟完成後,於層間絕緣層130、源極S與汲極D上依序形成平坦層140、連接墊BP1與連接墊BP2,其中連接墊BP1貫穿平坦層140以電性連接主動元件T的汲極D。連接墊BP1與連接墊BP2用於承接發光元件LED,且發光元件LED經由這些連接墊與基板100上的畫素電路層電性連接。在本實施例中,發光元件LED可包括磊晶結構ES、第一電極E1與第二電極E2,且第一電極E1與第二電極E2位於磊晶結構ES的同一側。也就是說,本實施例的發光元件LED可以是覆晶式(flip-chip type)發光二極體,但本發明不以此為限。在其他實施例中,發光元件也可以是水平式(lateral type)發光二極體或垂直式(vertical type)發光二極體。After the step of forming the active device T is completed, a
需說明的是,閘極G、源極S、汲極D、絕緣層110、閘絕緣層120、層間絕緣層130、平坦層140及連接墊分別可由任何所屬技術領域中具有通常知識者所周知的用於顯示面板的任一閘極、任一源極、任一汲極、任一絕緣層、任一閘絕緣層、任一層間絕緣層、任一平坦層及任一連接墊來實現,且閘極G、源極S、汲極D、絕緣層110、閘絕緣層120、層間絕緣層130、平坦層140及連接墊分別可藉由任何所屬技術領域中具有通常知識者所周知的任一方法來形成,故於此不加以贅述。It should be noted that the gate G, the source S, the drain D, the insulating
進一步而言,畫素陣列基板10更包括多個輔助圖案,且這些輔助圖案分別設置在多個孔洞的虛擬連線上。舉例來說,這些輔助圖案包括輔助圖案AP1、輔助圖案AP2與輔助圖案AP3。輔助圖案AP1設置在孔洞H1與孔洞H2的虛擬連線CL1上。輔助圖案AP2與輔助圖案AP3設置在孔洞H3與孔洞H4的虛擬連線CL2上。據此,可避免畫素陣列基板10撓曲時,應力集中在這些孔洞之間而使附近的膜層(例如導電層或絕緣層)產生裂縫,造成電性上的問題。換句話說,透過在這些孔洞的虛擬連線上設置至少一輔助圖案,可增加基板100在孔洞邊緣附近的區域的挺性(stiffness),進而提升畫素陣列基板10的耐撓曲性。從另一觀點來說,透過這些輔助圖案的設置,還能有效提升雷射鑽孔的精準度。亦即,可提升雷射鑽孔製程的良率。Furthermore, the
需說明的是,此處的虛擬連線是由兩孔洞各自的幾何中心的連線來定義,但不以此為限。在其他實施例中,虛擬連線也可由兩孔洞各自的邊緣上的任一點的連線來定義。由於圖1的訊號線SL1大致上重疊於孔洞H1與孔洞H2的幾何中心,因此圖1的孔洞H1與孔洞H2之間的虛擬連線CL1理應重疊於訊號線SL1。然而,為了清楚呈現起見,虛擬連線CL1是以稍微偏離訊號線SL1的方式示出。It should be noted that the virtual connection here is defined by the connection between the geometric centers of the two holes, but it is not limited to this. In other embodiments, the virtual line can also be defined by the line at any point on the respective edges of the two holes. Since the signal line SL1 in FIG. 1 roughly overlaps the geometric centers of the holes H1 and H2, the virtual connection CL1 between the holes H1 and the hole H2 in FIG. 1 should overlap the signal line SL1. However, for the sake of clarity, the virtual connection CL1 is shown slightly deviating from the signal line SL1.
在本實施例中,輔助圖案AP1、閘極G、導電圖案CP11與導電圖案CP12可選擇性地屬於同一膜層,輔助圖案AP2、輔助圖案AP3、源極S、汲極D、導電圖案CP21及導電圖案CP22可選擇性地屬於同一膜層,但不以此為限。也就是說,輔助圖案的材質可包括金屬材料,例如:鉬、鋁、銅、上述的合金、或上述的組合,但不以此為限。然而,本發明不限於此,根據其他實施例,為了增加多個孔洞間的膜層的延展性,輔助圖案的材質也可以是楊氏模量(Young’s modulus)較小的高分子材料。In this embodiment, the auxiliary pattern AP1, the gate G, the conductive pattern CP11, and the conductive pattern CP12 can selectively belong to the same film layer. The auxiliary pattern AP2, the auxiliary pattern AP3, the source S, the drain D, the conductive pattern CP21 and The conductive patterns CP22 can selectively belong to the same film layer, but it is not limited thereto. That is, the material of the auxiliary pattern may include metal materials, such as molybdenum, aluminum, copper, the above alloy, or a combination of the above, but it is not limited thereto. However, the present invention is not limited to this. According to other embodiments, in order to increase the ductility of the film layer between the multiple holes, the material of the auxiliary pattern may also be a polymer material with a small Young’s modulus.
特別一提的是,這些輔助圖案都具有浮置電位(floating potential)。也就是說,本實施例的這些輔助圖案雖然是以導電性材料製作而成,但都未與畫素陣列基板10的驅動電路層或任何的訊號線電性連接,如此可確保畫素陣列基板10(或顯示器)的電性操作不受影響。另一方面,為了達到顯示畫素的最緊密排列,輔助圖案的延伸方向可選擇性地垂直於孔洞間的虛擬連線的延伸方向。舉例而言,在本實施例中,輔助圖案AP1的延伸方向(例如方向Y)可垂直於孔洞H1與孔洞H2的虛擬連線CL1的延伸方向,輔助圖案AP2與輔助圖案AP3的延伸方向(例如方向Y)可垂直於孔洞H3與孔洞H4的虛擬連線CL2的延伸方向,但本發明不以此為限。In particular, these auxiliary patterns have floating potentials. That is to say, although the auxiliary patterns of this embodiment are made of conductive materials, they are not electrically connected to the driving circuit layer of the
以下將列舉另一些實施例以詳細說明本揭露,其中相同的構件將標示相同的符號,並且省略相同技術內容的說明,省略部分請參考前述實施例,以下不再贅述。Other embodiments will be listed below to describe the disclosure in detail, wherein the same components will be marked with the same symbols, and the description of the same technical content will be omitted. For the omitted parts, please refer to the foregoing embodiments, and will not be repeated hereafter.
圖3是本發明的第二實施例的畫素陣列基板的俯視示意圖。請參照圖3,本實施例的畫素陣列基板11與圖1的畫素陣列基板10的差異在於:輔助圖案的配置方式不同。具體而言,畫素陣列基板11包括輔助圖案AP11、輔助圖案AP12、輔助圖案AP21與輔助圖案AP22。輔助圖案AP11與輔助圖案AP21設置於孔洞H1與孔洞H2的虛擬連線CL1上,輔助圖案AP12與輔助圖案AP22設置於孔洞H3與孔洞H2的虛擬連線CL2上。FIG. 3 is a schematic top view of a pixel array substrate according to a second embodiment of the present invention. Please refer to FIG. 3, the difference between the
應注意的是,透過輔助圖案AP21與輔助圖案AP22在方向Z上分別重疊於輔助圖案AP11與輔助圖案AP12,可進一步增加這些孔洞之間的膜層延展性。另一方面,透過相互重疊的兩輔助圖案的延伸方向不同,可增加這些孔洞之間的膜層在不同方向上的延展性。舉例來說,設置於孔洞H1與孔洞H2的虛擬連線CL1上的輔助圖案AP11與輔助圖案AP21分別在方向Y與方向X上延伸,設置於孔洞H3與孔洞H4的虛擬連線CL2上的輔助圖案AP12與輔助圖案AP22分別在方向X與方向Y上延伸。It should be noted that by overlapping the auxiliary pattern AP21 and the auxiliary pattern AP22 on the auxiliary pattern AP11 and the auxiliary pattern AP12 respectively in the direction Z, the ductility of the film between these holes can be further increased. On the other hand, through the different extension directions of the two overlapping auxiliary patterns, the ductility of the film layer between the holes in different directions can be increased. For example, the auxiliary pattern AP11 and the auxiliary pattern AP21 arranged on the virtual line CL1 of the hole H1 and the hole H2 extend in the direction Y and the direction X, respectively, and the auxiliary pattern AP11 and the auxiliary pattern AP21 arranged on the virtual line CL2 of the hole H3 and the hole H4 The pattern AP12 and the auxiliary pattern AP22 extend in the direction X and the direction Y, respectively.
在本實施例中,輔助圖案AP11、輔助圖案AP12與導電圖案CP1可選擇性地為同一膜層,輔助圖案AP21、輔助圖案AP22與導電圖案CP2可選擇性地為同一膜層,但不以此為限。In this embodiment, the auxiliary pattern AP11, the auxiliary pattern AP12, and the conductive pattern CP1 can optionally be the same film layer, and the auxiliary pattern AP21, the auxiliary pattern AP22, and the conductive pattern CP2 can selectively be the same film layer, but not so. Is limited.
圖4是本發明的第三實施例的畫素陣列基板的俯視示意圖。請參照圖4,本實施例的畫素陣列基板12與圖1的畫素陣列基板10的差異在於:訊號線、導電圖案與輔助圖案的配置方式不同。在本實施例中,為了達到畫素結構的最密排列,多條訊號線SL1’的延伸方向不垂直且不平行於多條訊號線SL2。舉例來說,這些訊號線SL1’是沿著方向Y’排列且在方向X’延伸,且在方向Z上相互重疊的多個導電圖案CP1’與多個孔洞(例如孔洞H1’、孔洞H2’與孔洞H5)分別排列於這些訊號線SL1’的延伸路徑上。另一方面,不同於圖1的多個導電圖案CP2的排列方式,本實施例的多個導電圖案CP2’是分別在方向Y、方向X’與方向Y’上排列多串。4 is a schematic top view of a pixel array substrate according to a third embodiment of the present invention. Referring to FIG. 4, the difference between the
進一步而言,畫素陣列基板12包括位於同一膜層的輔助圖案AP1a、輔助圖案AP1b與輔助圖案AP1c以及位於另一膜層的輔助圖案AP2’。舉例來說,孔洞H1’與孔洞H2’的虛擬連線CL3上設置有輔助圖案AP1a,孔洞H1’與孔洞H3’的虛擬連線CL4上設有相互重疊的輔助圖案AP1b與輔助圖案AP2’,孔洞H1’與孔洞H4’的虛擬連線CL5上設有輔助圖案AP1c。據此,當畫素陣列基板12撓曲時,可避免應力集中在這些孔洞之間而使附近的膜層(例如導電層或絕緣層)產生裂縫,造成電性上的問題。換句話說,透過在這些孔洞的虛擬連線上設置至少一輔助圖案,可增加基板100在孔洞邊緣附近的區域的挺性(stiffness),進而提升畫素陣列基板12的耐撓曲性。Furthermore, the
在本實施例中,輔助圖案AP1a、輔助圖案AP1b、輔助圖案AP1c與導電圖案CP1’可選擇性地為同一膜層,輔助圖案AP2’與導電圖案CP2’可選擇性地為同一膜層,但不以此為限。In this embodiment, the auxiliary pattern AP1a, the auxiliary pattern AP1b, the auxiliary pattern AP1c, and the conductive pattern CP1' can optionally be the same film layer, and the auxiliary pattern AP2' and the conductive pattern CP2' can optionally be the same film layer, but Not limited to this.
圖5是本發明的第四實施例的畫素陣列基板的俯視示意圖。請參照圖5,本實施例的畫素陣列基板13與圖1的畫素陣列基板10的差異在於:輔助圖案於基板上的投影輪廓不同。在本實施例中,畫素陣列基板13的多個輔助圖案,例如輔助圖案AP1”、輔助圖案AP2”、輔助圖案AP3”與輔助圖案AP4,於基板100上的垂直投影輪廓為圓形。據此,當畫素陣列基板13撓曲時,可避免應力集中在如圖1的輔助圖案AP1的邊角而造成輔助圖案AP1的毀損。從另一觀點來說,透過具有圓形輪廓的輔助圖案的配置還可增加位於多個孔洞之間的膜層在各個方向上的延展性。FIG. 5 is a schematic top view of a pixel array substrate according to a fourth embodiment of the present invention. Referring to FIG. 5, the difference between the
圖6是本發明的第五實施例的畫素陣列基板的俯視示意圖。請參照圖6,本實施例的畫素陣列基板14與圖1的畫素陣列基板10的差異在於:輔助圖案於基板上的投影輪廓不同。在本實施例中,畫素陣列基板14的多個輔助圖案,例如輔助圖案AP1L、輔助圖案AP1R、輔助圖案AP2L與輔助圖案AP2R,於基板100上的垂直投影輪廓為彎月形。應注意的是,本實施例的輔助圖案可重疊於多個孔洞在不同排列方向上的多條虛擬連線,例如:輔助圖案AP1L在方向Z上同時重疊於孔洞H1與孔洞H2的虛擬連線CL1、孔洞H2與孔洞H3的虛擬連線CL6以及孔洞H3與孔洞H4的虛擬連線CL2。據此,可增加這些孔洞之間的膜層的延展性。另一方面,透過彎月形的輪廓,還可避免應力集中在如圖1的輔助圖案AP1的邊角而造成輔助圖案AP1的毀損。換句話說,本實施例的輔助圖案可具有較佳的耐彎折特性。FIG. 6 is a schematic top view of a pixel array substrate according to a fifth embodiment of the present invention. Please refer to FIG. 6, the difference between the
在本實施例中,輔助圖案AP1L具有相連接的第一延伸段AP1La與第二延伸段AP1Lb,且第一延伸段AP1La的延伸方向不同於第二延伸段AP1Lb的延伸方向。舉例而言,當基板100沿著方向X撓曲時,設置在孔洞H1與孔洞H2的虛擬連線CL1上的輔助圖案AP1L的第一延伸段AP1La,可增加孔洞H1與孔洞H2之間的膜層在方向X上的延展性;相似地,設置在孔洞H3與孔洞H4的虛擬連線CL2上的輔助圖案AP1L的第二延伸段AP1Lb,可增加孔洞H3與孔洞H4之間的膜層在方向X上的延展性。當基板100沿著孔洞H2與孔洞H3的排列方向撓曲時,設置在孔洞H2與孔洞H3的虛擬連線CL6上的第二延伸段AP1Lb還可增加孔洞H2與孔洞H3之間的膜層在所述撓曲方向上的延展性。In this embodiment, the auxiliary pattern AP1L has a first extension AP1La and a second extension AP1Lb connected, and the extension direction of the first extension AP1La is different from the extension direction of the second extension AP1Lb. For example, when the
同樣地,輔助圖案AP2L具有相連接的第一延伸段AP2La與第二延伸段AP2Lb,且第一延伸部AP2La的延伸方向不同於第二延伸部AP2Lb的延伸方向。舉例而言,當基板100沿著方向X撓曲時,設置在孔洞H3與孔洞H4的虛擬連線CL2上的輔助圖案AP2L,可增加孔洞H3與孔洞H4之間的膜層在方向X上的延展性。當基板100沿著孔洞H1與孔洞H4的排列方向撓曲時,設置在孔洞H1與孔洞H4的虛擬連線CL7上的第一延伸段AP2La還可增加孔洞H1與孔洞H4之間的膜層在所述撓曲方向上的延展性。當基板100沿著孔洞H5與孔洞H4的排列方向撓曲時,設置在孔洞H5與孔洞H4的虛擬連線CL8上的第二延伸段AP2Lb還可增加孔洞H5與孔洞H4之間的膜層在所述撓曲方向上的延展性。Similarly, the auxiliary pattern AP2L has a first extension AP2La and a second extension AP2Lb connected, and the extension direction of the first extension AP2La is different from the extension direction of the second extension AP2Lb. For example, when the
承接上述,透過具有彎月形輪廓的輔助圖案的配置,可增加位於多個孔洞(例如孔洞H1、孔洞H2、孔洞H3、孔洞H4與孔洞H5)之間的膜層在多個方向上的延展性。在本實施例中,在方向Y上排列的輔助圖案AP1L與輔助圖案AP1R的彎月形輪廓的開口方向可彼此相反,例如:輔助圖案AP1L的開口方向為方向X的相反方向,輔助圖案AP1R的開口方向為方向X。Continuing the above, through the configuration of the auxiliary pattern with the meniscus profile, the film layer located between the multiple holes (such as the hole H1, the hole H2, the hole H3, the hole H4 and the hole H5) can be increased in multiple directions. Sex. In this embodiment, the opening directions of the meniscus contours of the auxiliary pattern AP1L and the auxiliary pattern AP1R arranged in the direction Y may be opposite to each other. For example, the opening direction of the auxiliary pattern AP1L is the opposite direction of the direction X, and the auxiliary pattern AP1R The direction of the opening is the direction X.
也就是說,輔助圖案AP1R的第一延伸段AP1Ra的延伸方向大致上平行於輔助圖案AP1L的第二延伸段AP1Lb的延伸方向,輔助圖案AP1R的第二延伸段AP1Rb的延伸方向大致上平行於輔助圖案AP1L的第一延伸段AP1La的延伸方向。相似地,輔助圖案AP2R的第一延伸段AP2Ra的延伸方向大致上平行於輔助圖案AP2L的第二延伸段AP2Lb的延伸方向,輔助圖案AP2R的第二延伸段AP2Rb的延伸方向大致上平行於輔助圖案AP2L的第一延伸段AP2La的延伸方向。然而,本發明不限於此,在其他實施例中,所有具有彎月形輪廓的輔助圖案的開口方向也可朝同一方向設置。That is, the extension direction of the first extension AP1Ra of the auxiliary pattern AP1R is substantially parallel to the extension direction of the second extension AP1Lb of the auxiliary pattern AP1L, and the extension direction of the second extension AP1Rb of the auxiliary pattern AP1R is substantially parallel to the auxiliary pattern AP1R. The extension direction of the first extension AP1La of the pattern AP1L. Similarly, the extension direction of the first extension AP2Ra of the auxiliary pattern AP2R is substantially parallel to the extension direction of the second extension AP2Lb of the auxiliary pattern AP2L, and the extension direction of the second extension AP2Rb of the auxiliary pattern AP2R is substantially parallel to the auxiliary pattern. The extension direction of the first extension section AP2La of AP2L. However, the present invention is not limited to this. In other embodiments, the opening directions of all auxiliary patterns with a meniscus profile can also be set in the same direction.
圖7是本發明的第六實施例的畫素陣列基板的俯視示意圖。圖8是圖7的畫素陣列基板的剖視示意圖。請參照圖7及圖8,本實施例的畫素陣列基板15與圖1的畫素陣列基板10的差異在於:輔助圖案的膜層及配置方式不同。具體而言,畫素陣列基板15的輔助圖案(例如輔助圖案AP5與輔助圖案AP6)、連接墊BP1與連接墊BP2為同一膜層,輔助圖案AP5在方向Z上重疊於孔洞H1與孔洞H2,且輔助圖案AP6在方向Z上重疊於孔洞H3與孔洞H4。在本實施例中,輔助圖案是在方向X上延伸並重疊於相鄰排列的兩孔洞,但本發明不以此為限。在其他實施例中,輔助圖案也可在孔洞H2與孔洞H4的排列方向上延伸並同時重疊於孔洞H2與孔洞H4。FIG. 7 is a schematic top view of a pixel array substrate according to a sixth embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of the pixel array substrate of FIG. 7. Referring to FIGS. 7 and 8, the difference between the
透過單一輔助圖案與多個孔洞的重疊關係,可增加基板100在孔洞邊緣附近的區域的挺性(stiffness),進而提升畫素陣列基板15的耐撓曲性。Through the overlapping relationship between the single auxiliary pattern and the multiple holes, the stiffness of the
圖9是本發明的第七實施例的畫素陣列基板的俯視示意圖。請參照圖9,本實施例的畫素陣列基板16與圖1的畫素陣列基板10的差異在於:輔助圖案於基板上的投影輪廓不同。在本實施例中,畫素陣列基板16的多個輔助圖案,例如輔助圖案AP71、輔助圖案AP72、輔助圖案AP81與輔助圖案AP82,於基板100上的垂直投影輪廓分別環繞多個孔洞,且這些輔助圖案的垂直投影輪廓大致上可分為兩類。FIG. 9 is a schematic top view of a pixel array substrate according to a seventh embodiment of the present invention. Please refer to FIG. 9, the difference between the
舉例來說,分別環繞孔洞H2與孔洞H4的輔助圖案AP71與輔助圖案AP81於基板100上的垂直投影輪廓為連續的環狀圖案,而分別環繞孔洞H6與孔洞H7的輔助圖案AP72與輔助圖案AP82於基板100上的垂直投影輪廓則為不連續的環狀圖案。在本實施例中,輔助圖案AP72具有結構上分離的第一延伸段AP72a與第二延伸段AP72b,這兩延伸段的凹口彼此相對並朝向所圍繞的孔洞H6。相似地,輔助圖案AP82具有結構上分離的第一延伸段AP82a與第二延伸段AP82b,這兩延伸段的凹口彼此相對並朝向所圍繞的孔洞H7。值得一提的是,透過輔助圖案環繞孔洞,可增加孔洞周邊膜層的延展性,進而提升畫素陣列基板16的耐撓曲性。For example, the vertical projection contours of the auxiliary pattern AP71 and the auxiliary pattern AP81 respectively surrounding the hole H2 and the hole H4 on the
在本實施例中,輔助圖案AP71與輔助圖案AP72所屬的膜層不同於導電圖案CP1或導電圖案CP2的所屬膜層。相反地,輔助圖案AP81、輔助圖案AP82與導電圖案CP1可選擇性地屬於同一膜層,但不以此為限。需說明的是,本發明並不加以限制輔助圖案的輪廓種類,在其他實施例中,為了進一步強化畫素陣列基板在各方向上的耐撓曲性,所有的輔助圖案的垂直投影輪廓也可以都是連續的環狀圖案。In this embodiment, the film layer to which the auxiliary pattern AP71 and the auxiliary pattern AP72 belong is different from the film layer to which the conductive pattern CP1 or the conductive pattern CP2 belongs. On the contrary, the auxiliary pattern AP81, the auxiliary pattern AP82, and the conductive pattern CP1 can selectively belong to the same film layer, but it is not limited thereto. It should be noted that the present invention does not limit the types of outlines of the auxiliary patterns. In other embodiments, in order to further enhance the flexibility resistance of the pixel array substrate in all directions, the vertical projection outlines of all auxiliary patterns may also be used. All are continuous ring patterns.
圖10是本發明的第八實施例的畫素陣列基板的俯視示意圖。請參照圖10,本實施例的畫素陣列基板17與圖1的畫素陣列基板10的差異在於:導電圖案與輔助圖案的配置方式不同。在本實施例中,畫素陣列基板17的導電圖案CP1A在方向Z上不重疊於導電圖案CP2,導電圖案CP2位於孔洞H1”與孔洞H2”的虛擬連線CL9上,且輔助圖案AP9設置在導電圖案CP1A與導電圖案CP2之間。透過在訊號線SL2與導電圖案CP1A之間設置輔助圖案AP9可增加孔洞間(尤其是孔洞與鄰近的訊號線之間的區域)的基板挺性與耐撓曲性。特別說明的是,輔助圖案的設置並不侷限在畫素陣列基板10的顯示區AA內,於顯示區AA以外的周邊區PA也可設有輔助圖案。FIG. 10 is a schematic top view of a pixel array substrate according to an eighth embodiment of the present invention. Please refer to FIG. 10, the difference between the
在本實施例中,畫素陣列基板17還可包括多條周邊走線,例如周邊走線PL1與周邊走線PL2,且部分的周邊走線經由孔洞與位於基板100另一側的訊號線(未繪示)電性連接。舉例來說,位於周邊區PA的周邊走線PL2是經由孔洞H8來實現與基板100另一側的訊號線的電性連接關係。透過在周邊走線PL1與周邊走線PL2之間設置輔助圖案AP10,可增加孔洞H8與周邊走線PL1之間的基板挺性與耐撓曲性。In this embodiment, the
圖11是本發明的第九實施例的畫素陣列基板的俯視示意圖。請參照圖11,本實施例的畫素陣列基板17A與圖1的畫素陣列基板10的主要差異在於:輔助圖案的設置方式不同。具體而言,畫素陣列基板17A的導電圖案CP2的相對兩側分別設有輔助圖案AP91與輔助圖案AP92,且這些輔助圖案並未設置在多個孔洞間的虛擬連線(例如虛擬連線CL1)上。也就是說,輔助圖案AP91與輔助圖案AP92是用於增加訊號走線(例如訊號線SL2)周邊的基板挺性與耐撓曲性。FIG. 11 is a schematic top view of a pixel array substrate according to a ninth embodiment of the present invention. Referring to FIG. 11, the main difference between the
另一方面,類似於圖10的畫素陣列基板17,畫素陣列基板17A的輔助圖案也可設置於周邊區PA,用以增加周邊走線間的基板挺性與耐撓曲性。舉例來說,周邊走線PL1的相對兩側也可分別設有輔助圖案AP93與輔助圖案AP94。在本實施例中,輔助圖案AP91、輔助圖案AP92、輔助圖案AP93、輔助圖案AP94與導電圖案CP1可選擇性地屬於同一膜層,但不以此為限。On the other hand, similar to the
圖12是本發明的第十實施例的畫素陣列基板的俯視示意圖。圖13是圖12的畫素陣列基板的俯視示意圖。特別說明的是,為清楚呈現起見,圖12省略了圖13的絕緣層110、閘絕緣層120、層間絕緣層130、平坦層140、主動元件T、連接墊BP1、連接墊BP2’及發光元件LED的繪示,且圖12的訊號線SL2與訊號線SL3是以虛線的方式呈現。FIG. 12 is a schematic top view of a pixel array substrate according to a tenth embodiment of the present invention. FIG. 13 is a schematic top view of the pixel array substrate of FIG. 12. In particular, for the sake of clarity, FIG. 12 omits the insulating
請參照圖12及圖13,本實施例的畫素陣列基板18與圖1及圖2的畫素陣列基板10的差異在於:訊號線的配置方式不同。具體而言,畫素陣列基板18的多條訊號線的一部分可設置在基板100的第一表面100a的一側。舉例來說,用以驅動主動元件T的閘極G的多條訊號線SL1”是設置在基板100的第一表面100a上,且這些訊號線SL1”與主動元件T的閘極G屬於同一膜層。也因此,畫素陣列基板18無須設置圖1的導電圖案CP1以及重疊於導電圖案CP1的孔洞(例如孔洞H1與孔洞H2)。12 and FIG. 13, the difference between the
在本實施例中,畫素陣列基板18還可包括多條訊號線SL3,設置於基板100的第二表面100b的一側。訊號線SL3與訊號線SL2在方向X上交替排列。訊號線SL3經由孔洞H9與連接墊BP2’電性連接。更具體地說,訊號線SL3可以是用於傳輸電壓源(例如Vss)的電源線(power line)。應注意的是,這些訊號線SL2’與訊號線SL3在方向Z上不重疊於導電圖案(例如導電圖案CP2)與輔助圖案(例如輔助圖案AP2與輔助圖案AP3)。據此,當畫素陣列基板18撓曲時,可將產生的應力均勻地分散於基板100的相對兩側(即第一表面100a與第二表面100b的兩側),有助於增加基板的挺性與耐撓曲性。In this embodiment, the
圖14是本發明的第十一實施例的畫素陣列基板的俯視示意圖。請參照圖14,本實施例的畫素陣列基板19與圖10的畫素陣列基板17的差異在於:訊號線的配置方式不同。在本實施例中,畫素陣列基板19的訊號線SL1A與訊號線SL2’在方向Z上不重疊於導電圖案(例如導電圖案CP1A與導電圖案CP2)與輔助圖案(例如輔助圖案AP2、輔助圖案AP3與輔助圖案AP9)。據此,當畫素陣列基板19撓曲時,可將產生的應力均勻地分散於基板100的相對兩側(即第一表面100a與第二表面100b的兩側),有助於增加基板的挺性與耐撓曲性。FIG. 14 is a schematic top view of a pixel array substrate according to an eleventh embodiment of the present invention. Please refer to FIG. 14, the difference between the
綜上所述,在本發明的一實施例的畫素陣列基板中,位於基板相對兩側的多個導電圖案與多條訊號線的電性連接關係是經由貫穿基板的多個孔洞來實現。當畫素陣列基板被撓曲時,這些孔洞的虛擬連線上所設置的輔助圖案,可避免應力集中在這些孔洞之間而使附近的膜層產生裂縫。換句話說,可增加基板在孔洞邊緣附近的區域的挺性,據以提升畫素陣列基板的耐撓曲性。In summary, in the pixel array substrate of an embodiment of the present invention, the electrical connection relationship between the plurality of conductive patterns on the opposite sides of the substrate and the plurality of signal lines is achieved through a plurality of holes penetrating the substrate. When the pixel array substrate is flexed, the auxiliary patterns provided on the virtual lines of the holes can prevent the stress from being concentrated between the holes and causing cracks in the nearby film. In other words, the stiffness of the substrate near the edge of the hole can be increased, thereby improving the flexibility resistance of the pixel array substrate.
10、11、12、13、14、15、16、17、17A、18、19:畫素陣列基板
100:基板
100a:第一表面
100b:第二表面
110:絕緣層
120:閘絕緣層
130:層間絕緣層
140:平坦層
AA:顯示區
AP1、AP1”、AP1a、AP1b、AP1c、AP11、AP12、AP1L、AP1R、AP2、AP2’、AP2”、AP21、AP22、AP2L、AP2R、AP3、AP3”、AP4、AP5、AP6、AP71、AP72、AP81、AP82、AP9、AP91、AP92、AP93、AP94、AP10:輔助圖案
AP1La、AP1Ra、AP2La、AP2Ra、AP72a、AP82a:第一延伸段
AP1Lb、AP1Rb、AP2Lb、AP2Rb、AP72b、AP82b:第二延伸段
BP1、BP2、BP2’:連接墊
CH:通道區
CL1、CL2、CL3、CL4、CL5、CL6、CL7、CL8、CL9:虛擬連線
CP1、CP11、CP12、CP1A、CP2、CP21、CP22:導電圖案
D:汲極
DR:汲極區
ES:磊晶結構
E1:第一電極
E2:第二電極
G:閘極
H1、H1’、H1”、H2、H2’、H2”、H3、H3’、H4、H4’、H5、H6、H7、H8、H9:孔洞
LED:發光元件
PA:周邊區
PL1、PL2:周邊走線
PX:畫素結構
S:源極
SC:半導體圖案
SL1、SL1’、SL1”、SL1A、SL2、SL2’、SL3:訊號線
SR:源極區
T:主動元件
X、X’、Y、Y’、Z:方向10, 11, 12, 13, 14, 15, 16, 17, 17A, 18, 19: pixel array substrate
100:
圖1是本發明的第一實施例的畫素陣列基板的俯視示意圖。 圖2是圖1的畫素陣列基板的剖視示意圖。 圖3是本發明的第二實施例的畫素陣列基板的俯視示意圖。 圖4是本發明的第三實施例的畫素陣列基板的俯視示意圖。 圖5是本發明的第四實施例的畫素陣列基板的俯視示意圖。 圖6是本發明的第五實施例的畫素陣列基板的俯視示意圖。 圖7是本發明的第六實施例的畫素陣列基板的俯視示意圖。 圖8是圖7的畫素陣列基板的剖視示意圖。 圖9是本發明的第七實施例的畫素陣列基板的俯視示意圖。 圖10是本發明的第八實施例的畫素陣列基板的俯視示意圖。 圖11是本發明的第九實施例的畫素陣列基板的俯視示意圖。 圖12是本發明的第十實施例的畫素陣列基板的俯視示意圖。 圖13是圖12的畫素陣列基板的俯視示意圖。 圖14是本發明的第十一實施例的畫素陣列基板的俯視示意圖。 FIG. 1 is a schematic top view of a pixel array substrate according to a first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of the pixel array substrate of FIG. 1. FIG. 3 is a schematic top view of a pixel array substrate according to a second embodiment of the present invention. 4 is a schematic top view of a pixel array substrate according to a third embodiment of the present invention. FIG. 5 is a schematic top view of a pixel array substrate according to a fourth embodiment of the present invention. FIG. 6 is a schematic top view of a pixel array substrate according to a fifth embodiment of the present invention. FIG. 7 is a schematic top view of a pixel array substrate according to a sixth embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of the pixel array substrate of FIG. 7. FIG. 9 is a schematic top view of a pixel array substrate according to a seventh embodiment of the present invention. FIG. 10 is a schematic top view of a pixel array substrate according to an eighth embodiment of the present invention. FIG. 11 is a schematic top view of a pixel array substrate according to a ninth embodiment of the present invention. FIG. 12 is a schematic top view of a pixel array substrate according to a tenth embodiment of the present invention. FIG. 13 is a schematic top view of the pixel array substrate of FIG. 12. FIG. 14 is a schematic top view of a pixel array substrate according to an eleventh embodiment of the present invention.
10:畫素陣列基板 10: Pixel array substrate
100:基板 100: substrate
AP1、AP2、AP3:輔助圖案 AP1, AP2, AP3: auxiliary pattern
CL1、CL2:虛擬連線 CL1, CL2: Virtual connection
CP1、CP11、CP12、CP2、CP21、CP22:導電圖案 CP1, CP11, CP12, CP2, CP21, CP22: conductive pattern
H1、H2、H3、H4:孔洞 H1, H2, H3, H4: holes
SL1、SL2:訊號線 SL1, SL2: signal line
X、Y、Z:方向 X, Y, Z: direction
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