TW202127655A - Display apparatus and fabricating method thereof - Google Patents

Abstract

A display apparatus includes a pixel driving circuit, at least one first circuit electrode, at least one second circuit electrode, at least one first conductive pattern, at least one second conductive pattern and a light-emitting diode element. The pixel driving circuit includes a power line, a transistor and a common line, wherein a first end of the transistor is electrically connected to the power line. The at least one first circuit electrode is electrically connected to at least one of a second end of the transistor and the common line. The at least one second circuit electrode is electrically connected to at least one of the power line and the common line. The at least one first conductive pattern is disposed on the at least one first circuit electrode, and is electrically connected to the at least one first circuit electrode. The at least one second conductive pattern is disposed on the at least one second circuit electrode, and is electrically connected to the at least one second circuit electrode. A material of the at least one first conductive pattern is the same as a material of the at least one second conductive pattern, and a thickness of the at least one first conductive pattern and a thickness of the at least one second conductive pattern have a difference. The light-emitting diode element is disposed on the at least one first conductive pattern and is electrically connected to the at least one first conductive pattern. A fabricating method of the above display apparatus is also provided.

Description

Display device and manufacturing method thereof

The present invention relates to a photoelectric device and a manufacturing method thereof, and more particularly to a display device and a manufacturing method thereof.

The light-emitting diode display panel includes a driving backplane and a plurality of light-emitting diode elements transferred to the driving backplane. Inheriting the characteristics of light-emitting diodes, light-emitting diode display panels have the advantages of power saving, high efficiency, high brightness and fast response time. In addition, compared with organic light-emitting diode display panels, light-emitting diode display panels also have advantages such as easy color adjustment, long light-emitting life, and no image burn-in. Therefore, the LED display panel is regarded as the next generation of display technology. However, the transposition yield of the light-emitting diode elements of the light-emitting diode display panel still needs to be improved.

The invention provides a display device with a high transposition yield of light-emitting diode elements.

The present invention provides a method for manufacturing a display device, which has a high transposition yield of light-emitting diode elements.

A display device of the present invention includes a substrate, a pixel driving circuit arranged on the substrate, a dielectric layer, at least one first circuit electrode, at least one second circuit electrode, at least one first conductive pattern, and at least one second conductive pattern. Patterns and light-emitting diode components. The pixel driving circuit includes a power line, a transistor, and a common line, wherein the first end of the transistor is electrically connected to the power line. The dielectric layer is arranged on the pixel driving circuit. At least one first circuit electrode is disposed on the dielectric layer and is electrically connected to at least one of the second end of the transistor and the common line. At least one second circuit electrode is disposed on the dielectric layer and is electrically connected to at least one of the power line and the common line. At least one first conductive pattern is disposed on at least one first circuit electrode, and is electrically connected to at least one first circuit electrode. At least one second conductive pattern is disposed on at least one second circuit electrode, and is electrically connected to at least one second circuit electrode. The material of the at least one first conductive pattern is the same as the material of the at least one second conductive pattern, and the thickness of the at least one first conductive pattern and the thickness of the at least one second conductive pattern have a difference. The light emitting diode element is arranged on at least one first conductive pattern and is electrically connected to the at least one first conductive pattern.

In an embodiment of the present invention, the aforementioned at least one first circuit electrode includes a plurality of first circuit electrodes, and the plurality of first circuit electrodes are electrically connected to the second end of the transistor and the common line, respectively, and the plurality of first circuit electrodes The circuit electrodes have a first distance in one direction; at least one second circuit electrode includes a second circuit electrode electrically connected to the common line, and the second circuit electrode and a first circuit electrode electrically connected to the common line are on the structure They are separated and have a second pitch in the direction, and the second pitch is smaller than the first pitch.

In an embodiment of the present invention, the aforementioned at least one first conductive pattern includes a plurality of first conductive patterns respectively disposed on a plurality of first circuit electrodes; at least one second conductive pattern includes a plurality of first conductive patterns disposed on a second circuit electrode The second conductive pattern; the first conductive pattern electrically connected to the common line is in contact with the second conductive pattern.

In an embodiment of the present invention, the above-mentioned first conductive pattern electrically connected to the second end of the transistor has an extension part that extends beyond a first circuit electrode. The extension of the first conductive pattern has a first length in the direction. The second conductive pattern has an extension part beyond a second circuit electrode. The extension of the second conductive pattern has a second length in the direction. The second distance is less than or equal to the sum of the first length and the second length.

In an embodiment of the present invention, the above-mentioned first conductive pattern electrically connected to the second end of the second transistor has an extension that extends beyond a first circuit electrode, and the extension of the first conductive pattern is in the The direction has a first length, and the first distance is greater than twice the first length.

In an embodiment of the present invention, the above-mentioned at least one first circuit electrode includes a plurality of first circuit electrodes electrically connected to the second end of the transistor and the common line, and the at least one first conductive pattern includes The plurality of first conductive patterns on the plurality of first circuit electrodes, a first electrode and a second electrode of the light-emitting diode element are electrically connected to the plurality of first conductive patterns, and a plurality of the plurality of first conductive patterns The thickness is different.

。In an embodiment of the present invention, the absolute value of the aforementioned difference is greater than or equal to

.

且小於或等於

。In an embodiment of the present invention, the absolute value of the aforementioned difference is greater than or equal to

And less than or equal to

.

A method of manufacturing a display device of the present invention includes the following steps: providing a driving backplane, which includes a substrate, a pixel driving circuit, a dielectric layer, at least one first circuit electrode and at least one second circuit electrode, and the pixel The driving circuit is arranged on the substrate. The pixel driving circuit includes a power line, a transistor and a common line. The transistor has a first end, a second end and a control end. The first end of the transistor is electrically connected to the power line. The layer is disposed on the pixel driving circuit, at least one first circuit electrode is disposed on the dielectric layer and is electrically connected to at least one of the second end of the transistor and the common line, and at least one second circuit electrode is disposed on the dielectric Layer and electrically connected to at least one of the power line and the common line; using an electroplating process to form at least one first conductive pattern and at least one A second conductive pattern, wherein the material of the at least one first conductive pattern is the same as the material of the at least one second conductive pattern, and the thickness of the at least one first conductive pattern and the thickness of the at least one second conductive pattern have a difference; A light emitting diode element is placed on the at least one first conductive pattern, and the light emitting diode element is electrically connected to the at least one first conductive pattern.

In an embodiment of the present invention, the above-mentioned step of forming at least one first conductive pattern and at least one second conductive pattern on at least one first circuit electrode and at least one second circuit electrode of the driving backplane by the electroplating process, respectively Including: providing at least one first signal and at least one second signal to at least one first circuit electrode and at least one second circuit electrode respectively, wherein the electroplating process includes at least a first stage; in the first stage of the electroplating process, at least one The first signal and the at least one second signal respectively include a plurality of first pulses and a plurality of second pulses, the plurality of first pulses have a first period t1p, each first pulse has a time length t1, and a plurality of second pulses The pulse has a second period t2p, each second pulse signal has a time length t2, T1 is the time of the first stage of the electroplating process, and (T1/t1p)∙t1≠(T1/t2p)∙t2.

In an embodiment of the present invention, the aforementioned first period t1p is different from the second period t2p.

In an embodiment of the present invention, the above-mentioned step of forming at least one first conductive pattern and at least one second conductive pattern on at least one first circuit electrode and at least one second circuit electrode of the driving backplane by the electroplating process, respectively It further includes: after a first conductive pattern is in contact with a second conductive pattern, the electroplating process enters a second stage following the first stage; in the second stage of the electroplating process, the first signal and the second signal are substantially the same.

Reference will now be made in detail to the exemplary embodiments of the present invention, and examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and descriptions to indicate the same or similar parts.

It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connected" can refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that there are other elements between two elements.

As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within the acceptable deviation range of the specific value determined by a person of ordinary skill in the art, taking into account the measurement in question and the The specific amount of measurement-related error (ie, the limitation of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "about", "approximately" or "substantially" as used herein can be based on optical properties, etching properties or other properties to select a more acceptable range of deviation or standard deviation, and not one standard deviation can be applied to all properties .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of related technologies and the present invention, and will not be interpreted as idealized or excessive The formal meaning, unless explicitly defined as such in this article.

1A to 1D are schematic cross-sectional views of the manufacturing process of the display device 10 according to an embodiment of the invention.

Please refer to FIG. 1A. First, a driving backplane 100 is provided. The driving backplane 100 includes a substrate 110, a pixel driving circuit 120, a dielectric layer 130, at least one first circuit electrode 141, 142, and at least one second circuit electrode 143.

The pixel driving circuit 120 is disposed on the substrate 110. For example, in this embodiment, the material of the substrate 110 may be glass, quartz, organic polymers, or opaque/reflective materials (for example, wafers, ceramics, or other applicable materials), or Other applicable materials.

FIG. 2 is a schematic circuit diagram of a pixel driving circuit 120 according to an embodiment of the invention. 1A and FIG. 2, the pixel driving circuit 120 includes a power line L_VDD, a transistor TFT2, and a common line L_VSS, wherein the transistor TFT2 has a first terminal T2a, a second terminal T2b, and a control terminal T2c. The first terminal T2a of the crystal TFT2 is electrically connected to the power line L_VDD.

For example, in this embodiment, the pixel driving circuit 120 may also include two other transistors TFT1, TFT3, a capacitor C, a data line DL, a scan line GL, a signal line L_SEL, and a signal line L_SEN. , Wherein the first terminal T1a of the transistor TFT1 is electrically connected to the data line DL, the control terminal T1c of the transistor TFT1 is electrically connected to the scan line GL, and the second terminal T1b of the transistor TFT1 is electrically connected to the control of the transistor TFT2 Terminal T2c, the second terminal T2b of the transistor TFT2, the second terminal T3b of the transistor TFT3, the first terminal T3a of the transistor TFT3 is electrically connected to the signal line L_SEN, and the control terminal T3c of the transistor TFT3 is electrically connected to the signal line L_SEL One end Ca of the capacitor C is electrically connected to the second end T1b of the transistor TFT1 and the control end T2c of the transistor TFT2, and the other end Cb of the capacitor C is electrically connected to the first end T2a of the transistor TFT2.

In short, in this embodiment, the pixel driving circuit 120 adopts a structure of three transistors and one capacitor (3T1C). However, the present invention is not limited to this. In other embodiments, the pixel driving circuit 120 may also adopt any other possible architectures, such as but not limited to: a transistor and a capacitor (1T1C) architecture, two transistors and One capacitor (2T1C) architecture, three transistors and two capacitors (3T2C) architecture, four transistors and one capacitor (4T1C) architecture, four transistors and two capacitors (4T2C) architecture, five One transistor and one capacitor (5T1C), five transistors and two capacitors (5T2C), six transistors and one capacitor (6T1C), or seven transistors and two capacitors (7T2C) Architecture.

1A, the dielectric layer 130 is disposed on the pixel driving circuit 120. The pixel driving circuit 120 is located between the dielectric layer 130 and the substrate 110. For example, in this embodiment, the material of the dielectric layer 130 can be an inorganic material (for example: silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the foregoing materials), organic material, or any of the foregoing materials. combination.

1A and FIG. 2, at least one first circuit electrode 141, 142 is disposed on the dielectric layer 130 and is electrically connected to at least one of the second terminal T2b of the transistor TFT2 and the common line L_VSS. Specifically, in this embodiment, at least one first circuit electrode 141, 142 includes a first circuit electrode 141 and a first circuit electrode 142, and the first circuit electrode 141 is electrically connected to the contact window 131a of the dielectric layer 130 The second terminal T2b of the transistor TFT2 of the pixel driving circuit 120 and the second terminal T3b of the transistor TFT3 (ie, the point P141 of the pixel driving circuit 120 of FIG. 2), and the first circuit electrode 142 penetrates the dielectric layer 130 The contact window 131b is electrically connected to the common line L_VSS of the pixel driving circuit 120 (ie, the point P142 of the pixel driving circuit 120 in FIG. 2). The first circuit electrode 141 and the first circuit electrode 142 are two electrodes for electrically connecting with the light emitting diode device 200 (drawn in FIG. 1D ).

1A and FIG. 2, at least one second circuit electrode 143 is disposed on the dielectric layer 130 and is electrically connected to at least one of the power line L_VDD and the common line L_VSS. Specifically, in this embodiment, at least one second circuit electrode 143 includes a second circuit electrode 143, wherein the second circuit electrode 143 is electrically connected to the pixel driving circuit 120 through the contact window 132a of the dielectric layer 130 The power supply line L_VDD (ie, the point P143 of the pixel driving circuit 120 in FIG. 2). The second circuit electrode 143 is a part of the power path.

FIG. 3 shows the electroplating process of the driving backplane 100 according to an embodiment of the present invention.

Please refer to FIGS. 1B and 3, then, at least one first conductive pattern 151, 151 is formed on at least one first circuit electrode 141, 142 and at least one second circuit electrode 143 of the driving backplane 100 by an electroplating process, respectively 152 and at least one second conductive pattern 153, wherein at least one first conductive pattern 151, 152 and at least one second conductive pattern 153 are electrically connected to at least one first circuit electrode 141, 142 and at least one second circuit electrode 143, respectively . In other words, at least one first circuit electrode 141, 142 and at least one second circuit electrode 143 of the driving backplane 100 are used as a seed layer in the electroplating process. During the electroplating process, the electroplated metal ions of the electroplated metal 300 (shown in FIG. 3) can be eluted, and then accumulated on at least one first circuit electrode 141, 142 and at least one second circuit electrode 143 to form at least one first circuit electrode. The conductive patterns 151 and 152 and at least one second conductive pattern 153.

The at least one first conductive pattern 151, 152 and the at least one second conductive pattern 153 are completed in the same electroplating process, and the material of the at least one first conductive pattern 151, 152 is the same as the material of the at least one second conductive pattern 153 same. For example, in this embodiment, the material of the at least one first conductive pattern 151, 152 and the material of the at least one second conductive pattern 153 may both be copper. However, the present invention is not limited to this. In other embodiments, the material of the at least one first conductive pattern 151, 152 and the material of the at least one second conductive pattern 153 may also be other conductive materials, such as but not limited to: zinc (Zn ), chromium (Cr) or silver (Ag).

。也就是說，至少一第一導電圖案151、152的頂面151a、152a與至少一第二導電圖案153的頂面153a具有高低差。在本實施例中，所述差值的絕對值

以大於或等於

為佳；舉例而言，差值的絕對值

可大於或等於

且小於或等於

；但本發明不以此為限。1B, it is worth noting that the thickness H11, H12 of the at least one first conductive pattern 151, 152 and the thickness H21 of the at least one second conductive pattern 153 have a difference

. That is, the top surface 151a, 152a of the at least one first conductive pattern 151, 152 and the top surface 153a of the at least one second conductive pattern 153 have a height difference. In this embodiment, the absolute value of the difference

To be greater than or equal to

Is better; for example, the absolute value of the difference

Can be greater than or equal to

And less than or equal to

; But the present invention is not limited to this.

For example, in this embodiment, the thickness H11, H12 of the first conductive pattern 151, 152 can be selectively greater than the thickness H21 of the at least one second conductive pattern 143; however, the present invention is not limited to this, in other embodiments In this case, the thickness H11 and H12 of the first conductive patterns 151 and 152 may also be smaller than the thickness H21 of the at least one second conductive pattern 143.

In addition, in this embodiment, the thickness H11 of the first conductive pattern 151 and the thickness H12 of the first conductive pattern 152 may be substantially the same; however, the present invention is not limited to this. In other embodiments, the thickness H11 of the first conductive pattern 151 The thickness H11 and the thickness H12 of the first conductive pattern 152 may also be different.

1B, FIG. 2, FIG. 4, FIG. 5, and FIG. 6 to illustrate how to form at least one first conductive pattern 151, 152 and at least one second conductive pattern 153 with different thicknesses in the same electroplating process.

FIG. 4 shows the signal V11 applied to the signal line L_SEN of the pixel driving circuit 120 (drawn in FIG. 2) of an embodiment of the present invention during the electroplating process.

FIG. 5 shows the signal V12 applied to the common line L_VSS of the pixel driving circuit 120 (drawn in FIG. 2) of an embodiment of the present invention during the electroplating process.

FIG. 6 shows the signal V21 applied to the power line L_VDD of the pixel driving circuit 120 (drawn in FIG. 2) of an embodiment of the present invention during the electroplating process.

Please refer to FIG. 1B, FIG. 2, FIG. 4, FIG. 5, and FIG. 6. In this embodiment, during the electroplating process, a gate very high voltage can be input to the data line DL, and a gate low voltage is input to the scan line GL, input a gate low voltage to the signal line L_SEL, input the signal V11 of FIG. 4 to the signal line L_SEN, input the signal V12 of FIG. 5 to the common line L_VSS, and input the signal V21 of FIG. 6 to the power line L_VDD. At this time, the first signal provided to the first circuit electrode 141 (or point P141) is substantially equal to the signal V11 in FIG. 4, and the first signal provided to the first circuit electrode 142 (or point P142) It is substantially equal to the signal V12 of FIG. 5 and the second signal provided to the second circuit electrode 143 (or point P143) is substantially equal to the signal V21 of FIG. 6.

4, the signal V11 includes a plurality of first pulses, the plurality of first pulses of the signal V11 have a first period t11p, and each first pulse has a time length t11. Referring to FIG. 6, the signal V21 includes a plurality of second pulses, the plurality of second pulses have a second period t21p, and each second pulse signal has a time length t21. Please refer to Figures 4 and 6, in particular, t11p, t11, t21p, and t21 satisfy the following formula: (T1/t11p)∙t11≠(T1/t21p)∙t21, where T1 is the time of the first stage of the electroplating process. In this embodiment, the time T1 of the first stage of the electroplating process is the total time of the electroplating process.

Please refer to Figure 1B, Figure 4 and Figure 6, (T1/t11p)∙t11≠(T1/t21p)∙t21, which means the time during which voltage is applied to the first circuit electrode 141 in the same plating process (for example: in the plating process The sum of the multiple time lengths t11 of the multiple first pulses of the signal V11 and the voltage applied time to the second circuit electrode 143 (for example: in the total time of the electroplating process, the multiple first pulses of the signal V21 The sum of the multiple time lengths t21 of the two pulses is different. Thereby, the amount of electroplating metal ions accumulated on the first circuit electrode 141 is different from the amount of electroplating metal ions accumulated on the second circuit electrode 143, so that the amount of electroplating metal ions accumulated on the first circuit electrode 141 and the second circuit electrode 143 is different. The thicknesses H11 and H21 of the first conductive pattern 151 and the second conductive pattern 153 are different.

For example, in this embodiment, t11p, t11, t21p, and t21 may satisfy the following formula: (T1/t11p)∙t11>(T1/t21p)∙t21, so that the thickness H11 of the first conductive pattern 151 is greater than that of the first conductive pattern 151 The thickness of the two conductive patterns 153 is H21. However, the present invention is not limited to this. In other embodiments, t11p, t11, t21p, and t21 may also satisfy the following formula: (T1/t11p)∙t11<(T1/t21p)∙t21, so that the first conductive pattern 151 The thickness H11 is smaller than the thickness H21 of the second conductive pattern 153.

Please refer to Figure 4 and Figure 6, so that t11p, t11, t21p and t21 satisfy the following formula: (T1/t11p)∙t11≠(T1/t21p)∙t21 There are many ways. For example, in this embodiment, the time length t11 of each first pulse of the signal V11 can be substantially equal to the time length t21 of each second pulse of the signal V21, and the first period t11p is different from the second period t21p (That is, the frequency of the first pulses of the signal V11 is different from the frequency of the second pulses of the signal V21). However, the present invention is not limited to this. In another embodiment, the time length t11 of each first pulse of the signal V11 and the time length t21 of each second pulse of the signal V21 may be different, and the first period t11p and the first period t11p may be different from each other. The two periods t21p may be the same; in another embodiment, the time length t11 of each first pulse of the signal V11 and the time length t21 of each second pulse of the signal V21 may be different, and the first period t1p and the second period t2p can also be different, as long as t11p, t11, t21p and t21 satisfy the following formula: (T1/t11p)∙t11≠(T1/t21p)∙t21.

5, the signal V12 includes a plurality of first pulses, the plurality of first pulses of the signal V12 have a first period t12p, and each first pulse has a time length t12. Referring to FIG. 6, the signal V21 includes a plurality of second pulses, the plurality of second pulses have a second period t21p, and each second pulse signal has a time length t21. Please refer to Figures 5 and 6, in particular, t12p, t12, t21p, and t21 satisfy the following formula: (T1/t12p)∙t12≠(T1/t21p)∙t21, where T1 is the time of the first stage of the electroplating process. In this embodiment, the time T1 of the first stage of the electroplating process is the total time of the electroplating process.

Please refer to Figure 1B, Figure 5 and Figure 6, (T1/t12p)∙t12≠(T1/t21p)∙t21, which means the time during which voltage is applied to the first circuit electrode 142 in the same plating process (for example: in the plating process The sum of the multiple time lengths t12 of the multiple first pulses of the signal V12 and the voltage applied time to the second circuit electrode 143 (for example: in the total time of the electroplating process, the multiple first pulses of the signal V21 The sum of the multiple time lengths t21 of the two pulses is different. Thereby, the amount of electroplating metal ions accumulated on the first circuit electrode 142 and the amount of electroplating metal ions accumulated on the second circuit electrode 143 will be different, so that the amount of electroplating metal ions accumulated on the first circuit electrode 142 and the second circuit electrode are formed respectively. The thickness H12 and H21 of the first conductive pattern 152 and the second conductive pattern 153 on the 143 are different.

For example, in this embodiment, t12p, t12, t21p, and t21 may satisfy the following formula: (T1/t12p)∙t12>(T1/t21p)∙t21, so that the thickness H12 of the first conductive pattern 152 is greater than that of the first conductive pattern 152 The thickness of the two conductive patterns 153 is H21. However, the present invention is not limited to this. In other embodiments, t12p, t12, t21p, and t21 may also satisfy the following formula: (T1/t12p)∙t12<(T1/t21p)∙t21, so that the first conductive pattern 152 The thickness H12 of the second conductive pattern 153 is smaller than the thickness H21 of the second conductive pattern 153.

Please refer to Figure 5 and Figure 6, there are many ways to make t12p, t12, t21p and t21 satisfy: (T1/t12p)∙t12≠(T/t21p)∙t21. For example, in this embodiment, the time length t12 of each first pulse of the signal V12 can be substantially equal to the time length t21 of each second pulse of the signal V21, and the first period t12p is different from the second period t21p (That is, the frequency of the multiple first pulses of the signal V12 is different from the frequency of the multiple second pulses of the signal V21). However, the present invention is not limited to this. In another embodiment, the time length t12 of each first pulse of the signal V12 and the time length t21 of each second pulse of the signal V21 may be different, and the first period t12p and the first period t12p The two periods t21p can be the same; in another embodiment, the time length t12 of each first pulse of the signal V12 and the time length t21 of each second pulse of the signal V21 can be different, and the first period t12p and the second period t21p can also be different, as long as t12p, t12, t21p and t21 satisfy the following formula: (T1/t12p)∙t12≠(T1/t21p)∙t21.

1B, 4, and 5, in this embodiment, the signal V11 and the signal V12 can optionally be substantially the same, so that the thickness H11 of the first conductive pattern 151 is substantially equal to the thickness of the first conductive pattern 152 H12. However, the present invention is not limited to this. In other embodiments, the signal V11 and the signal V12 may also be different, so that the thickness H11 of the first conductive pattern 151 and the thickness H12 of the first conductive pattern 152 are different.

Please refer to FIG. 1C. Then, in this embodiment, a chemical plating process may be selectively performed to form a first conductive pattern 151, a first conductive pattern 152, and a second conductive pattern 153. The connection pattern 161, the first connection pattern 162 and the second connection pattern 163. The first connection pattern 161 covers the top surface 151 a and the sidewall 151 b of the first conductive pattern 151. The first connection pattern 162 covers the top surface 152a and the sidewalls 152b of the first conductive pattern 152. The second connection pattern 163 covers the top surface 153 a and the sidewall 153 b of the second conductive pattern 153. In this embodiment, the stacked structure of the first connection pattern 161 and the first conductive pattern 151 can be regarded as a pad 171, and the stacked structure of the first connection pattern 162 and the first conductive pattern 152 can be regarded as a pad 172. 171 and 172 are used for bonding with the first electrode 240 and the second electrode 250 of the light emitting diode device 200 (shown in FIG. 1D ).

For example, in this embodiment, the material of the first connection pattern 161, the first connection pattern 162, and the second connection pattern 163 is tin, for example. However, the present invention is not limited thereto. In other embodiments, the material of the first connection pattern 161, the first connection pattern 162, and the second connection pattern 163 may also be other conductive materials.

1D, finally, the light emitting diode device 200 is transposed on at least one first conductive pattern 151, 152, and the light emitting diode device 200 is electrically connected to the at least one first conductive pattern 151, 152, This completes the display device 10.

The light emitting diode element 200 includes a first type semiconductor layer 210, a second type semiconductor layer 220, an active layer 230 located between the first type semiconductor layer 210 and the second type semiconductor layer 220, and a first type semiconductor layer 210 electrically connected to each other. The first electrode 240 is electrically connected and the second electrode 250 is electrically connected to the second-type semiconductor layer 220. For example, in this embodiment, an eutectic bonding process can be used to make the first electrode 240 and the second electrode 250 of the light emitting diode device 200 electrically connected to the first conductive pattern 151 and the second conductive pattern 151 and the second electrode, respectively. Two conductive patterns 152. However, the present invention is not limited to this. In other embodiments, the light emitting diode device 200 may also be electrically connected to the first conductive pattern 151 and the first conductive pattern 152 in other ways.

It is worth mentioning that since the thickness H11, H12 of the at least one first conductive pattern 151, 152 and the thickness H21 of the at least one second conductive pattern 153 have a difference, therefore, when the light emitting diode element 200 is transferred to the first When one conductive pattern 151, 152 is on, the light emitting diode element 200 is not easily short-circuited with the second conductive pattern 153 and/or other conductive elements. In this way, the transposition yield of the light-emitting diode device 200 can be improved.

In addition, in this embodiment, since the thicknesses H11, H12 of the first conductive patterns 151, 152 are thicker and have a larger surface area, the electroless plating layer deposited on the surface of the first conductive patterns 151, 152 (ie, The amount of the first connection pattern 161 and the second connection pattern 162) is relatively large, which helps the first electrode 240 and the second electrode 250 of the light emitting diode device 200 and the first conductive pattern 151 and the first conductive pattern 152 Electrical connection.

It must be noted here that the following embodiments use the element numbers and part of the content of the foregoing embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

7A to 7E are schematic cross-sectional views of the manufacturing process of the display device 10A according to an embodiment of the invention.

Please refer to FIG. 7A. First, a driving backplane 100A is provided. The driving backplane 100A of this embodiment is slightly different from the aforementioned driving backplane 100. Specifically, in this embodiment, the driving backplane 100A includes a substrate 110, a pixel driving circuit 120A disposed on the substrate 110, a dielectric layer 130 disposed on the pixel driving circuit 120A, and a dielectric layer 130 disposed on the dielectric layer 130. At least one first circuit electrode 141, 142 thereon and at least one second circuit electrode 144 arranged on the dielectric layer 130. Different from the aforementioned driving backplane 100, the pixel driving circuit 120A of the driving backplane 100A of this embodiment is different from the pixel driving circuit 120 of the driving backplane 100 of the aforementioned embodiment.

FIG. 8 is a schematic circuit diagram of a pixel driving circuit 120A according to an embodiment of the invention. 7A and 8, the pixel driving circuit 120A includes a power line L_VDD, a transistor TFT2, and a common line L_VSS. The transistor TFT2 has a first terminal T2a, a second terminal T2b, and a control terminal T2c, and the second terminal of the transistor TFT2 One end T2a is electrically connected to the power line L_VDD. In this embodiment, the pixel driving circuit 120A may further include another transistor TFT1, a capacitor C, a data line DL, and a scan line GL. The first terminal T1a of the transistor TFT1 is electrically connected to the data line DL. The control terminal T1c of TFT1 is electrically connected to the scan line GL, the second terminal T1b of the transistor TFT1 is electrically connected to the control terminal T2c of the transistor TFT2, and one end Ca of the capacitor C is electrically connected to the second terminal T1b of the transistor TFT1 And the control terminal T2c of the transistor TFT2, and the other terminal Cb of the capacitor C is electrically connected to the first terminal T2a of the transistor TFT2. In short, in this embodiment, the pixel driving circuit 120 adopts a structure of two transistors and one capacitor (2T1C).

Referring to FIG. 7A, the dielectric layer 130 is disposed on the pixel driving circuit 120A. The pixel driving circuit 120A is located between the dielectric layer 130 and the substrate 110. Referring to FIGS. 7A and 8, the second circuit electrode 144 is disposed on the dielectric layer 130 and is electrically connected to the common line L_VSS (ie, the point P144 of the pixel driving circuit 120A in FIG. 8 ). The first circuit electrodes 141 and 142 are disposed on the dielectric layer 130. The first circuit electrode 141 is electrically connected to the second terminal T2b of the transistor TFT2 (ie, the point P141 of the pixel driving circuit 120A in FIG. 8). The second circuit electrode 142 is electrically connected to the point P142 of the pixel driving circuit 120A in FIG. 8. The difference from the foregoing embodiment is that before the electroplating process has not been completed, in this embodiment, the first circuit electrode 142 is not electrically connected to the common line L_VSS (that is, the point P142 and the point P142 of the pixel driving circuit 120A in FIG. 8 Point P144 is not electrically connected).

Please refer to FIGS. 7B and 7C. Next, a first conductive pattern 151 and a first conductive pattern 152 are formed on the first circuit electrode 141, the first circuit electrode 142, and the second circuit electrode 144 of the driving backplane 100A, respectively, by an electroplating process And the second conductive pattern 154, wherein the first conductive pattern 151, the first conductive pattern 152, and the second conductive pattern 154 are electrically connected to the first circuit electrode 141, the first circuit electrode 142, and the second circuit electrode 144, respectively. The first conductive pattern 151, the first conductive pattern 152, and the second conductive pattern 154 are completed in the same electroplating process, and the materials of the first conductive pattern 151, the first conductive pattern 152, and the second conductive pattern 154 are the same.

。也就是說，第一導電圖案151、152的頂面151a、152b與第二導電圖案154的頂面154a具有高低差。在本實施例中，所述差值的絕對值

以大於或等於

為佳；舉例而言，所述差值的絕對值

可大於或等於

且小於或等於

；但本發明不以此為限。7C, it is worth noting that the thickness H11, H12 of the first conductive pattern 151, 152 and the thickness H22 of the second conductive pattern 154 have a difference

. In other words, the top surfaces 151a, 152b of the first conductive patterns 151, 152 and the top surfaces 154a of the second conductive patterns 154 have a height difference. In this embodiment, the absolute value of the difference

To be greater than or equal to

Is better; for example, the absolute value of the difference

Can be greater than or equal to

And less than or equal to

; But the present invention is not limited to this.

7B, FIG. 7C, FIG. 8, FIG. 9, FIG. 10, and FIG. 11, examples of how to form first conductive patterns 151, 152 and second conductive patterns 154 with different thicknesses in the same electroplating process, and make the first The circuit electrode 142 is electrically connected to the common line L_VSS of the pixel driving circuit 120A.

FIG. 9 shows the signal V11 applied to the power line L_VDD of the pixel driving circuit 120A of an embodiment of the present invention during the electroplating process.

FIG. 10 shows the signal V12 applied to the first circuit electrode 142 of an embodiment of the present invention during the electroplating process.

FIG. 11 shows the signal V22 applied to the common line L_VSS of the pixel driving circuit 120A of an embodiment of the present invention during the electroplating process.

Please refer to Figure 7B, Figure 7C, Figure 8, Figure 9, Figure 10 and Figure 11, in this embodiment, during the electroplating process, input a gate low voltage to the data line DL, input a gate low voltage to The scan line GL inputs the signal V11 of FIG. 9 to the power line L_VDD, inputs the signal V12 of FIG. 10 to the first circuit electrode 142, and inputs the signal V22 of FIG. 11 to the common line L_VSS. At this time, the first signal provided to the first circuit electrode 141 (ie, point P141 of the pixel driving circuit 120A in FIG. 8) is substantially equal to the signal V11 in FIG. 9, and the first signal provided to the first circuit electrode 142 ( That is, the point P142 of the pixel driving circuit 120A of FIG. 8 is substantially equal to the signal V12 of FIG. 10, and the second signal provided to the second circuit electrode 144 (ie, the point P144 of the pixel driving circuit 120A of FIG. 8) It is substantially equal to the signal V22 in FIG. 11.

In this embodiment, the electroplating process may include a first stage and a second stage; in the first stage of the electroplating process, the time T1 is mainly to produce the difference in thickness between the first conductive patterns 151, 152 and the second conductive pattern 154 ; In the second stage of the electroplating process in the time T2, mainly to thicken the first conductive patterns 151, 152 and the second conductive pattern 154, and then make the first conductive pattern 152 and the second conductive pattern 154 contact, and make The first conductive pattern 152 can be electrically connected to the common line L_VSS of the pixel driving circuit 120A through the second conductive pattern 154.

7B, 9 and 11, in the first stage of the electroplating process time T1, the signal V11 includes a plurality of first pulses, the plurality of first pulses of the signal V11 have a first period t11p, and each A pulse has a time length t11; the signal V22 includes a plurality of second pulses, the plurality of second pulses have a second period t22p, and each second pulse signal has a time length t22; in particular, t11p, t11, t22p and t22 satisfies the following formula: (T1/t11p)∙t11≠(T1/t22p)∙t22, where T1 is the time of the first stage of the electroplating process.

(T1/t11p)∙t11≠(T1/t22p)∙t22, which means that the voltage is applied to the first circuit electrode 141 during the first stage of the electroplating process during the time T1 (for example: during the first stage of the time T1 , The sum of the multiple time lengths t11 of the multiple first pulses of the signal V11 and the time that the voltage is applied to the second circuit electrode 144 (for example: in the first stage of time T1, the multiple second pulses of the signal V22 The sum of the multiple time lengths t22) are different. Thereby, the amount of electroplating metal ions accumulated on the first circuit electrode 141 is different from the amount of electroplating metal ions accumulated on the second circuit electrode 144, so that the amount of electroplating metal ions accumulated on the first circuit electrode 141 and the second circuit electrode 144 are formed respectively. The thicknesses H11' and H22' of the first conductive pattern 151 and the second conductive pattern 154 above are different.

In this embodiment, t11p, t11, t22p, and t22 may satisfy the following formula: (T1/t11p)∙t11>(T1/t22p)∙t22, so that the thickness H11' of the first conductive pattern 151 is greater than that of the second conductive pattern The thickness of 154 is H22'. However, the present invention is not limited to this. In other embodiments, t11p, t11, t22p, and t22 may also satisfy: (T1/t11p)∙t11<(T1/t22p)∙t22, so that the thickness of the first conductive pattern 151 H11' is smaller than the thickness H22' of the second conductive pattern 154.

There are many ways to make t11p, t11, t22p and t22 satisfy the following formula: (T1/t11p)∙t11≠(T1/t22p)∙t22. For example, in this embodiment, the time length t11 of each first pulse of the signal V11 can be substantially equal to the time length t22 of each second pulse of the signal V22, and the first period t11p is different from the second period t22p (That is, the frequency of the first pulses of the signal V11 is different from the frequency of the second pulses of the signal V22). However, the present invention is not limited to this. In another embodiment, the time length t11 of each first pulse of the signal V11 and the time length t22 of each second pulse of the signal V22 may be different, and the first period t11p is different from the first period t11p. The two periods t22p can be the same; in another embodiment, the time length t11 of each first pulse of the signal V11 and the time length t22 of each second pulse of the signal V22 can be different, the first period t11p and the second period t22p It can also be different, as long as t11p, t11, t22p and t22 satisfy the following formula: (T1/t11p)∙t11≠(T1/t22p)∙t22.

Referring to FIGS. 7B, 10 and 11, the signal V12 includes a plurality of first pulses, the plurality of first pulses of the signal V12 have a first period t12p, and each first pulse has a time length t12. The signal V22 includes a plurality of second pulses, the plurality of second pulses have a second period t22p, and each second pulse signal has a time length t22. In particular, t12p, t12, t22p and t22 satisfy: (T1/t12p)∙t12≠(T1/t22p)∙t22, where T1 is the time of the first stage of the electroplating process.

(T1/t12p)∙t12≠(T1/t22p)∙t22, which means that the voltage is applied to the first circuit electrode 142 in the first stage of the same plating process (that is, in the first stage of time T1, The sum of the multiple time lengths t12 of the multiple first pulses of the signal V12) and the time when the voltage is applied to the second circuit electrode 144 (that is, the multiple of the multiple second pulses of the signal V22 during the first stage of time T1) The sum of the time length t22) is different. Thereby, the amount of electroplating metal ions accumulated on the first circuit electrode 142 is different from the amount of electroplating metal ions accumulated on the second circuit electrode 144, so that the amount of electroplating metal ions accumulated on the first circuit electrode 142 and the second circuit electrode 144 are formed respectively. The thicknesses H12' and H22' of the first conductive pattern 152 and the second conductive pattern 154 above are different.

For example, in this embodiment, t12p, t12, t22p, and t22 may satisfy the following formula: (T1/t12p)∙t12>(T1/t22p)∙t22, so that the thickness H12' of the first conductive pattern 152 is greater than The thickness of the second conductive pattern 154 is H22'. However, the present invention is not limited to this. In other embodiments, t12p, t12, t22p, and t22 may also satisfy: (T1/t12p)∙t12<(T1/t22p)∙t22, so that the thickness of the first conductive pattern 152 H12' is smaller than the thickness H22' of the second conductive pattern 154.

There are many ways to make t12p, t12, t22p and t22 satisfy the following formula: (T1/t12p)∙t12≠(T1/t22p)∙t22. For example, in this embodiment, the time length t12 of each first pulse of the signal V12 may be substantially equal to the time length t22 of each second pulse of the signal V22, and the first period t12p is different from the second period t22p (That is, the frequency of the multiple first pulses of the signal V12 is different from the frequency of the multiple second pulses of the signal V21). However, the present invention is not limited to this. In another embodiment, the time length t12 of each first pulse of the signal V12 and the time length t22 of each second pulse of the signal V22 may be different. The period t22p may be the same; in another embodiment, the time length t12 of each first pulse of the signal V12 and the time length t22 of each second pulse of the signal V22 may be different, and the first period t12p and the second period t22p are also It can be different, as long as t12p, t12, t22p and t22 satisfy the following formula: (T1/t12p)∙t12≠(T1/t22p)∙t22.

In addition, different from the previous embodiment, in this embodiment, the electroplating process also includes a second stage. Through the second stage of the electroplating process, the common line L_VSS of the first circuit electrode 142 and the pixel driving circuit 120A can be electrically connected. Connection (that is, the point P142 and the point P144 of the pixel driving circuit 120A in FIG. 8 are electrically connected to each other).

Please refer to FIG. 7C, FIG. 8, FIG. 9, FIG. 10, and FIG. 11. Specifically, in this embodiment, after detecting that the first conductive pattern 152 is in contact with the second conductive pattern 154, the first step The end of the time T1 of the phase, and the time T2 of the second phase of the electroplating process. After the time T2 in the second stage of the electroplating process, the signal V12 and the signal V22 can be made substantially the same, so that the signals V12 and V22 will not interfere with each other, and the first conductive pattern 152 and the second conductive pattern 154 can continue to face Thickness in multiple directions. Through the second stage of the electroplating process, the contact area of the first conductive pattern 152 and the second conductive pattern 154 is increased, so that the electrical connection between the first conductive pattern 152 and the second conductive pattern 154 is more stable. When the first conductive pattern 152 and the second conductive pattern 154 are in contact, the first conductive pattern 152 that is not electrically connected to the common line L_VSS of the pixel driving circuit 120A can pass through the second conductive pattern 154 and the second circuit electrode 144 is electrically connected to the common line L_VSS of the pixel driving circuit 120A.

12 is a schematic top view of the first circuit electrode 141, the first circuit electrode 142, the second circuit electrode 144, the first conductive pattern 151, the first conductive pattern 152, and the second conductive pattern 154 of FIG. 7B. Fig. 7B corresponds to the section line I-I' of Fig. 12.

13 is a schematic top view of the first circuit electrode 141, the first circuit electrode 142, the second circuit electrode 144, the first conductive pattern 151, the first conductive pattern 152, and the second conductive pattern 154 of FIG. 7C. Fig. 7C corresponds to the section line II-II' of Fig. 13.

Referring to FIGS. 7B and 12, in this embodiment, the plurality of first circuit electrodes 151, 152 have a first pitch Xpad in a direction d; the second circuit electrode 154 and the first circuit electrode 152 are structurally separated And there is a second pitch Xppath in the direction d, and the second pitch Xppath is smaller than the first pitch Xpad. Please refer to FIG. 7C and FIG. 13, whereby after the first stage and the second stage of the above-mentioned electroplating process are completed, the first conductive pattern 152 and the second conductive pattern 154 will be in contact, and the first conductive pattern 151 and the second conductive pattern A conductive pattern 152 does not touch.

Referring to FIGS. 7C, 8 and 13, in this embodiment, the first conductive pattern 151 electrically connected to the second terminal T2b of the transistor TFT2 has an extension 151-1 extending beyond the first circuit electrode 141. The extension 151-1 of a conductive pattern 151 has a first length D1 in the direction d, the second conductive pattern 154 has an extension 154-1 that extends beyond the second circuit electrode 144, and the extension 154-1 of the second conductive pattern 154 It has a second length D2 in the direction d, the second distance Xppath is less than or equal to the sum of the first length D1 and the second length D2, and the first distance Xpad is greater than twice the first length D1.

Please refer to FIG. 7D. Then, in this embodiment, an electroless plating process can be selectively performed to form the first connection patterns 161, 161, and 161 on the first conductive pattern 151, the first conductive pattern 152, and the second conductive pattern 154. The first connection pattern 162 and the second connection pattern 164.

Referring to FIG. 7E, finally, the light emitting diode device 200 is transposed on at least one first conductive pattern 151, 152, and the light emitting diode device 200 is electrically connected to the at least one first conductive pattern 151, 152. This completes the display device 10A.

The display device 10A has similar functions and advantages as the aforementioned display device 10, and will not be repeated here.

14A to 14D are schematic cross-sectional views of the manufacturing process of the display device 10B according to an embodiment of the invention.

Please refer to FIG. 14A. First, a driving backplane 100B is provided. The driving backplane 100A includes a substrate 110, a pixel driving circuit 120, a dielectric layer 130, a first circuit electrode 141 and a first circuit electrode 142.

FIG. 15 is a schematic circuit diagram of a pixel driving circuit 120B according to an embodiment of the present invention. Please refer to FIGS. 14A and 15, the pixel driving circuit 100B of this embodiment can be the same as the aforementioned pixel driving circuit 100A, and will not be repeated here.

14A and FIG. 15, the dielectric layer 130 is disposed on the pixel driving circuit 120B. The pixel driving circuit 120B is located between the dielectric layer 130 and the substrate 110. The first circuit electrodes 141 and 142 and the second circuit electrode 144 are disposed on the dielectric layer 130. The first circuit electrode 141 is electrically connected to the second terminal T2b of the transistor TFT2.

Please refer to FIG. 14B. Next, a first conductive pattern 151 and a first conductive pattern 152 are formed on the first circuit electrode 141 and the first circuit electrode 142 of the driving backplane 100B, respectively, by an electroplating process.

FIG. 16 shows the signal V11 applied to the power line L_VDD of the pixel driving circuit 120B of an embodiment of the present invention during the electroplating process.

FIG. 17 shows the signal V12 applied to the first circuit electrode 142 of an embodiment of the present invention during the electroplating process.

Referring to FIGS. 7B, 9 and 10, in the foregoing embodiment of the display device 10A, during the electroplating process, the signal V11 applied to the power line L_VDD of the pixel driving circuit 120A is substantially equal to the signal V11 applied to the first The signal V12 on the circuit electrode 142; that is, the first signal provided to the first circuit electrode 141 is substantially equal to the first signal provided to the first circuit electrode 142. Please refer to FIG. 14B, FIG. 16 and FIG. 17, however, in this embodiment, the first signal provided to the first circuit electrode 141 and the first signal provided to the first circuit electrode 142 may be different, so that they are formed respectively The thickness H11 of the first conductive pattern 151 and the thickness H12 of the first conductive pattern 152 on the first circuit electrode 141 and the first circuit electrode 142 are different.

Please refer to FIG. 14B, FIG. 15, FIG. 16, and FIG. 17. In this embodiment, during the electroplating process, a gate low voltage is input to the data line DL, and a gate low voltage is input to the scan line GL. The signal V11 of 16 is sent to the power line L_VDD, and the signal V12 of FIG. 17 is input to the first circuit electrode 142. At this time, the first signal provided to the first circuit electrode 141 is substantially equal to the signal V11 in FIG. 16.

The signal V11 includes a plurality of first pulses. The plurality of first pulses of the signal V11 have a first period t11p, and each first pulse has a time length t11. The signal V12 includes a plurality of first pulses, the plurality of first pulses have a second period t12p, and each first pulse signal has a time length t12. In particular, t11p, t11, t12p and t12 satisfy the following formula: (T1/t11p)∙t11≠(T1/t12p)∙t12, where T1 is the time of the first stage of the electroplating process. That is, in the first stage of the same electroplating process, the time during which the first circuit electrode 141 is applied with voltage (that is, within the time T1 of the first stage, the multiple time lengths of the multiple first pulses of the signal V11 The sum of t11) is different from the time during which the voltage is applied to the first circuit electrode 142 (that is, the sum of the multiple time lengths t12 of the multiple first pulses of the signal V12 in the first stage of time T1). Thereby, the amount of electroplating metal ions accumulated on the first circuit electrode 141 is different from the amount of electroplating metal ions accumulated on the first circuit electrode 142, so that the amount of electroplating metal ions accumulated on the first circuit electrode 141 and the first circuit electrode 142 are formed respectively. The thickness H11 of the first conductive pattern 151 and the thickness H12 of the first conductive pattern 152 are different.

For example, in this embodiment, t11p, t11, t12p, and t12 may satisfy the following formula: (T1/t11p)∙t11<(T1/t12p)∙t12, so that the thickness H11 of the first conductive pattern 151 is smaller than the first conductive pattern 151 The thickness of a conductive pattern 152 is H12. However, the present invention is not limited to this. In other embodiments, t11p, t11, t12p, and t12 may also satisfy the following formula: (T1/t11p)∙t11>(T1/t12p)∙t12, so that the first conductive The thickness H11 of the pattern 151 is greater than the thickness H12 of the first conductive pattern 152.

There are many ways to make t11p, t11, t12p and t12 satisfy: (T1/t11p)∙t11≠(T1/t12p)∙t12. For example, in this embodiment, the time length t11 of each first pulse of the signal V11 may be less than the time length t12 of each first pulse of the signal V12, and the first period t11p and the first period t12p may be the same. However, the present invention is not limited to this. In another embodiment, the time length t11 of each first pulse of the signal V11 and the time length t12 of each first pulse of the signal V12 may be the same, and the first period t11p and the first pulse A period t21p may be different; in another embodiment, the time length t11 of each first pulse of the signal V11 and the time length t12 of each first pulse of the signal V12 may be different, and the first period t11p is different from the first period t12p can also be different, as long as t11p, t11, t12p and t12 satisfy the following formula: (T1/t11p)∙t11≠(T1/t12p)∙t12.

Please refer to FIG. 14C. Then, in this embodiment, an electroless plating process may be selectively performed to form the first connection pattern 161 and the first connection pattern 162 on the first conductive pattern 151 and the first conductive pattern 152.

Please refer to FIG. 15D. Finally, the light emitting diode device 200 is transposed on at least one first conductive pattern 151, 152, and the light emitting diode device 200 is electrically connected to the at least one first conductive pattern 151, 152. This completes the display device 10B.

It is worth mentioning that, in this embodiment, the first conductive pattern 151 and the first conductive pattern 152 used to be electrically connected to the light emitting diode element 200 have a thickness difference (ie, H11-H12), and the first The thickness difference between the conductive pattern 151 and the first conductive pattern 152 (ie, H11-H12) can compensate for the height difference between the first electrode 240 and the second electrode 250 of the light emitting diode device 200 (ie, the height h1 minus the height h2) , Thereby improving the transposition yield of the light-emitting diode device 200. For example, in this embodiment, H11, H12, h1, and h2 may satisfy the following formula: (h1-h2)≤(H12-H11), but the present invention is not limited thereto.

10, 10A, 10B: display device 100, 100A, 100B: drive backplane 110: Base 120, 120A, 120B: pixel drive circuit 130: Dielectric layer 131a, 131b, 132a: contact window 141, 142: first circuit electrode 143, 144: second circuit electrode 151, 152: first conductive pattern 151-1, 154-1: Extension 151a, 152a, 153a: top surface 151b, 152b, 153b: side wall 153, 154: second conductive pattern 161, 162: The first connection pattern 163, 164: second connection pattern 171, 172: pads 200: Light-emitting diode element 210: The first type semiconductor layer 220: Type II semiconductor layer 230: active layer 240: first electrode 250: second electrode 300: Electroplated metal C: Capacitance Ca, Cb: one end D1: first length D2: second length DL: Data line d: direction GL: scan line H11, H12, H21, H22, H11’, H22’: thickness h1, h2: height L_VDD: power line L_VSS: common line L_SEL, L_SEN: signal line P141, P142, P143, P144: point TFT1, TFT2, TFT3: Transistor T1a, T2a, T3a: the first end T1b, T2b, T3b: second end T1c, T2c, T3c: control terminal T1, T2: time t11p, t12p: first cycle t21p, t22p: second cycle t11, t21, t12, t22: length of time V11, V12, V21, V22: signal Xpad: first pitch Xppath: second spacing I-I’, II-II’: Sectional line

1A to 1D are schematic cross-sectional views of the manufacturing process of the display device 10 according to an embodiment of the invention. FIG. 2 is a schematic circuit diagram of a pixel driving circuit 120 according to an embodiment of the invention. FIG. 3 shows the electroplating process of the driving backplane 100 according to an embodiment of the present invention. FIG. 4 shows the signal V11 applied to the signal line L_SEN of the pixel driving circuit 120 of an embodiment of the present invention during the electroplating process. FIG. 5 shows the signal V12 applied to the common line L_VSS of the pixel driving circuit 120 according to an embodiment of the present invention during the electroplating process. FIG. 6 shows the signal V21 applied to the power line L_VDD of the pixel driving circuit 120 of an embodiment of the present invention during the electroplating process. 7A to 7E are schematic cross-sectional views of the manufacturing process of the display device 10A according to an embodiment of the invention. FIG. 8 is a schematic circuit diagram of a pixel driving circuit 120A according to an embodiment of the invention. FIG. 9 shows the signal V11 applied to the power line L_VDD of the pixel driving circuit 120A of an embodiment of the present invention during the electroplating process. FIG. 10 shows the signal V12 applied to the first circuit electrode 142 of an embodiment of the present invention during the electroplating process. FIG. 11 shows the signal V22 applied to the common line L_VSS of the pixel driving circuit 120A of an embodiment of the present invention during the electroplating process. 12 is a schematic top view of the first circuit electrode 141, the first circuit electrode 142, the second circuit electrode 144, the first conductive pattern 151, the first conductive pattern 152, and the second conductive pattern 154 of FIG. 7B. 13 is a schematic top view of the first circuit electrode 141, the first circuit electrode 142, the second circuit electrode 144, the first conductive pattern 151, the first conductive pattern 152, and the second conductive pattern 154 of FIG. 7C. 14A to 14D are schematic cross-sectional views of the manufacturing process of the display device 10B according to an embodiment of the invention. FIG. 15 is a schematic circuit diagram of a pixel driving circuit 120B according to an embodiment of the present invention. FIG. 16 shows the signal V11 applied to the power line L_VDD of the pixel driving circuit 120B of an embodiment of the present invention during the electroplating process. FIG. 17 shows the signal V12 applied to the first circuit electrode 142 of an embodiment of the present invention during the electroplating process.

10: Display device

100: drive backplane

110: Base

120: Pixel drive circuit

130: Dielectric layer

131a, 131b, 132a: contact window

141, 142: first circuit electrode

143: second circuit electrode

151, 152: first conductive pattern

153: second conductive pattern

161, 162: The first connection pattern

163: The second connection pattern

171, 172: pads

200: Light-emitting diode element

210: The first type semiconductor layer

220: Type II semiconductor layer

230: active layer

240: first electrode

250: second electrode

H11, H12, H21: thickness

Claims (12)

A display device includes: A base A pixel driving circuit is disposed on the substrate, wherein the pixel driving circuit includes: A power cord; A transistor having a first end, a second end and a control end, wherein the first end of the transistor is electrically connected to the power line; and A common line; A dielectric layer disposed on the pixel driving circuit; At least one first circuit electrode disposed on the dielectric layer and electrically connected to at least one of the second end of the transistor and the common line; At least one second circuit electrode disposed on the dielectric layer and electrically connected to at least one of the power line and the common line; At least one first conductive pattern disposed on the at least one first circuit electrode and electrically connected to the at least one first circuit electrode; At least one second conductive pattern is disposed on the at least one second circuit electrode and is electrically connected to the at least one second circuit electrode, wherein the material of the at least one first conductive pattern and the material of the at least one second conductive pattern The material is the same, and the thickness of the at least one first conductive pattern and the thickness of the at least one second conductive pattern have a difference; and A light emitting diode element is disposed on the at least one first conductive pattern and is electrically connected to the at least one first conductive pattern. The display device according to claim 1, wherein the at least one first circuit electrode includes a plurality of first circuit electrodes, and the first circuit electrodes are respectively electrically connected to the second end of the transistor and the common line, The first circuit electrodes have a first distance in a direction; the at least one second circuit electrode includes a second circuit electrode electrically connected to the common line, and the second circuit electrode is electrically connected to the common line One of the first circuit electrodes is structurally separated and has a second pitch in the direction, and the second pitch is smaller than the first pitch. The display device according to claim 2, wherein the at least one first conductive pattern includes a plurality of first conductive patterns respectively disposed on the first circuit electrodes; the at least one second conductive pattern includes a plurality of first conductive patterns disposed on the second A second conductive pattern on the circuit electrode; the first conductive pattern electrically connected to the common line is in contact with the second conductive pattern. The display device according to claim 2, wherein a first conductive pattern electrically connected to the second end of the transistor has an extension part beyond a first circuit electrode, and the extension of the first conductive pattern The portion has a first length in the direction, the second conductive pattern has an extension that extends beyond the second circuit electrode, the extension of the second conductive pattern has a second length in the direction, and the first The second distance is less than or equal to the sum of the first length and the second length. The display device according to claim 2, wherein a first conductive pattern electrically connected to the second end of the second transistor has an extension part that exceeds a first circuit electrode, and the first conductive pattern The extension portion has a first length in the direction, and the first distance is greater than twice the first length. The display device according to claim 1, wherein the at least one first circuit electrode includes a plurality of first circuit electrodes electrically connected to the second end of the transistor and the common line, and the at least one first conductive The pattern includes a plurality of first conductive patterns respectively disposed on the first circuit electrodes, a first electrode and a second electrode of the light emitting diode element are electrically connected to the first conductive patterns, and the The thicknesses of the first conductive patterns are different. The display device according to claim 1, wherein the absolute value of the difference is greater than or equal to

. The display device according to claim 1, wherein the absolute value of the difference is greater than or equal to

And less than or equal to

. A method for manufacturing a display device includes: A driving backplane is provided, the driving backplane includes a substrate, a pixel driving circuit, a dielectric layer, at least one first circuit electrode and at least one second circuit electrode, and the pixel driving circuit is disposed on the substrate, The pixel driving circuit includes a power line, a transistor and a common line. The transistor has a first end, a second end and a control end. The first end of the transistor is electrically connected to the power source Line, the dielectric layer is disposed on the pixel driving circuit, the at least one first circuit electrode is disposed on the dielectric layer and electrically connected to at least one of the second end of the transistor and the common line , The at least one second circuit electrode is disposed on the dielectric layer and is electrically connected to at least one of the power line and the common line; The at least one first conductive pattern and the at least one second conductive pattern are respectively formed on the at least one first circuit electrode and the at least one second circuit electrode of the driving backplane by an electroplating process, wherein the at least one first The material of the conductive pattern is the same as the material of the at least one second conductive pattern, and the thickness of the at least one first conductive pattern and the thickness of the at least one second conductive pattern have a difference; and A light emitting diode element is placed on the at least one first conductive pattern, and the light emitting diode element is electrically connected to the at least one first conductive pattern. The method of manufacturing a display device according to claim 9, wherein the at least one first conductive pattern and the at least one second circuit electrode are respectively formed on the at least one first circuit electrode and the at least one second circuit electrode of the driving backplane by the electroplating process The steps of the at least one second conductive pattern include: Provide at least one first signal and at least one second signal to the at least one first circuit electrode and the at least one second circuit electrode, respectively, wherein the electroplating process includes at least a first stage; in the first stage of the electroplating process The at least one first signal and the at least one second signal respectively include a plurality of first pulses and a plurality of second pulses, the first pulses have a first period t1p, and each of the first pulses has a time length t1, the second pulses have a second period t2p, each of the second pulse signals has a time length t2, T1 is the time of the first stage of the electroplating process, and (T1/t1p)∙t1≠( T1/t2p)∙t2. The manufacturing method of the display device according to claim 10, wherein the first period t1p is different from the second period t2p. The method of manufacturing a display device according to claim 10, wherein the at least one first conductive pattern and the at least one second circuit electrode are respectively formed on the at least one first circuit electrode and the at least one second circuit electrode of the driving backplane by the electroplating process The step of the at least one second conductive pattern further includes: After a first conductive pattern is in contact with a second conductive pattern, the electroplating process enters a second stage following the first stage; in the second stage of the electroplating process, the first signal and the first The two signals are essentially the same.

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