TWI742735B - Pixel array substrate - Google Patents

Abstract

A pixel array substrate includes a base, signal lines, pixel structures and at least one first compensation capacitor. The signal lines are disposed on the base and arranged in an identical direction, wherein the signal lines include at least one first signal line disposed on a first region of the base. The pixel structures are electrically connected to the signal lines. The at least one first compensation capacitor is electrically connected to the at least one first signal line. Each of the at least one first compensation capacitor includes a first semiconductor pattern, a first conductive pattern and an insulating layer disposed between the first semiconductor pattern and the first conductive pattern.

Description

Pixel array substrate

The present invention relates to a pixel array substrate.

With the rapid development of science and technology, display panels have become ubiquitous in today’s society and are widely used in various electronic products, such as smart phones (smart mobile phones), personal digital assistants (PDAs), and tablet computers. (tablet PC) or Virtual Reality (VR) device.

In order to meet the needs of users, the display panel is usually integrated with other components (for example, a speaker, an optical sensor, or a lens). However, in order to integrate with other components, the display area of the display panel is usually of irregular shape in design. Therefore, during display, the scan line in the display area is prone to uneven capacitance, which causes the brightness of different display areas. Poor, affect the display effect.

The invention provides a pixel array substrate with good performance.

The pixel array substrate of the present invention includes a substrate, a plurality of signal lines, a plurality of pixel structures, and at least one first compensation capacitor. The substrate has a first zone and a first zone outside The second district. A plurality of signal lines are arranged on the substrate and arranged in the same direction, wherein the plurality of signal lines include at least one first signal line and a plurality of second signal lines, and at least one first signal line is arranged on the first area of the substrate , And a plurality of second signal lines are arranged on the second area of the substrate. The multiple pixel structures are electrically connected to multiple signal lines. At least one first compensation capacitor is electrically connected to at least one first signal line. Each of the at least one first compensation capacitor includes a first semiconductor pattern, a first conductive pattern, and an insulating layer disposed between the first semiconductor pattern and the first conductive pattern.

In an embodiment of the present invention, at least one first conductive pattern of at least one first compensation capacitor is electrically connected to at least one first signal line, and at least one first semiconductor pattern of at least one first compensation capacitor is electrically connected It is connected to a driving circuit.

In an embodiment of the present invention, at least one first signal line is a plurality of first signal lines, at least one first compensation capacitor is a plurality of first compensation capacitors, and a plurality of first conductive patterns of the plurality of first compensation capacitors The plurality of first semiconductor patterns of the plurality of first compensation capacitors are respectively electrically connected to the plurality of first signal lines, and the plurality of first semiconductor patterns of the plurality of first compensation capacitors are electrically connected to the driving circuit. The first semiconductor pattern of a first compensation capacitor and the first conductive pattern have a first potential difference, the first semiconductor pattern of the other first compensation capacitor and the first conductive pattern have a second potential difference, and the absolute value of the first potential difference is greater than The absolute value of the second potential difference.

In an embodiment of the present invention, the aforementioned first semiconductor pattern of a first compensation capacitor is directly connected to the first semiconductor pattern of another first compensation capacitor.

In an embodiment of the present invention, the above-mentioned substrate further has a first area and a third area outside the second area. The pixel array substrate is adapted to be bent along a reference axis, and the reference axis is located in the third area. The multiple signal lines further include a third signal disposed on the third area of the substrate Number line. The pixel array substrate further includes a second compensation capacitor, which is electrically connected to the third signal line. The second compensation capacitor includes a second semiconductor pattern, a second conductive pattern, and an insulating layer disposed between the second semiconductor pattern and the second conductive pattern.

In an embodiment of the present invention, the first semiconductor pattern and the first conductive pattern of the first compensation capacitor have a first potential difference, and the second semiconductor pattern and the second conductive pattern of the second compensation capacitor have a third potential difference, and The absolute value of the first potential difference is greater than the absolute value of the third potential difference.

In an embodiment of the present invention, the vertical projection area of the first semiconductor pattern of the first compensation capacitor on the substrate is larger than the vertical projection area of the second semiconductor pattern of the second compensation capacitor on the substrate.

In an embodiment of the present invention, the distance between the second semiconductor pattern of the second compensation capacitor and the second conductive pattern is greater than the distance between the first semiconductor pattern of the first compensation capacitor and the first conductive pattern.

In an embodiment of the present invention, the above-mentioned first semiconductor pattern of the first compensation capacitor is located between the first conductive pattern and the substrate.

In an embodiment of the present invention, the above-mentioned first conductive pattern of the first compensation capacitor is located between the first semiconductor pattern and the substrate.

10, 10A, 10B, 10B’, 10B”, 10D, 10E: pixel array substrate

110: Base

110a: Non-straight edge

112, 141: first conductive pattern

114, 130, 150: insulating layer

121: The first semiconductor pattern

122: second semiconductor pattern

142, 162: second conductive pattern

Cm1, Cm1’, Cm1-1, Cm1-2: first compensation capacitor

Cm2: second compensation capacitor

Cst: storage capacitor

DL, SL: signal line

D1, D3: distance

IC: drive circuit

L1: The first peripheral routing

L2: Second peripheral routing

OLED: organic light emitting diode element

PX: Pixel structure

R1: Zone 1

R2: Zone 2

R3: Zone 3

SL1, SL1-1, SL1-1: the first signal line

SL2: second signal line

SL3: The third signal line

T1: The first transistor

T1a, T2a: first end

T1b, T2b: second end

T1c, T2c: control terminal

T2: second transistor

x: reference axis

y: direction

FIG. 1 is a schematic top view of a pixel array substrate 10 according to an embodiment of the invention.

Figure 2 shows the pixel structure PX and the first compensation circuit located in the first region R1 of Figure 1 Equivalent circuit of capacity Cm1.

FIG. 3 shows an equivalent circuit of the pixel structure PX located in the second region R2 of FIG. 1.

4 is a schematic cross-sectional view of the first compensation capacitor Cm1 of the pixel array substrate 10 in FIG. 1.

FIG. 5 is a schematic top view of the first compensation capacitor Cm1 of the pixel array substrate 10 of FIG. 1.

FIG. 6 shows the relationship between the compensation capacitor and the cross voltage of the compensation capacitor according to an embodiment of the present invention.

FIG. 7 is a schematic top view of a pixel array substrate 10A according to an embodiment of the invention.

FIG. 8 is a schematic cross-sectional view of the second compensation capacitor Cm2 of the pixel array substrate 10A of FIG. 7.

FIG. 9 is a schematic top view of a pixel array substrate 10B according to an embodiment of the invention.

10 is a schematic cross-sectional view of the first compensation capacitor Cm1 of the pixel array substrate 10B of FIG. 9.

FIG. 11 is a schematic cross-sectional view of the second compensation capacitor Cm2 of the pixel array substrate 10B of FIG. 9.

FIG. 12 is a schematic top view of a pixel array substrate 10B' according to an embodiment of the invention.

FIG. 13 is a schematic top view of the first compensation capacitor Cm1 of the pixel array substrate 10B' of FIG. 12.

FIG. 14 is a schematic top view of the second compensation capacitor Cm2 of the pixel array substrate 10B' of FIG. 12.

FIG. 15 is a schematic top view of a pixel array substrate 10B" according to an embodiment of the present invention.

FIG. 16 is a schematic cross-sectional view of the first compensation capacitor Cm1 of the pixel array substrate 10B" of FIG. 15.

FIG. 17 is a schematic cross-sectional view of the second compensation capacitor Cm2 of the pixel array substrate 10B″ of FIG. 15.

FIG. 18 is a schematic top view of a pixel array substrate 10D according to an embodiment of the invention.

FIG. 19 is a schematic top view of a plurality of first compensation capacitors Cm1-1 and Cm1-2 of the pixel array substrate 10D of FIG. 18.

FIG. 20 is a schematic cross-sectional view of a pixel array substrate 10E according to an embodiment of the invention.

Reference will now be made in detail to the exemplary embodiments of the present invention, and examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and descriptions to indicate the same or similar parts.

It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connected" can refer to physical and/or electrical connection. Furthermore, "electricity "Sexual connection" or "coupling" may mean that there are other elements between two elements.

As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within the acceptable deviation range of the specific value determined by a person of ordinary skill in the art, taking into account the measurement in question and the A certain amount of measurement-related error (ie, the limitation of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "about", "approximately" or "substantially" as used herein can be based on optical properties, etching properties or other properties to select a more acceptable range of deviation or standard deviation, and not one standard deviation can be applied to all properties .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of related technologies and the present invention, and will not be interpreted as idealized or excessive The formal meaning, unless explicitly defined as such in this article.

FIG. 1 is a schematic top view of a pixel array substrate 10 according to an embodiment of the invention.

FIG. 2 shows an equivalent circuit of the pixel structure PX and the first compensation capacitor Cm1 located in the first region R1 of FIG. 1.

FIG. 3 shows an equivalent circuit of the pixel structure PX located in the second region R2 of FIG. 1.

FIG. 4 is a diagram of the first compensation capacitor Cm1 of the pixel array substrate 10 of FIG. 1 Schematic cross-section.

FIG. 5 is a schematic top view of the first compensation capacitor Cm1 of the pixel array substrate 10 of FIG. 1.

6 shows the relationship between the compensation capacitor and the cross voltage of the compensation capacitor according to an embodiment of the present invention, wherein the compensation capacitor includes a semiconductor pattern, a conductive pattern, and at least one insulating layer disposed between the semiconductor pattern and the conductive pattern.

1, the pixel array substrate 10 includes a base 110 having a first region R1 and a second region R2 outside the first region R1. For example, in this embodiment, the first area R1 may be a special-shaped area with a non-linear edge 110a, such as but not limited to a notch area, and the second area R2 may be a normal display area.

In this embodiment, the material of the substrate 110 may be glass, quartz, organic polymers, or opaque/reflective materials (for example, wafers, ceramics, or other applicable materials), or other applicable materials. Material.

The pixel array substrate 10 further includes a plurality of signal lines SL, which are disposed on the base 110 and arranged in the same direction y. The plurality of signal lines SL includes a first signal line SL1 and a plurality of second signal lines SL2. The first signal line SL1 is disposed on the first region R1 of the substrate 110. A plurality of second signal lines SL2 are disposed on the second region R2 of the substrate 110.

In this embodiment, the pixel array substrate 10 further includes a plurality of signal lines DL, which are arranged alternately with the plurality of signal lines SL. The signal line DL and the signal line SL belong to two different conductive layers, respectively. For example, in this embodiment, the signal line SL may be a scan line, and the signal line DL may be a data line.

Please refer to Figure 1, Figure 2 and Figure 3, the pixel array substrate 10 also includes a plurality of The pixel structure PX is electrically connected to a plurality of signal lines SL.

For example, in this embodiment, each pixel structure PX may include a first transistor T1, a second transistor T2, a storage capacitor Cst, and an organic light emitting diode element OLED, wherein the first transistor T1 One end T1a is electrically connected to a corresponding signal line DL, the control end T1c of the first transistor T1 is electrically connected to a corresponding signal line SL, and the second end T1b of the first transistor T1 is electrically connected to the storage capacitor Cst, the storage capacitor Cst is electrically connected to the control terminal T2c of the second transistor T2, the first terminal T2a of the second transistor T2 is electrically connected to a power line (not shown) with a high system potential, and the second transistor The second terminal T2b of the crystal T2 is electrically connected to the anode (not shown) of the organic light-emitting diode element OLED, and the cathode (not shown) of the organic light-emitting diode element OLED is electrically connected to the system low potential A common line (not shown). However, the present invention is not limited to this. In other embodiments, the pixel structure PX may also be of other types.

1, the pixel array substrate 10 further includes a first compensation capacitor Cm1, which is electrically connected to the first signal line SL1. 4 and 5, the first compensation capacitor Cm1 includes a first semiconductor pattern 121, a first conductive pattern 141, and an insulating layer 130 disposed between the first semiconductor pattern 121 and the first conductive pattern 141.

Through the arrangement of the first compensation capacitor Cm1, the capacitance loaded by the first signal line SL1 located in the first region R1 can be close to (or substantially equal to) the capacitance loaded by the second signal line SL2 located in the second region R2 .

Please refer to FIG. 1. For example, in this embodiment, the number of pixel structures PX that are electrically connected to the first signal line SL1 is small (FIG. 1 takes 6 as an example). The number of pixel structures PX electrically connected to the second signal line SL2 is relatively large (14 as an example in FIG. 1). Therefore, the capacitance between the first signal line SL1 and the plurality of pixel structures PX electrically connected to it is relatively small, while the capacitance between the second signal line SL2 and the plurality of pixel structures PX electrically connected to it is relatively large. . Through the compensation of the first compensation capacitor Cm1, the capacitance between the first signal line SL1 and the plurality of pixel structures PX electrically connected thereto and the equivalent capacitance formed by the first compensation capacitor Cm1 can be close to (or substantially equal to) ) The capacitance between the second signal line SL2 and the plurality of pixel structures PX electrically connected thereto; that is, the capacitance loaded by the first signal line SL1 can be close to (or substantially equal to) the second signal line SL2 The capacitance of the load.

4 and 6, it is worth noting that the first compensation capacitor Cm1 includes a first semiconductor pattern 121, a first conductive pattern 141, and an insulating layer 130 disposed between the first semiconductor pattern 121 and the first conductive pattern 141 , And the size of the first compensation capacitor Cm1 is related to the voltage across the first compensation capacitor Cm1 (ie, the potential difference between the first semiconductor pattern 121 and the first conductive pattern 141). In other words, the size of the first compensation capacitor Cm1 can be changed by adjusting the cross voltage of the first compensation capacitor Cm1. In this way, the cross voltage of the first compensation capacitor Cm1 can be set according to the actual condition of each pixel array substrate 10, so that the first compensation capacitor Cm1 has the required compensation capacitance value, and the first signal line SL1 The loaded capacitance is close to (or substantially equal to) the capacitance loaded by the second signal line SL2, which reduces the brightness difference between the first region R1 and the second region R2.

Specifically, in this embodiment, the first conductive pattern 141 of the first compensation capacitor Cm1 is electrically connected to the first signal line SL1, and the first compensation capacitor Cm1 The first semiconductor pattern 121 is electrically connected to a driving circuit IC. The cross voltage of the first compensation capacitor Cm1 can be set through the driving circuit IC, so that the first compensation capacitor Cm1 has the required compensation capacitance value.

It must be noted here that the following embodiments use the element numbers and part of the content of the foregoing embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

FIG. 7 is a schematic top view of a pixel array substrate 10A according to an embodiment of the invention.

FIG. 8 is a schematic cross-sectional view of the second compensation capacitor Cm2 of the pixel array substrate 10A of FIG. 7.

The pixel array substrate 10A of FIGS. 7 and 8 is similar to the pixel array substrate 10 of FIG. 1, and the differences between the two are as follows. Referring to FIG. 7, in this embodiment, the pixel array substrate 10A has a third region R3, the pixel array substrate 10A is adapted to bend along a reference axis x, and the reference axis x is located in the third region R3 of the pixel array substrate 10A superior. In short, the pixel array substrate 10A has a bendable third region R3, and the third region R3 is located in the second region R2.

Referring to FIG. 7, the plurality of signal lines SL of the pixel array substrate 10A includes a third signal line SL3, which is disposed on the third region R3 of the base 110. The pixel array substrate 10A further includes a second compensation capacitor Cm2, which is electrically connected to the third signal line SL3. Referring to FIGS. 7 and 8, the second compensation capacitor Cm2 includes a second semiconductor pattern 122, a second conductive pattern 142, and a second semiconductor pattern 122 and a second conductive pattern. Case 142 between the insulating layer 130.

For example, in this embodiment, the number of pixel structures PX that are electrically connected to the third signal line SL3 and the number of pixel structures PX that are electrically connected to the second signal line SL2 can be the same; as a pixel array substrate When 10A is not bent, the capacitance loaded by the third signal line SL3 is approximately equal to the capacitance loaded by the second signal line SL2, and the brightness of the third region R3 is substantially equal to the brightness of the second region R2; however, when When the pixel array substrate 10A is bent along the reference axis x located in the third region R3, the film thicknesses of the components (for example, the signal line SL, the pixel structure PX, etc.) on the third region R3 change, resulting in the third signal line The size of the capacitance loaded by SL3 changes, which in turn causes the brightness difference between the second region R2 and the third region R3. At this time, through the compensation of the second compensation capacitor Cm2, the capacitance between the third signal line SL3 and the plurality of pixel structures PX electrically connected to it and the equivalent capacitance formed by the second compensation capacitor Cm2 will be close to (or It is substantially equal to) the capacitance between the second signal line SL2 and the plurality of pixel structures PX electrically connected thereto. That is, through the compensation of the second compensation capacitor Cm2, the capacitance loaded by the third signal line SL3 can be close to (or substantially equal to) the capacitance loaded by the second signal line SL2. Thereby, the brightness difference between the second region R2 and the third region R3 caused by bending can be reduced.

FIG. 9 is a schematic top view of a pixel array substrate 10B according to an embodiment of the invention.

10 is a schematic cross-sectional view of the first compensation capacitor Cm1 of the pixel array substrate 10B of FIG. 9.

FIG. 11 is the second compensation capacitor Cm2 of the pixel array substrate 10B of FIG. 9 Schematic diagram of the cross-section.

The pixel array substrate 10B of FIG. 9 is similar to the pixel array substrate 10 of FIG. 1, and the difference between the two is: in the embodiment of FIG. , There is also a third zone R3. The pixel array substrate 10B is adapted to be bent along the reference axis x, and the reference axis x is located in the third region R3 of the pixel array substrate 10B. The third region R3 of the pixel array substrate 10B is a bendable region, and the third region R3 is located between the first region R1 and a part of the second region R2.

Referring to FIG. 9, the multiple signal lines SL of the pixel array substrate 10B include not only the first signal line SL1 and the multiple second signal lines SL2 respectively disposed on the first region R1 and the second region R2, but also include The third signal line SL3 on the third area R3. In addition to the first compensation capacitor Cm1 electrically connected to the first signal line SL1, the pixel array substrate 10B further includes a second compensation capacitor Cm2 electrically connected to the third signal line SL3.

9 and 10, the first compensation capacitor Cm1 includes a first semiconductor pattern 121, a first conductive pattern 141, and an insulating layer 130 disposed between the first semiconductor pattern 121 and the first conductive pattern 141.

9 and 11, similarly, the second compensation capacitor Cm2 includes a second semiconductor pattern 122, a second conductive pattern 142, and an insulating layer 130 disposed between the second semiconductor pattern 122 and the second conductive pattern 142.

In this embodiment, the first area R1 is a special-shaped area, and the third area R3 is a bendable area. The size of the compensation capacitor required by the first area R1 (that is, the compensation capacitance value of the first compensation capacitor Cm1) is the same as that of the third area R1. The size of the compensation capacitor required for zone R3 (i.e. the second compensation The compensation capacitance value of the capacitor Cm2) is different.

For example, in this embodiment, although the structure of the first compensation capacitor Cm1 is substantially the same as the structure of the second compensation capacitor Cm2, the driver circuit IC is used to apply different cross voltages to the first compensation capacitor Cm1 and the second compensation capacitor Cm1. The capacitor Cm2 can make the first compensation capacitor Cm1 and the second compensation capacitor Cm2 have different compensation capacitance values. Thereby, even if the size of the compensation capacitor required by the first region R1 is different from the size of the compensation capacitor required by the third region R3, the brightness difference between the first region R1 and the second region R2 and the third region R3 can be reduced at the same time. The brightness difference with the second area R2.

For example, in this embodiment, the first semiconductor pattern 121 and the first conductive pattern 141 of the first compensation capacitor Cm1 have a first potential difference, and the second semiconductor pattern 122 and the second conductive pattern 142 of the second compensation capacitor Cm2 have The third potential difference, and the absolute value of the first potential difference is greater than the absolute value of the third potential difference. In this way, the first compensation capacitor Cm1 can be made larger than the second compensation capacitor Cm2, thereby simultaneously reducing the brightness difference between the first region R1 and the second region R2 and the brightness difference between the third region R3 and the second region R2.

FIG. 12 is a schematic top view of a pixel array substrate 10B' according to an embodiment of the invention.

FIG. 13 is a schematic top view of the first compensation capacitor Cm1 of the pixel array substrate 10B' of FIG. 12.

FIG. 14 is a schematic top view of the second compensation capacitor Cm2 of the pixel array substrate 10B' of FIG. 12.

The pixel array substrate 10B' of FIGS. 12, 13 and 14 is similar to the pixel array substrate 10B of FIGS. 9, 10 and 11, and the differences between the two are as follows. Please refer to the picture 12. As shown in FIGS. 13 and 14, in this embodiment, the first compensation capacitor Cm1 and the second compensation capacitor Cm2 respectively located in the first region R1 and the third region R3 have different structures.

Specifically, in this embodiment, the vertical projection area of the first semiconductor pattern 121 of the first compensation capacitor Cm1 on the substrate 110 is larger than the vertical projection area of the second semiconductor pattern 122 of the second compensation capacitor Cm2 on the substrate 110 area. In this way, the first compensation capacitor Cm1 can be made larger than the second compensation capacitor Cm2, thereby simultaneously reducing the brightness difference between the first region R1 and the second region R2 and the brightness difference between the third region R3 and the second region R2.

FIG. 15 is a schematic top view of a pixel array substrate 10B" according to an embodiment of the present invention.

FIG. 16 is a schematic cross-sectional view of the first compensation capacitor Cm1 of the pixel array substrate 10B" of FIG. 15.

FIG. 17 is a schematic cross-sectional view of the second compensation capacitor Cm2 of the pixel array substrate 10B″ of FIG. 15.

The pixel array substrate 10B" of FIGS. 15, 16 and 17 is similar to the pixel array substrate 10B of FIGS. 9, 10, and 11, and the differences between the two are as follows. Please refer to FIGS. 15, 16 and 17, in In this embodiment, the first compensation capacitor Cm1 and the second compensation capacitor Cm2 respectively located in the first region R1 and the third region R3 have different structures.

Specifically, in this embodiment, the insulating layer 130 is sandwiched between the first semiconductor pattern 121 and the first conductive pattern 141 of the first compensation capacitor Cm1, and the second semiconductor pattern 122 and the second conductive pattern 122 of the second compensation capacitor Cm2 are interposed therebetween. In addition to the insulating layer 130, another insulating layer 150 is sandwiched between the patterns 162, so that the second compensation capacitor Cm2 The distance D3 between the second semiconductor 122 and the second conductive pattern 162 is greater than the distance D1 between the first semiconductor pattern 121 and the first conductive pattern 141 of the first compensation capacitor Cm1. In this way, the second compensation capacitor Cm2 can also be made smaller than the first compensation capacitor Cm1, thereby simultaneously reducing the brightness difference between the first region R1 and the second region R2 and the brightness difference between the third region R3 and the second region R2.

FIG. 18 is a schematic top view of a pixel array substrate 10D according to an embodiment of the invention.

FIG. 19 is a schematic top view of a plurality of first compensation capacitors Cm1 of the pixel array substrate 10D of FIG. 18.

The pixel array substrate 10D of FIGS. 18 and 19 is similar to the pixel array substrate 10 of FIG. 1, and the differences between the two are as follows. Referring to FIGS. 18 and 19, in this embodiment, the pixel array substrate 10D further includes a plurality of first compensation capacitors Cm1-1, Cm1-2, which are connected to a plurality of first signal lines SL1-1, SL1-2, respectively. Electrical connection. The number of pixel structures PX electrically connected to the first signal line SL1-1 is relatively small, and the number of pixel structures PX electrically connected to the first signal line SL1-2 is relatively large. Each first compensation capacitor Cm1-1, Cm1-2 includes a first semiconductor pattern 121, a first conductive pattern 141, and an insulating layer 130 disposed between the first semiconductor pattern 121 and the first conductive pattern 141 (refer to FIG. 4 ).

In this embodiment, the first semiconductor pattern 121 of the first compensation capacitor Cm1-1 and a first semiconductor pattern 121 of the first compensation capacitor Cm1-2 can be directly connected. In this embodiment, the first semiconductor pattern 121 of the first compensation capacitor Cm1-1 is electrically connected to the driving circuit IC through a first peripheral trace L1 to have a first electrical Potential difference; the first semiconductor pattern 121 of the first compensation capacitor Cm1-2 is electrically connected to the driving circuit IC through a second peripheral wiring L2 to have a second potential difference, wherein the first potential difference is greater than the second potential difference. By adjusting the above potential difference, the desired voltage/capacitance gradient change can be achieved, so as to reduce the brightness difference between the first region R1 and the second region R2, and reduce the number of first compensation capacitors Cm1-1, Cm1-2 required Layout (layout) space.

FIG. 20 is a schematic cross-sectional view of a pixel array substrate 10E according to an embodiment of the invention. The pixel array substrate 10E of FIG. 20 is similar to the pixel array substrate 10 of FIG. 4, and the difference between the two is that the structure of the first compensation capacitor Cm1' in FIG.

Specifically, in the embodiment of FIG. 4, the first semiconductor pattern 121 of the first compensation capacitor Cm1 is located between the first conductive pattern 141 and the substrate 110. That is to say, in the embodiment of FIG. 4, the first conductive pattern 141 of the first compensation capacitor Cm1 is made by using a conductive layer disposed above the first semiconductor pattern 121. In the embodiment of FIG. 20, the first compensation capacitor Cm1' includes a first conductive pattern 112, a first semiconductor pattern 121, and an insulating layer 114 located between the first semiconductor pattern 121 and the first conductive pattern 112. The difference is that in the embodiment of FIG. 20, the first conductive pattern 112 of the first compensation capacitor Cm1' is located between the first semiconductor pattern 121 and the substrate 110. That is, in the embodiment of FIG. 20, the first conductive pattern 112 of the first compensation capacitor Cm1' is made by using a conductive layer disposed under the first semiconductor pattern 121.

The structure of the first compensation capacitor Cm1' in FIG. 20 can also be used to replace any of the foregoing The first compensation capacitor Cm1 and/or the second compensation capacitor Cm2 of an embodiment.

10: Pixel array substrate

110: Base

110a: Non-straight edge

Cm1: first compensation capacitor

DL, SL: signal line

IC: drive circuit

PX: Pixel structure

R1: Zone 1

R2: Zone 2

SL1: The first signal line

SL2: second signal line

y: direction

Claims (10)

A pixel array substrate includes: a base having a first area and a second area outside the first area; a plurality of signal lines are arranged on the base and arranged in the same direction, wherein the signals The line includes at least one first signal line and a plurality of second signal lines, the at least one first signal line is disposed on the first area of the substrate, and the second signal lines are disposed on the second area of the substrate On; a plurality of pixel structures electrically connected to the signal lines; and at least one first compensation capacitor electrically connected to the at least one first signal line, wherein each of the at least one first compensation capacitor includes: A first semiconductor pattern; a first conductive pattern; and an insulating layer disposed between the first semiconductor pattern and the first conductive pattern. The pixel array substrate according to claim 1, wherein at least one of the first conductive patterns of the at least one first compensation capacitor is electrically connected to the at least one first signal line, and at least one of the first compensation At least one of the first semiconductor patterns of the capacitor is electrically connected to a driving circuit. For the pixel array substrate described in claim 2, wherein the at least one first signal line is a plurality of first signal lines, the at least one first compensation capacitor is a plurality of first compensation capacitors, and the first The multiple first conductive patterns of the compensation capacitor are respectively Are electrically connected to the first signal lines, and the first semiconductor patterns of the first compensation capacitors are electrically connected to the driving circuit; wherein, the first semiconductor pattern of a first compensation capacitor and the first semiconductor pattern are electrically connected to the driving circuit. A conductive pattern has a first potential difference, and the first semiconductor pattern of the first compensation capacitor and the first conductive pattern have a second potential difference, and the first potential difference is greater than the second potential difference. In the pixel array substrate described in item 3 of the scope of patent application, the first semiconductor pattern of one of the first compensation capacitors is directly connected to the first semiconductor pattern of the other first compensation capacitor. The pixel array substrate according to claim 1, wherein the base further has the first area and a third area outside the second area, the pixel array substrate is suitable for bending along a reference axis, the The reference axis is located in the third area, the signal lines further include a third signal line, the third signal line is disposed on the third area of the substrate, and the pixel array substrate further includes: a second compensation capacitor , Electrically connected to the third signal line, wherein the second compensation capacitor includes: a second semiconductor pattern; a second conductive pattern; and an insulating layer disposed between the second semiconductor pattern and the second conductive pattern between. According to the pixel array substrate described in item 5 of the scope of patent application, the first semiconductor pattern and the first conductive pattern of a first compensation capacitor have a first A potential difference, the second semiconductor pattern of the second compensation capacitor and the second conductive pattern have a third potential difference, and the absolute value of the first potential difference is greater than the absolute value of the third potential difference. The pixel array substrate according to claim 5, wherein a vertical projection area of the first semiconductor pattern of the first compensation capacitor on the substrate is larger than that of the second semiconductor pattern of the second compensation capacitor on the substrate The area of the vertical projection of one of the substrates. The pixel array substrate according to claim 5, wherein the distance between the second semiconductor pattern of the second compensation capacitor and the second conductive pattern is greater than the distance between the first semiconductor pattern and the second conductive pattern of the first compensation capacitor The distance of a conductive pattern. The pixel array substrate according to claim 1, wherein the first semiconductor pattern of the first compensation capacitor is located between the first conductive pattern and the substrate. The pixel array substrate according to claim 1, wherein the first conductive pattern of the first compensation capacitor is located between the first semiconductor pattern and the substrate.

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